; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN:     -target-abi=lp64d -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN

define <2 x bfloat> @copysign_v2bf16(<2 x bfloat> %vm, <2 x bfloat> %vs) {
; ZVFBFA-LABEL: copysign_v2bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfsgnj.vv v8, v8, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: copysign_v2bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFBFMIN-NEXT:    vand.vx v9, v9, a0
; ZVFBFMIN-NEXT:    addi a0, a0, -1
; ZVFBFMIN-NEXT:    vand.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vor.vv v8, v8, v9
; ZVFBFMIN-NEXT:    ret
  %r = call <2 x bfloat> @llvm.copysign.v2bf16(<2 x bfloat> %vm, <2 x bfloat> %vs)
  ret <2 x bfloat> %r
}

define <4 x bfloat> @copysign_v4bf16(<4 x bfloat> %vm, <4 x bfloat> %vs) {
; ZVFBFA-LABEL: copysign_v4bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfsgnj.vv v8, v8, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: copysign_v4bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFBFMIN-NEXT:    vand.vx v9, v9, a0
; ZVFBFMIN-NEXT:    addi a0, a0, -1
; ZVFBFMIN-NEXT:    vand.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vor.vv v8, v8, v9
; ZVFBFMIN-NEXT:    ret
  %r = call <4 x bfloat> @llvm.copysign.v4bf16(<4 x bfloat> %vm, <4 x bfloat> %vs)
  ret <4 x bfloat> %r
}

define <8 x bfloat> @copysign_v8bf16(<8 x bfloat> %vm, <8 x bfloat> %vs) {
; ZVFBFA-LABEL: copysign_v8bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vfsgnj.vv v8, v8, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: copysign_v8bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFMIN-NEXT:    vand.vx v9, v9, a0
; ZVFBFMIN-NEXT:    addi a0, a0, -1
; ZVFBFMIN-NEXT:    vand.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vor.vv v8, v8, v9
; ZVFBFMIN-NEXT:    ret
  %r = call <8 x bfloat> @llvm.copysign.v8bf16(<8 x bfloat> %vm, <8 x bfloat> %vs)
  ret <8 x bfloat> %r
}

define <16 x bfloat> @copysign_v16bf16(<16 x bfloat> %vm, <16 x bfloat> %vs) {
; ZVFBFA-LABEL: copysign_v16bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vfsgnj.vv v8, v8, v10
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: copysign_v16bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFBFMIN-NEXT:    vand.vx v10, v10, a0
; ZVFBFMIN-NEXT:    addi a0, a0, -1
; ZVFBFMIN-NEXT:    vand.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vor.vv v8, v8, v10
; ZVFBFMIN-NEXT:    ret
  %r = call <16 x bfloat> @llvm.copysign.v16bf16(<16 x bfloat> %vm, <16 x bfloat> %vs)
  ret <16 x bfloat> %r
}

define <32 x bfloat> @copysign_v32bf32(<32 x bfloat> %vm, <32 x bfloat> %vs) {
; ZVFBFA-LABEL: copysign_v32bf32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    li a0, 32
; ZVFBFA-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; ZVFBFA-NEXT:    vfsgnj.vv v8, v8, v12
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: copysign_v32bf32:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    li a0, 32
; ZVFBFMIN-NEXT:    lui a1, 8
; ZVFBFMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vand.vx v12, v12, a1
; ZVFBFMIN-NEXT:    addi a1, a1, -1
; ZVFBFMIN-NEXT:    vand.vx v8, v8, a1
; ZVFBFMIN-NEXT:    vor.vv v8, v8, v12
; ZVFBFMIN-NEXT:    ret
  %r = call <32 x bfloat> @llvm.copysign.v32bf32(<32 x bfloat> %vm, <32 x bfloat> %vs)
  ret <32 x bfloat> %r
}

define <64 x bfloat> @copysign_v64bf16(<64 x bfloat> %vm, <64 x bfloat> %vs) {
; ZVFBFA-LABEL: copysign_v64bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    li a0, 64
; ZVFBFA-NEXT:    vsetvli zero, a0, e16alt, m8, ta, ma
; ZVFBFA-NEXT:    vfsgnj.vv v8, v8, v16
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: copysign_v64bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    li a0, 64
; ZVFBFMIN-NEXT:    lui a1, 8
; ZVFBFMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
; ZVFBFMIN-NEXT:    vand.vx v16, v16, a1
; ZVFBFMIN-NEXT:    addi a1, a1, -1
; ZVFBFMIN-NEXT:    vand.vx v8, v8, a1
; ZVFBFMIN-NEXT:    vor.vv v8, v8, v16
; ZVFBFMIN-NEXT:    ret
  %r = call <64 x bfloat> @llvm.copysign.v64bf16(<64 x bfloat> %vm, <64 x bfloat> %vs)
  ret <64 x bfloat> %r
}

define <2 x half> @copysign_v2f16(<2 x half> %vm, <2 x half> %vs) {
; CHECK-LABEL: copysign_v2f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vand.vx v9, v9, a0
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    vor.vv v8, v8, v9
; CHECK-NEXT:    ret
  %r = call <2 x half> @llvm.copysign.v2f16(<2 x half> %vm, <2 x half> %vs)
  ret <2 x half> %r
}

define <8 x half> @copysign_v8f16(<8 x half> %vm, <8 x half> %vs) {
; CHECK-LABEL: copysign_v8f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vand.vx v9, v9, a0
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    vand.vx v8, v8, a0
; CHECK-NEXT:    vor.vv v8, v8, v9
; CHECK-NEXT:    ret
  %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %vm, <8 x half> %vs)
  ret <8 x half> %r
}

define <32 x half> @copysign_v32f16(<32 x half> %vm, <32 x half> %vs) {
; CHECK-LABEL: copysign_v32f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    lui a1, 8
; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT:    vand.vx v12, v12, a1
; CHECK-NEXT:    addi a1, a1, -1
; CHECK-NEXT:    vand.vx v8, v8, a1
; CHECK-NEXT:    vor.vv v8, v8, v12
; CHECK-NEXT:    ret
  %r = call <32 x half> @llvm.copysign.v32f16(<32 x half> %vm, <32 x half> %vs)
  ret <32 x half> %r
}

define <64 x half> @copysign_v64f16(<64 x half> %vm, <64 x half> %vs) {
; CHECK-LABEL: copysign_v64f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 64
; CHECK-NEXT:    lui a1, 8
; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT:    vand.vx v16, v16, a1
; CHECK-NEXT:    addi a1, a1, -1
; CHECK-NEXT:    vand.vx v8, v8, a1
; CHECK-NEXT:    vor.vv v8, v8, v16
; CHECK-NEXT:    ret
  %r = call <64 x half> @llvm.copysign.v64f16(<64 x half> %vm, <64 x half> %vs)
  ret <64 x half> %r
}