; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN:     -target-abi=ilp32d -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+experimental-zvfbfa \
; RUN:     -target-abi=lp64d -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfhmin,+zvfbfmin -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s \
; RUN:     | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN

define <1 x bfloat> @v1bf16(<1 x bfloat> %va) {
; ZVFBFA-LABEL: v1bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 1, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfneg.v v8, v8
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: v1bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    ret
  %vb = fneg <1 x bfloat> %va
  ret <1 x bfloat> %vb
}

define <2 x bfloat> @v2bf16(<2 x bfloat> %va) {
; ZVFBFA-LABEL: v2bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 2, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfneg.v v8, v8
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: v2bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    ret
  %vb = fneg <2 x bfloat> %va
  ret <2 x bfloat> %vb
}

define <4 x bfloat> @v4bf16(<4 x bfloat> %va) {
; ZVFBFA-LABEL: v4bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 4, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfneg.v v8, v8
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: v4bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    ret
  %vb = fneg <4 x bfloat> %va
  ret <4 x bfloat> %vb
}

define <8 x bfloat> @v8bf16(<8 x bfloat> %va) {
; ZVFBFA-LABEL: v8bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 8, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vfneg.v v8, v8
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: v8bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    ret
  %vb = fneg <8 x bfloat> %va
  ret <8 x bfloat> %vb
}

define <16 x bfloat> @v16bf16(<16 x bfloat> %va) {
; ZVFBFA-LABEL: v16bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetivli zero, 16, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vfneg.v v8, v8
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: v16bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetivli zero, 16, e16, m2, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    ret
  %vb = fneg <16 x bfloat> %va
  ret <16 x bfloat> %vb
}

define <32 x bfloat> @v32bf16(<32 x bfloat> %va) {
; ZVFBFA-LABEL: v32bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    li a0, 32
; ZVFBFA-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; ZVFBFA-NEXT:    vfneg.v v8, v8
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: v32bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    li a0, 32
; ZVFBFMIN-NEXT:    lui a1, 8
; ZVFBFMIN-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a1
; ZVFBFMIN-NEXT:    ret
  %vb = fneg <32 x bfloat> %va
  ret <32 x bfloat> %vb
}

define <64 x bfloat> @v64bf16(<64 x bfloat> %va) {
; ZVFBFA-LABEL: v64bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    li a0, 64
; ZVFBFA-NEXT:    vsetvli zero, a0, e16alt, m8, ta, ma
; ZVFBFA-NEXT:    vfneg.v v8, v8
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: v64bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    li a0, 64
; ZVFBFMIN-NEXT:    lui a1, 8
; ZVFBFMIN-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a1
; ZVFBFMIN-NEXT:    ret
  %vb = fneg <64 x bfloat> %va
  ret <64 x bfloat> %vb
}

define <1 x half> @v1f16(<1 x half> %va) {
; CHECK-LABEL: v1f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT:    vxor.vx v8, v8, a0
; CHECK-NEXT:    ret
  %vb = fneg <1 x half> %va
  ret <1 x half> %vb
}

define <2 x half> @v2f16(<2 x half> %va) {
; CHECK-LABEL: v2f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT:    vxor.vx v8, v8, a0
; CHECK-NEXT:    ret
  %vb = fneg <2 x half> %va
  ret <2 x half> %vb
}

define <8 x half> @v8f16(<8 x half> %va) {
; CHECK-LABEL: v8f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lui a0, 8
; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT:    vxor.vx v8, v8, a0
; CHECK-NEXT:    ret
  %vb = fneg <8 x half> %va
  ret <8 x half> %vb
}

define <32 x half> @v32f16(<32 x half> %va) {
; CHECK-LABEL: v32f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 32
; CHECK-NEXT:    lui a1, 8
; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
; CHECK-NEXT:    vxor.vx v8, v8, a1
; CHECK-NEXT:    ret
  %vb = fneg <32 x half> %va
  ret <32 x half> %vb
}

define <64 x half> @v64f16(<64 x half> %va) {
; CHECK-LABEL: v64f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a0, 64
; CHECK-NEXT:    lui a1, 8
; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
; CHECK-NEXT:    vxor.vx v8, v8, a1
; CHECK-NEXT:    ret
  %vb = fneg <64 x half> %va
  ret <64 x half> %vb
}