; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple riscv64 -mattr=+v,+experimental-zvfbfa -verify-machineinstrs \
; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFBFA
; RUN: llc -mtriple riscv64 -mattr=+v,+zfbfmin,+zvfbfmin -verify-machineinstrs \
; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,NOVLDEP,ZVFBFMIN
; RUN: llc -mtriple riscv64 -mattr=+v,+experimental-zvfbfa,+vl-dependent-latency -verify-machineinstrs \
; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFBFA
; RUN: llc -mtriple riscv64 -mattr=+v,+zfbfmin,+zvfbfmin,+vl-dependent-latency -verify-machineinstrs \
; RUN:   < %s | FileCheck %s --check-prefixes=CHECK,VLDEP,ZVFBFMIN

define <8 x bfloat> @test_vp_splice_v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
; NOVLDEP-LABEL: test_vp_splice_v8bf16:
; NOVLDEP:       # %bb.0:
; NOVLDEP-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
; NOVLDEP-NEXT:    vslidedown.vi v8, v8, 5
; NOVLDEP-NEXT:    addi a0, a0, -5
; NOVLDEP-NEXT:    vslideup.vx v8, v9, a0
; NOVLDEP-NEXT:    ret
;
; VLDEP-LABEL: test_vp_splice_v8bf16:
; VLDEP:       # %bb.0:
; VLDEP-NEXT:    addi a0, a0, -5
; VLDEP-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
; VLDEP-NEXT:    vslidedown.vi v8, v8, 5
; VLDEP-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
; VLDEP-NEXT:    vslideup.vx v8, v9, a0
; VLDEP-NEXT:    ret
  %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
  ret <8 x bfloat> %v
}

define <8 x bfloat> @test_vp_splice_v8bf16_negative_offset(<8 x bfloat> %va, <8 x bfloat> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
; NOVLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:
; NOVLDEP:       # %bb.0:
; NOVLDEP-NEXT:    addi a0, a0, -5
; NOVLDEP-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
; NOVLDEP-NEXT:    vslidedown.vx v8, v8, a0
; NOVLDEP-NEXT:    vslideup.vi v8, v9, 5
; NOVLDEP-NEXT:    ret
;
; VLDEP-LABEL: test_vp_splice_v8bf16_negative_offset:
; VLDEP:       # %bb.0:
; VLDEP-NEXT:    addi a0, a0, -5
; VLDEP-NEXT:    vsetivli zero, 5, e16, m1, ta, ma
; VLDEP-NEXT:    vslidedown.vx v8, v8, a0
; VLDEP-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
; VLDEP-NEXT:    vslideup.vi v8, v9, 5
; VLDEP-NEXT:    ret
  %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 -5, <8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
  ret <8 x bfloat> %v
}

define <8 x bfloat> @test_vp_splice_v8bf16_masked(<8 x bfloat> %va, <8 x bfloat> %vb, <8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
; NOVLDEP-LABEL: test_vp_splice_v8bf16_masked:
; NOVLDEP:       # %bb.0:
; NOVLDEP-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
; NOVLDEP-NEXT:    vslidedown.vi v8, v8, 5, v0.t
; NOVLDEP-NEXT:    addi a0, a0, -5
; NOVLDEP-NEXT:    vsetvli zero, zero, e16, m1, ta, mu
; NOVLDEP-NEXT:    vslideup.vx v8, v9, a0, v0.t
; NOVLDEP-NEXT:    ret
;
; VLDEP-LABEL: test_vp_splice_v8bf16_masked:
; VLDEP:       # %bb.0:
; VLDEP-NEXT:    addi a0, a0, -5
; VLDEP-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
; VLDEP-NEXT:    vslidedown.vi v8, v8, 5, v0.t
; VLDEP-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
; VLDEP-NEXT:    vslideup.vx v8, v9, a0, v0.t
; VLDEP-NEXT:    ret
  %v = call <8 x bfloat> @llvm.experimental.vp.splice.v8bf16(<8 x bfloat> %va, <8 x bfloat> %vb, i32 5, <8 x i1> %mask, i32 %evla, i32 %evlb)
  ret <8 x bfloat> %v
}

define <4 x bfloat> @test_vp_splice_v4b16_with_firstelt(bfloat %first, <4 x bfloat> %vb, <4 x i1> %mask, i32 zeroext %evl) {
; ZVFBFA-LABEL: test_vp_splice_v4b16_with_firstelt:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli zero, a0, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfslide1up.vf v9, v8, fa0, v0.t
; ZVFBFA-NEXT:    vmv1r.v v8, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFMIN-LABEL: test_vp_splice_v4b16_with_firstelt:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    fmv.x.h a1, fa0
; ZVFBFMIN-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
; ZVFBFMIN-NEXT:    vslide1up.vx v9, v8, a1, v0.t
; ZVFBFMIN-NEXT:    vmv1r.v v8, v9
; ZVFBFMIN-NEXT:    ret
  %va = insertelement <4 x bfloat> poison, bfloat %first, i32 0
  %v = call <4 x bfloat> @llvm.experimental.vp.splice.v4b16(<4 x bfloat> %va, <4 x bfloat> %vb, i32 0, <4 x i1> %mask, i32 1, i32 %evl)
  ret <4 x bfloat> %v
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}