; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple riscv64 -mattr=+v < %s | FileCheck %s

define <vscale x 8 x i8> @sdiv_nxv8i8(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: sdiv_nxv8i8:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i8> @llvm.masked.sdiv(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i8> %res
}

define <vscale x 4 x i16> @sdiv_nxv4i16(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m) {
; CHECK-LABEL: sdiv_nxv4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i16> @llvm.masked.sdiv(<vscale x 4 x i16> %x, <vscale x 4 x i16> %y, <vscale x 4 x i1> %m)
  ret <vscale x 4 x i16> %res
}

define <vscale x 4 x i32> @sdiv_nxv4i32(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m) {
; CHECK-LABEL: sdiv_nxv4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i32> @llvm.masked.sdiv(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i1> %m)
  ret <vscale x 4 x i32> %res
}

define <vscale x 8 x i32> @sdiv_nxv8i32(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: sdiv_nxv8i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v12, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i32> @llvm.masked.sdiv(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i32> %res
}

define <vscale x 8 x i32> @sdiv_nxv8i32_splat_rhs(<vscale x 8 x i32> %x, i32 %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: sdiv_nxv8i32_splat_rhs:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT:    vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0
  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
  %res = call <vscale x 8 x i32> @llvm.masked.sdiv(<vscale x 8 x i32> %x, <vscale x 8 x i32> %splat, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i32> %res
}

define <vscale x 8 x i16> @sdiv_nxv8i16(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m) {
; CHECK-LABEL: sdiv_nxv8i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i16> @llvm.masked.sdiv(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i1> %m)
  ret <vscale x 8 x i16> %res
}

define <vscale x 2 x i64> @sdiv_nxv2i64(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: sdiv_nxv2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i64> @llvm.masked.sdiv(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y, <vscale x 2 x i1> %m)
  ret <vscale x 2 x i64> %res
}

define <4 x i32> @sdiv_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m) {
; CHECK-LABEL: sdiv_v4i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    ret
  %res = call <4 x i32> @llvm.masked.sdiv(<4 x i32> %x, <4 x i32> %y, <4 x i1> %m)
  ret <4 x i32> %res
}

define <2 x i64> @sdiv_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m) {
; CHECK-LABEL: sdiv_v2i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    ret
  %res = call <2 x i64> @llvm.masked.sdiv(<2 x i64> %x, <2 x i64> %y, <2 x i1> %m)
  ret <2 x i64> %res
}

define <4 x i64> @sdiv_v4i64(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m) {
; CHECK-LABEL: sdiv_v4i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e64, m2, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v10, v0.t
; CHECK-NEXT:    ret
  %res = call <4 x i64> @llvm.masked.sdiv(<4 x i64> %x, <4 x i64> %y, <4 x i1> %m)
  ret <4 x i64> %res
}

define <2 x i32> @sdiv_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m) {
; CHECK-LABEL: sdiv_v2i32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    ret
  %res = call <2 x i32> @llvm.masked.sdiv(<2 x i32> %x, <2 x i32> %y, <2 x i1> %m)
  ret <2 x i32> %res
}

define <4 x i16> @sdiv_v4i16(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m) {
; CHECK-LABEL: sdiv_v4i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    ret
  %res = call <4 x i16> @llvm.masked.sdiv(<4 x i16> %x, <4 x i16> %y, <4 x i1> %m)
  ret <4 x i16> %res
}

define <1 x i64> @sdiv_v1i64(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m) {
; CHECK-LABEL: sdiv_v1i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 1, e64, m1, ta, ma
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    ret
  %res = call <1 x i64> @llvm.masked.sdiv(<1 x i64> %x, <1 x i64> %y, <1 x i1> %m)
  ret <1 x i64> %res
}

define <2 x i128> @sdiv_v2i128(<2 x i128> %x, <2 x i128> %y, <2 x i1> %m) nounwind {
; CHECK-LABEL: sdiv_v2i128:
; CHECK:       # %bb.0:
; CHECK-NEXT:    addi sp, sp, -80
; CHECK-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s2, 48(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s3, 40(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s4, 32(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s5, 24(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s6, 16(sp) # 8-byte Folded Spill
; CHECK-NEXT:    csrr a3, vlenb
; CHECK-NEXT:    sub sp, sp, a3
; CHECK-NEXT:    mv a4, a1
; CHECK-NEXT:    addi a3, sp, 16
; CHECK-NEXT:    vs1r.v v0, (a3) # vscale x 8-byte Folded Spill
; CHECK-NEXT:    ld a6, 16(a1)
; CHECK-NEXT:    ld a1, 24(a1)
; CHECK-NEXT:    ld a3, 24(a2)
; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vmerge.vim v8, v8, 1, v0
; CHECK-NEXT:    vslidedown.vi v8, v8, 1
; CHECK-NEXT:    vmv.x.s a5, v8
; CHECK-NEXT:    andi a7, a5, 1
; CHECK-NEXT:    mv s0, a0
; CHECK-NEXT:    bnez a7, .LBB13_2
; CHECK-NEXT:  # %bb.1:
; CHECK-NEXT:    li a5, 1
; CHECK-NEXT:    j .LBB13_3
; CHECK-NEXT:  .LBB13_2:
; CHECK-NEXT:    ld a5, 16(a2)
; CHECK-NEXT:  .LBB13_3:
; CHECK-NEXT:    ld s1, 0(a4)
; CHECK-NEXT:    ld s2, 8(a4)
; CHECK-NEXT:    ld s3, 0(a2)
; CHECK-NEXT:    ld s6, 8(a2)
; CHECK-NEXT:    neg a0, a7
; CHECK-NEXT:    and a3, a0, a3
; CHECK-NEXT:    mv a0, a6
; CHECK-NEXT:    mv a2, a5
; CHECK-NEXT:    call __divti3
; CHECK-NEXT:    mv s4, a0
; CHECK-NEXT:    addi a0, sp, 16
; CHECK-NEXT:    vl1r.v v8, (a0) # vscale x 8-byte Folded Reload
; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
; CHECK-NEXT:    vfirst.m a0, v8
; CHECK-NEXT:    mv s5, a1
; CHECK-NEXT:    beqz a0, .LBB13_5
; CHECK-NEXT:  # %bb.4:
; CHECK-NEXT:    li s3, 1
; CHECK-NEXT:  .LBB13_5:
; CHECK-NEXT:    snez a0, a0
; CHECK-NEXT:    addi a0, a0, -1
; CHECK-NEXT:    and a3, a0, s6
; CHECK-NEXT:    mv a0, s1
; CHECK-NEXT:    mv a1, s2
; CHECK-NEXT:    mv a2, s3
; CHECK-NEXT:    call __divti3
; CHECK-NEXT:    sd a0, 0(s0)
; CHECK-NEXT:    sd a1, 8(s0)
; CHECK-NEXT:    sd s4, 16(s0)
; CHECK-NEXT:    sd s5, 24(s0)
; CHECK-NEXT:    csrr a0, vlenb
; CHECK-NEXT:    add sp, sp, a0
; CHECK-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s1, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s2, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s3, 40(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s4, 32(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s5, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s6, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT:    addi sp, sp, 80
; CHECK-NEXT:    ret
  %res = call <2 x i128> @llvm.masked.sdiv(<2 x i128> %x, <2 x i128> %y, <2 x i1> %m)
  ret <2 x i128> %res
}

define <3 x i10> @sdiv_v3i10(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m) {
; CHECK-LABEL: sdiv_v3i10:
; CHECK:       # %bb.0:
; CHECK-NEXT:    ld a3, 0(a2)
; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 7
; CHECK-NEXT:    ld a4, 8(a2)
; CHECK-NEXT:    ld a2, 16(a2)
; CHECK-NEXT:    vmv.v.x v9, a3
; CHECK-NEXT:    ld a3, 0(a1)
; CHECK-NEXT:    ld a5, 8(a1)
; CHECK-NEXT:    ld a1, 16(a1)
; CHECK-NEXT:    vmand.mm v0, v0, v8
; CHECK-NEXT:    vmv.v.x v8, a3
; CHECK-NEXT:    vslide1down.vx v9, v9, a4
; CHECK-NEXT:    vslide1down.vx v8, v8, a5
; CHECK-NEXT:    vslide1down.vx v9, v9, a2
; CHECK-NEXT:    vslide1down.vx v8, v8, a1
; CHECK-NEXT:    vslidedown.vi v9, v9, 1
; CHECK-NEXT:    vslidedown.vi v8, v8, 1
; CHECK-NEXT:    vsll.vi v9, v9, 6
; CHECK-NEXT:    vsll.vi v8, v8, 6
; CHECK-NEXT:    vsra.vi v9, v9, 6
; CHECK-NEXT:    vsra.vi v8, v8, 6
; CHECK-NEXT:    vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT:    vmv.x.s a1, v8
; CHECK-NEXT:    vslidedown.vi v9, v8, 1
; CHECK-NEXT:    vslidedown.vi v8, v8, 2
; CHECK-NEXT:    andi a1, a1, 1023
; CHECK-NEXT:    vmv.x.s a2, v9
; CHECK-NEXT:    vmv.x.s a3, v8
; CHECK-NEXT:    andi a2, a2, 1023
; CHECK-NEXT:    slli a3, a3, 20
; CHECK-NEXT:    slli a2, a2, 10
; CHECK-NEXT:    or a1, a1, a3
; CHECK-NEXT:    or a1, a1, a2
; CHECK-NEXT:    slli a1, a1, 34
; CHECK-NEXT:    srli a1, a1, 34
; CHECK-NEXT:    sw a1, 0(a0)
; CHECK-NEXT:    ret
  %res = call <3 x i10> @llvm.masked.sdiv(<3 x i10> %x, <3 x i10> %y, <3 x i1> %m)
  ret <3 x i10> %res
}