; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+unaligned-scalar-mem | FileCheck %s

; We should produce a vse8 due to the align 1
define void @test(ptr %out, <1 x i16> %v) {
; CHECK-LABEL: test:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, ta, ma
; CHECK-NEXT:    vse8.v v8, (a0)
; CHECK-NEXT:    ret
  %coerce.val.ii.i = extractelement <1 x i16> %v, i64 0
  store i16 %coerce.val.ii.i, ptr %out, align 1
  ret void
}