; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s

define <vscale x 8 x i8> @test(<vscale x 8 x i1> %0) #0 {
; CHECK-LABEL: test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    lui a0, 7
; CHECK-NEXT:    addi a0, a0, -1236
; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT:    vlse8.v v8, (zero), a0, v0.t
; CHECK-NEXT:    ret
entry:
  %1 = tail call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i32(ptr null, i32 27436, <vscale x 8 x i1> %0, i32 1)
  %2 = tail call <vscale x 8 x i8> @llvm.experimental.vp.strided.load.nxv8i8.p0.i64(ptr null, i64 27436, <vscale x 8 x i1> %0, i32 1)
  %3 = or <vscale x 8 x i8> %1, %2
  ret <vscale x 8 x i8> %3
}