; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s

define <vscale x 1 x i8> @test_vlseg3_mask_nxv16i8_triscv.vector.tuple_nxv1i8_3t(ptr %base, i64 %vl, <vscale x 1 x i1> %mask, target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %passthru) {
; CHECK-LABEL: test_vlseg3_mask_nxv16i8_triscv.vector.tuple_nxv1i8_3t:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetivli zero, 1, e8, m1, ta, ma
; CHECK-NEXT:    vmv1r.v v8, v9
; CHECK-NEXT:    addi a0, a0, 1
; CHECK-NEXT:    li a2, 3
; CHECK-NEXT:    vsetvli zero, a1, e8, mf8, ta, mu
; CHECK-NEXT:    vlse8.v v8, (a0), a2, v0.t
; CHECK-NEXT:    ret
entry:
  %0 = tail call target("riscv.vector.tuple", <vscale x 1 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv1i8_3t.nxv16i1(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %passthru, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 3)
  %1 = call <vscale x 1 x i8> @llvm.riscv.tuple.extract.nxv1i8.triscv.vector.tuple_nxv1i8_3t(target("riscv.vector.tuple", <vscale x 1 x i8>, 3) %0, i32 1)
  ret <vscale x 1 x i8> %1
}