; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfmin,+v -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zvfbfmin,+v -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH-ZVFHMIN,ZVFHMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+v,+experimental-zvfbfa -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+v,+experimental-zvfbfa -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA

define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv1bf16:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv1bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 1 x bfloat> @llvm.vp.fabs.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> %m, i32 %evl)
  ret <vscale x 1 x bfloat> %v
}

define <vscale x 1 x bfloat> @vfabs_vv_nxv1bf16_unmasked(<vscale x 1 x bfloat> %va, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv1bf16_unmasked:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv1bf16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 1 x bfloat> @llvm.vp.fabs.nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 1 x bfloat> %v
}

define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv2bf16:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv2bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 2 x bfloat> @llvm.vp.fabs.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> %m, i32 %evl)
  ret <vscale x 2 x bfloat> %v
}

define <vscale x 2 x bfloat> @vfabs_vv_nxv2bf16_unmasked(<vscale x 2 x bfloat> %va, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv2bf16_unmasked:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv2bf16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 2 x bfloat> @llvm.vp.fabs.nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 2 x bfloat> %v
}

define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv4bf16:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv4bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 4 x bfloat> @llvm.vp.fabs.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> %m, i32 %evl)
  ret <vscale x 4 x bfloat> %v
}

define <vscale x 4 x bfloat> @vfabs_vv_nxv4bf16_unmasked(<vscale x 4 x bfloat> %va, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv4bf16_unmasked:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv4bf16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 4 x bfloat> @llvm.vp.fabs.nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 4 x bfloat> %v
}

define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv8bf16:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv8bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 8 x bfloat> @llvm.vp.fabs.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> %m, i32 %evl)
  ret <vscale x 8 x bfloat> %v
}

define <vscale x 8 x bfloat> @vfabs_vv_nxv8bf16_unmasked(<vscale x 8 x bfloat> %va, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv8bf16_unmasked:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv8bf16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 8 x bfloat> @llvm.vp.fabs.nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 8 x bfloat> %v
}

define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv16bf16:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv16bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 16 x bfloat> @llvm.vp.fabs.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> %m, i32 %evl)
  ret <vscale x 16 x bfloat> %v
}

define <vscale x 16 x bfloat> @vfabs_vv_nxv16bf16_unmasked(<vscale x 16 x bfloat> %va, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv16bf16_unmasked:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv16bf16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 16 x bfloat> @llvm.vp.fabs.nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 16 x bfloat> %v
}

define <vscale x 32 x bfloat> @vfabs_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv32bf16:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv32bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m8, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 32 x bfloat> @llvm.vp.fabs.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> %m, i32 %evl)
  ret <vscale x 32 x bfloat> %v
}

define <vscale x 32 x bfloat> @vfabs_vv_nxv32bf16_unmasked(<vscale x 32 x bfloat> %va, i32 zeroext %evl) {
; ZVFH-ZVFHMIN-LABEL: vfabs_vv_nxv32bf16_unmasked:
; ZVFH-ZVFHMIN:       # %bb.0:
; ZVFH-ZVFHMIN-NEXT:    lui a0, 8
; ZVFH-ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFH-ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFH-ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFH-ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv32bf16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m8, ta, ma
; ZVFBFA-NEXT:    vfabs.v v8, v8
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 32 x bfloat> @llvm.vp.fabs.nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 32 x bfloat> %v
}

define <vscale x 1 x half> @vfabs_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv1f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv1f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv1f16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 1 x half> @llvm.vp.fabs.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> %m, i32 %evl)
  ret <vscale x 1 x half> %v
}

define <vscale x 1 x half> @vfabs_vv_nxv1f16_unmasked(<vscale x 1 x half> %va, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv1f16_unmasked:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv1f16_unmasked:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv1f16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 1 x half> @llvm.vp.fabs.nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 1 x half> %v
}

define <vscale x 2 x half> @vfabs_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv2f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv2f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv2f16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 2 x half> @llvm.vp.fabs.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> %m, i32 %evl)
  ret <vscale x 2 x half> %v
}

define <vscale x 2 x half> @vfabs_vv_nxv2f16_unmasked(<vscale x 2 x half> %va, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv2f16_unmasked:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv2f16_unmasked:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv2f16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 2 x half> @llvm.vp.fabs.nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 2 x half> %v
}

define <vscale x 4 x half> @vfabs_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv4f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv4f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv4f16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 4 x half> @llvm.vp.fabs.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> %m, i32 %evl)
  ret <vscale x 4 x half> %v
}

define <vscale x 4 x half> @vfabs_vv_nxv4f16_unmasked(<vscale x 4 x half> %va, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv4f16_unmasked:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv4f16_unmasked:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv4f16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 4 x half> @llvm.vp.fabs.nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 4 x half> %v
}

define <vscale x 8 x half> @vfabs_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv8f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv8f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv8f16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 8 x half> @llvm.vp.fabs.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %m, i32 %evl)
  ret <vscale x 8 x half> %v
}

define <vscale x 8 x half> @vfabs_vv_nxv8f16_unmasked(<vscale x 8 x half> %va, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv8f16_unmasked:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv8f16_unmasked:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv8f16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 8 x half> @llvm.vp.fabs.nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 8 x half> %v
}

define <vscale x 16 x half> @vfabs_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv16f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv16f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv16f16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 16 x half> @llvm.vp.fabs.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> %m, i32 %evl)
  ret <vscale x 16 x half> %v
}

define <vscale x 16 x half> @vfabs_vv_nxv16f16_unmasked(<vscale x 16 x half> %va, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv16f16_unmasked:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv16f16_unmasked:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv16f16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 16 x half> @llvm.vp.fabs.nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 16 x half> %v
}

define <vscale x 32 x half> @vfabs_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv32f16:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv32f16:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv32f16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 32 x half> @llvm.vp.fabs.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> %m, i32 %evl)
  ret <vscale x 32 x half> %v
}

define <vscale x 32 x half> @vfabs_vv_nxv32f16_unmasked(<vscale x 32 x half> %va, i32 zeroext %evl) {
; ZVFH-LABEL: vfabs_vv_nxv32f16_unmasked:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; ZVFH-NEXT:    vfabs.v v8, v8
; ZVFH-NEXT:    ret
;
; ZVFHMIN-LABEL: vfabs_vv_nxv32f16_unmasked:
; ZVFHMIN:       # %bb.0:
; ZVFHMIN-NEXT:    lui a0, 8
; ZVFHMIN-NEXT:    addi a0, a0, -1
; ZVFHMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFHMIN-NEXT:    vand.vx v8, v8, a0
; ZVFHMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfabs_vv_nxv32f16_unmasked:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    lui a0, 8
; ZVFBFA-NEXT:    addi a0, a0, -1
; ZVFBFA-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFBFA-NEXT:    vand.vx v8, v8, a0
; ZVFBFA-NEXT:    ret
  %v = call <vscale x 32 x half> @llvm.vp.fabs.nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 32 x half> %v
}

define <vscale x 1 x float> @vfabs_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv1f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 1 x float> @llvm.vp.fabs.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> %m, i32 %evl)
  ret <vscale x 1 x float> %v
}

define <vscale x 1 x float> @vfabs_vv_nxv1f32_unmasked(<vscale x 1 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv1f32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 1 x float> @llvm.vp.fabs.nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 1 x float> %v
}

define <vscale x 2 x float> @vfabs_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv2f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 2 x float> @llvm.vp.fabs.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> %m, i32 %evl)
  ret <vscale x 2 x float> %v
}

define <vscale x 2 x float> @vfabs_vv_nxv2f32_unmasked(<vscale x 2 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv2f32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 2 x float> @llvm.vp.fabs.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 2 x float> %v
}

define <vscale x 4 x float> @vfabs_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 4 x float> @llvm.vp.fabs.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> %m, i32 %evl)
  ret <vscale x 4 x float> %v
}

define <vscale x 4 x float> @vfabs_vv_nxv4f32_unmasked(<vscale x 4 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv4f32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 4 x float> @llvm.vp.fabs.nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 4 x float> %v
}

define <vscale x 8 x float> @vfabs_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 8 x float> @llvm.vp.fabs.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> %m, i32 %evl)
  ret <vscale x 8 x float> %v
}

define <vscale x 8 x float> @vfabs_vv_nxv8f32_unmasked(<vscale x 8 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv8f32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 8 x float> @llvm.vp.fabs.nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 8 x float> %v
}

define <vscale x 16 x float> @vfabs_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 16 x float> @llvm.vp.fabs.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> %m, i32 %evl)
  ret <vscale x 16 x float> %v
}

define <vscale x 16 x float> @vfabs_vv_nxv16f32_unmasked(<vscale x 16 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv16f32_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 16 x float> @llvm.vp.fabs.nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 16 x float> %v
}

define <vscale x 1 x double> @vfabs_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv1f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 1 x double> @llvm.vp.fabs.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> %m, i32 %evl)
  ret <vscale x 1 x double> %v
}

define <vscale x 1 x double> @vfabs_vv_nxv1f64_unmasked(<vscale x 1 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv1f64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 1 x double> @llvm.vp.fabs.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 1 x double> %v
}

define <vscale x 2 x double> @vfabs_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 2 x double> @llvm.vp.fabs.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> %m, i32 %evl)
  ret <vscale x 2 x double> %v
}

define <vscale x 2 x double> @vfabs_vv_nxv2f64_unmasked(<vscale x 2 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv2f64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 2 x double> @llvm.vp.fabs.nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 2 x double> %v
}

define <vscale x 4 x double> @vfabs_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 4 x double> @llvm.vp.fabs.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> %m, i32 %evl)
  ret <vscale x 4 x double> %v
}

define <vscale x 4 x double> @vfabs_vv_nxv4f64_unmasked(<vscale x 4 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv4f64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 4 x double> @llvm.vp.fabs.nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 4 x double> %v
}

define <vscale x 7 x double> @vfabs_vv_nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv7f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 7 x double> @llvm.vp.fabs.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> %m, i32 %evl)
  ret <vscale x 7 x double> %v
}

define <vscale x 7 x double> @vfabs_vv_nxv7f64_unmasked(<vscale x 7 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv7f64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 7 x double> @llvm.vp.fabs.nxv7f64(<vscale x 7 x double> %va, <vscale x 7 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 7 x double> %v
}

define <vscale x 8 x double> @vfabs_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 8 x double> @llvm.vp.fabs.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> %m, i32 %evl)
  ret <vscale x 8 x double> %v
}

define <vscale x 8 x double> @vfabs_vv_nxv8f64_unmasked(<vscale x 8 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv8f64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    ret
  %v = call <vscale x 8 x double> @llvm.vp.fabs.nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 8 x double> %v
}

; Test splitting.

define <vscale x 16 x double> @vfabs_vv_nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv16f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    vfabs.v v16, v16
; CHECK-NEXT:    ret
  %v = call <vscale x 16 x double> @llvm.vp.fabs.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> %m, i32 %evl)
  ret <vscale x 16 x double> %v
}

define <vscale x 16 x double> @vfabs_vv_nxv16f64_unmasked(<vscale x 16 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfabs_vv_nxv16f64_unmasked:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfabs.v v8, v8
; CHECK-NEXT:    vfabs.v v16, v16
; CHECK-NEXT:    ret
  %v = call <vscale x 16 x double> @llvm.vp.fabs.nxv16f64(<vscale x 16 x double> %va, <vscale x 16 x i1> splat (i1 true), i32 %evl)
  ret <vscale x 16 x double> %v
}