; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+experimental-zvfbfa \
; RUN:   -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+experimental-zvfbfa \
; RUN:   -verify-machineinstrs -target-abi=lp64d | FileCheck %s

define <vscale x 1 x i16> @intrinsic_vfclass_v_nxv1i16_nxv1bf16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv1i16_nxv1bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf4, ta, ma
; CHECK-NEXT:    vfclass.v v8, v8
; CHECK-NEXT:    ret
  <vscale x 1 x bfloat> %0,
  iXLen %1) nounwind {
entry:
  %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.nxv1i16.nxv1bf16(
    <vscale x 1 x i16> poison,
    <vscale x 1 x bfloat> %0,
    iXLen %1)

  ret <vscale x 1 x i16> %a
}

define <vscale x 1 x i16> @intrinsic_vfclass_mask_v_nxv1i16_nxv1bf16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv1i16_nxv1bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf4, tu, mu
; CHECK-NEXT:    vfclass.v v8, v9, v0.t
; CHECK-NEXT:    ret
  <vscale x 1 x i16> %0,
  <vscale x 1 x bfloat> %1,
  <vscale x 1 x i1> %2,
  iXLen %3) nounwind {
entry:
  %a = call <vscale x 1 x i16> @llvm.riscv.vfclass.mask.nxv1i16.nxv1bf16(
    <vscale x 1 x i16> %0,
    <vscale x 1 x bfloat> %1,
    <vscale x 1 x i1> %2,
    iXLen %3, iXLen 0)

  ret <vscale x 1 x i16> %a
}

define <vscale x 2 x i16> @intrinsic_vfclass_v_nxv2i16_nxv2bf16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv2i16_nxv2bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf2, ta, ma
; CHECK-NEXT:    vfclass.v v8, v8
; CHECK-NEXT:    ret
  <vscale x 2 x bfloat> %0,
  iXLen %1) nounwind {
entry:
  %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.nxv2i16.nxv2bf16(
    <vscale x 2 x i16> poison,
    <vscale x 2 x bfloat> %0,
    iXLen %1)

  ret <vscale x 2 x i16> %a
}

define <vscale x 2 x i16> @intrinsic_vfclass_mask_v_nxv2i16_nxv2bf16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv2i16_nxv2bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, mf2, tu, mu
; CHECK-NEXT:    vfclass.v v8, v9, v0.t
; CHECK-NEXT:    ret
  <vscale x 2 x i16> %0,
  <vscale x 2 x bfloat> %1,
  <vscale x 2 x i1> %2,
  iXLen %3) nounwind {
entry:
  %a = call <vscale x 2 x i16> @llvm.riscv.vfclass.mask.nxv2i16.nxv2bf16(
    <vscale x 2 x i16> %0,
    <vscale x 2 x bfloat> %1,
    <vscale x 2 x i1> %2,
    iXLen %3, iXLen 0)

  ret <vscale x 2 x i16> %a
}

define <vscale x 4 x i16> @intrinsic_vfclass_v_nxv4i16_nxv4bf16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv4i16_nxv4bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m1, ta, ma
; CHECK-NEXT:    vfclass.v v8, v8
; CHECK-NEXT:    ret
  <vscale x 4 x bfloat> %0,
  iXLen %1) nounwind {
entry:
  %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.nxv4i16.nxv4bf16(
    <vscale x 4 x i16> poison,
    <vscale x 4 x bfloat> %0,
    iXLen %1)

  ret <vscale x 4 x i16> %a
}

define <vscale x 4 x i16> @intrinsic_vfclass_mask_v_nxv4i16_nxv4bf16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv4i16_nxv4bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m1, tu, mu
; CHECK-NEXT:    vfclass.v v8, v9, v0.t
; CHECK-NEXT:    ret
  <vscale x 4 x i16> %0,
  <vscale x 4 x bfloat> %1,
  <vscale x 4 x i1> %2,
  iXLen %3) nounwind {
entry:
  %a = call <vscale x 4 x i16> @llvm.riscv.vfclass.mask.nxv4i16.nxv4bf16(
    <vscale x 4 x i16> %0,
    <vscale x 4 x bfloat> %1,
    <vscale x 4 x i1> %2,
    iXLen %3, iXLen 0)

  ret <vscale x 4 x i16> %a
}

define <vscale x 8 x i16> @intrinsic_vfclass_v_nxv8i16_nxv8bf16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv8i16_nxv8bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m2, ta, ma
; CHECK-NEXT:    vfclass.v v8, v8
; CHECK-NEXT:    ret
  <vscale x 8 x bfloat> %0,
  iXLen %1) nounwind {
entry:
  %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.nxv8i16.nxv8bf16(
    <vscale x 8 x i16> poison,
    <vscale x 8 x bfloat> %0,
    iXLen %1)

  ret <vscale x 8 x i16> %a
}

define <vscale x 8 x i16> @intrinsic_vfclass_mask_v_nxv8i16_nxv8bf16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv8i16_nxv8bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m2, tu, mu
; CHECK-NEXT:    vfclass.v v8, v10, v0.t
; CHECK-NEXT:    ret
  <vscale x 8 x i16> %0,
  <vscale x 8 x bfloat> %1,
  <vscale x 8 x i1> %2,
  iXLen %3) nounwind {
entry:
  %a = call <vscale x 8 x i16> @llvm.riscv.vfclass.mask.nxv8i16.nxv8bf16(
    <vscale x 8 x i16> %0,
    <vscale x 8 x bfloat> %1,
    <vscale x 8 x i1> %2,
    iXLen %3, iXLen 0)

  ret <vscale x 8 x i16> %a
}

define <vscale x 16 x i16> @intrinsic_vfclass_v_nxv16i16_nxv16bf16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv16i16_nxv16bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m4, ta, ma
; CHECK-NEXT:    vfclass.v v8, v8
; CHECK-NEXT:    ret
  <vscale x 16 x bfloat> %0,
  iXLen %1) nounwind {
entry:
  %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.nxv16i16.nxv16bf16(
    <vscale x 16 x i16> poison,
    <vscale x 16 x bfloat> %0,
    iXLen %1)

  ret <vscale x 16 x i16> %a
}

define <vscale x 16 x i16> @intrinsic_vfclass_mask_v_nxv16i16_nxv16bf16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv16i16_nxv16bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m4, tu, mu
; CHECK-NEXT:    vfclass.v v8, v12, v0.t
; CHECK-NEXT:    ret
  <vscale x 16 x i16> %0,
  <vscale x 16 x bfloat> %1,
  <vscale x 16 x i1> %2,
  iXLen %3) nounwind {
entry:
  %a = call <vscale x 16 x i16> @llvm.riscv.vfclass.mask.nxv16i16.nxv16bf16(
    <vscale x 16 x i16> %0,
    <vscale x 16 x bfloat> %1,
    <vscale x 16 x i1> %2,
    iXLen %3, iXLen 0)

  ret <vscale x 16 x i16> %a
}

define <vscale x 32 x i16> @intrinsic_vfclass_v_nxv32i16_nxv32bf16(
; CHECK-LABEL: intrinsic_vfclass_v_nxv32i16_nxv32bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m8, ta, ma
; CHECK-NEXT:    vfclass.v v8, v8
; CHECK-NEXT:    ret
  <vscale x 32 x bfloat> %0,
  iXLen %1) nounwind {
entry:
  %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.nxv32i16.nxv32bf16(
    <vscale x 32 x i16> poison,
    <vscale x 32 x bfloat> %0,
    iXLen %1)

  ret <vscale x 32 x i16> %a
}

define <vscale x 32 x i16> @intrinsic_vfclass_mask_v_nxv32i16_nxv32bf16(
; CHECK-LABEL: intrinsic_vfclass_mask_v_nxv32i16_nxv32bf16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetvli zero, a0, e16alt, m8, tu, mu
; CHECK-NEXT:    vfclass.v v8, v16, v0.t
; CHECK-NEXT:    ret
  <vscale x 32 x i16> %0,
  <vscale x 32 x bfloat> %1,
  <vscale x 32 x i1> %2,
  iXLen %3) nounwind {
entry:
  %a = call <vscale x 32 x i16> @llvm.riscv.vfclass.mask.nxv32i16.nxv32bf16(
    <vscale x 32 x i16> %0,
    <vscale x 32 x bfloat> %1,
    <vscale x 32 x i1> %2,
    iXLen %3, iXLen 0)

  ret <vscale x 32 x i16> %a
}