; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
; RUN:     -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
; RUN:     -verify-machineinstrs -early-live-intervals < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFMIN
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+experimental-zvfbfa,+v -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+zvfbfwma,+v -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFWMA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+zvfbfwma,+v -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFWMA

; This tests a mix of vfmsac and vfmsub by using different operand orders to
; trigger commuting in TwoAddressInstructionPass.

define <vscale x 1 x bfloat> @vfmsub_vv_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x bfloat> %vc) {
; ZVFBFMIN-LABEL: vfmsub_vv_nxv1bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v11, v8
; ZVFBFMIN-NEXT:    vxor.vx v8, v10, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v12, v9
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v12, v11, v10
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v12
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vv_nxv1bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfmsub.vv v8, v9, v10
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vv_nxv1bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v10, v10, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v11, v10
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v11, v8, v9
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v11
; ZVFBFWMA-NEXT:    ret
  %neg = fneg <vscale x 1 x bfloat> %vc
  %vd = call <vscale x 1 x bfloat> @llvm.fma.v1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, <vscale x 1 x bfloat> %neg)
  ret <vscale x 1 x bfloat> %vd
}

define <vscale x 1 x bfloat> @vfmsub_vf_nxv1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb, bfloat %c) {
; ZVFBFMIN-LABEL: vfmsub_vf_nxv1bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v9, v9, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v10, v9
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vf v9, fa5, v10
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, mf4, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v9
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vf_nxv1bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfmsub.vf v8, fa0, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vf_nxv1bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v9, v9, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v10, v9
; ZVFBFWMA-NEXT:    vfwmaccbf16.vf v10, fa0, v8
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v10
; ZVFBFWMA-NEXT:    ret
  %head = insertelement <vscale x 1 x bfloat> poison, bfloat %c, i32 0
  %splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
  %neg = fneg <vscale x 1 x bfloat> %vb
  %vd = call <vscale x 1 x bfloat> @llvm.fma.v1bf16(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %splat, <vscale x 1 x bfloat> %neg)
  ret <vscale x 1 x bfloat> %vd
}

define <vscale x 2 x bfloat> @vfmsub_vv_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, <vscale x 2 x bfloat> %vc) {
; ZVFBFMIN-LABEL: vfmsub_vv_nxv2bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v11, v8
; ZVFBFMIN-NEXT:    vxor.vx v8, v9, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v9, v8
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v12, v10
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v12, v11, v9
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v12
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vv_nxv2bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfmsub.vv v8, v10, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vv_nxv2bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v9, v9, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v11, v9
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v11, v8, v10
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v11
; ZVFBFWMA-NEXT:    ret
  %neg = fneg <vscale x 2 x bfloat> %vb
  %vd = call <vscale x 2 x bfloat> @llvm.fma.v2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vc, <vscale x 2 x bfloat> %neg)
  ret <vscale x 2 x bfloat> %vd
}

define <vscale x 2 x bfloat> @vfmsub_vf_nxv2bf16(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb, bfloat %c) {
; ZVFBFMIN-LABEL: vfmsub_vf_nxv2bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v11, v9
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vf v11, fa5, v10
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, mf2, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v11
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vf_nxv2bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfmsac.vf v8, fa0, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vf_nxv2bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v8, v8, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFBFWMA-NEXT:    vfwmaccbf16.vf v10, fa0, v9
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v10
; ZVFBFWMA-NEXT:    ret
  %head = insertelement <vscale x 2 x bfloat> poison, bfloat %c, i32 0
  %splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
  %neg = fneg <vscale x 2 x bfloat> %va
  %vd = call <vscale x 2 x bfloat> @llvm.fma.v2bf16(<vscale x 2 x bfloat> %vb, <vscale x 2 x bfloat> %splat, <vscale x 2 x bfloat> %neg)
  ret <vscale x 2 x bfloat> %vd
}

define <vscale x 4 x bfloat> @vfmsub_vv_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, <vscale x 4 x bfloat> %vc) {
; ZVFBFMIN-LABEL: vfmsub_vv_nxv4bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v12, v9
; ZVFBFMIN-NEXT:    vxor.vx v9, v10, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v10, v9
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v14, v8
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v14, v12, v10
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v14
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vv_nxv4bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vfmsub.vv v8, v9, v10
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vv_nxv4bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v12, v10, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v10, v12
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v10, v9, v8
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v10
; ZVFBFWMA-NEXT:    ret
  %neg = fneg <vscale x 4 x bfloat> %vc
  %vd = call <vscale x 4 x bfloat> @llvm.fma.v4bf16(<vscale x 4 x bfloat> %vb, <vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %neg)
  ret <vscale x 4 x bfloat> %vd
}

define <vscale x 4 x bfloat> @vfmsub_vf_nxv4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb, bfloat %c) {
; ZVFBFMIN-LABEL: vfmsub_vf_nxv4bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v9, v9, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v10, v9
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v12, v8
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vf v12, fa5, v10
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m1, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v12
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vf_nxv4bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vfmsub.vf v8, fa0, v9
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vf_nxv4bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v9, v9, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v10, v9
; ZVFBFWMA-NEXT:    vfwmaccbf16.vf v10, fa0, v8
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v10
; ZVFBFWMA-NEXT:    ret
  %head = insertelement <vscale x 4 x bfloat> poison, bfloat %c, i32 0
  %splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
  %neg = fneg <vscale x 4 x bfloat> %vb
  %vd = call <vscale x 4 x bfloat> @llvm.fma.v4bf16(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %splat, <vscale x 4 x bfloat> %neg)
  ret <vscale x 4 x bfloat> %vd
}

define <vscale x 8 x bfloat> @vfmsub_vv_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, <vscale x 8 x bfloat> %vc) {
; ZVFBFMIN-LABEL: vfmsub_vv_nxv8bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v10
; ZVFBFMIN-NEXT:    vxor.vx v14, v8, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v8, v14
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v20, v12
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v20, v16, v8
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v20
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vv_nxv8bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vfmsac.vv v8, v12, v10
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vv_nxv8bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v8, v8, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v16, v8
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v16, v10, v12
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v16
; ZVFBFWMA-NEXT:    ret
  %neg = fneg <vscale x 8 x bfloat> %va
  %vd = call <vscale x 8 x bfloat> @llvm.fma.v8bf16(<vscale x 8 x bfloat> %vb, <vscale x 8 x bfloat> %vc, <vscale x 8 x bfloat> %neg)
  ret <vscale x 8 x bfloat> %vd
}

define <vscale x 8 x bfloat> @vfmsub_vf_nxv8bf16(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb, bfloat %c) {
; ZVFBFMIN-LABEL: vfmsub_vf_nxv8bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v12, v8
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v10
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vf v16, fa5, v12
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v16
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vf_nxv8bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vfmsac.vf v8, fa0, v10
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vf_nxv8bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v8, v8, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v12, v8
; ZVFBFWMA-NEXT:    vfwmaccbf16.vf v12, fa0, v10
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v12
; ZVFBFWMA-NEXT:    ret
  %head = insertelement <vscale x 8 x bfloat> poison, bfloat %c, i32 0
  %splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
  %neg = fneg <vscale x 8 x bfloat> %va
  %vd = call <vscale x 8 x bfloat> @llvm.fma.v8bf16(<vscale x 8 x bfloat> %vb, <vscale x 8 x bfloat> %splat, <vscale x 8 x bfloat> %neg)
  ret <vscale x 8 x bfloat> %vd
}

define <vscale x 16 x bfloat> @vfmsub_vv_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, <vscale x 16 x bfloat> %vc) {
; ZVFBFMIN-LABEL: vfmsub_vv_nxv16bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v16
; ZVFBFMIN-NEXT:    vxor.vx v12, v12, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v12
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v0, v8
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v0, v24, v16
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v0
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vv_nxv16bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT:    vfmsub.vv v8, v16, v12
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vv_nxv16bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v12, v12, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v24, v12
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v24, v16, v8
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v24
; ZVFBFWMA-NEXT:    ret
  %neg = fneg <vscale x 16 x bfloat> %vb
  %vd = call <vscale x 16 x bfloat> @llvm.fma.v16bf16(<vscale x 16 x bfloat> %vc, <vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %neg)
  ret <vscale x 16 x bfloat> %vd
}

define <vscale x 16 x bfloat> @vfmsub_vf_nxv16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %vb, bfloat %c) {
; ZVFBFMIN-LABEL: vfmsub_vf_nxv16bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v12, v12, a0
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v12
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v8
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vf v24, fa5, v16
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v24
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vf_nxv16bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m4, ta, ma
; ZVFBFA-NEXT:    vfmsub.vf v8, fa0, v12
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vf_nxv16bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v12, v12, a0
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v16, v12
; ZVFBFWMA-NEXT:    vfwmaccbf16.vf v16, fa0, v8
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v8, v16
; ZVFBFWMA-NEXT:    ret
  %head = insertelement <vscale x 16 x bfloat> poison, bfloat %c, i32 0
  %splat = shufflevector <vscale x 16 x bfloat> %head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
  %neg = fneg <vscale x 16 x bfloat> %vb
  %vd = call <vscale x 16 x bfloat> @llvm.fma.v16bf16(<vscale x 16 x bfloat> %va, <vscale x 16 x bfloat> %splat, <vscale x 16 x bfloat> %neg)
  ret <vscale x 16 x bfloat> %vd
}

define <vscale x 32 x bfloat> @vfmsub_vv_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, <vscale x 32 x bfloat> %vc) {
; ZVFBFMIN-LABEL: vfmsub_vv_nxv32bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    addi sp, sp, -16
; ZVFBFMIN-NEXT:    .cfi_def_cfa_offset 16
; ZVFBFMIN-NEXT:    csrr a1, vlenb
; ZVFBFMIN-NEXT:    slli a1, a1, 3
; ZVFBFMIN-NEXT:    mv a2, a1
; ZVFBFMIN-NEXT:    slli a1, a1, 1
; ZVFBFMIN-NEXT:    add a1, a1, a2
; ZVFBFMIN-NEXT:    sub sp, sp, a1
; ZVFBFMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; ZVFBFMIN-NEXT:    csrr a1, vlenb
; ZVFBFMIN-NEXT:    slli a1, a1, 3
; ZVFBFMIN-NEXT:    add a1, sp, a1
; ZVFBFMIN-NEXT:    addi a1, a1, 16
; ZVFBFMIN-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    vl8re16.v v24, (a0)
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 4
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v16
; ZVFBFMIN-NEXT:    addi a1, sp, 16
; ZVFBFMIN-NEXT:    vs8r.v v24, (a1) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v8
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 4
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v0, v24
; ZVFBFMIN-NEXT:    addi a0, sp, 16
; ZVFBFMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v0, v24, v16
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 3
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v20
; ZVFBFMIN-NEXT:    addi a0, sp, 16
; ZVFBFMIN-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v12
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 4
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v12
; ZVFBFMIN-NEXT:    addi a0, sp, 16
; ZVFBFMIN-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v16, v8, v24
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v0
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v12, v16
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 3
; ZVFBFMIN-NEXT:    mv a1, a0
; ZVFBFMIN-NEXT:    slli a0, a0, 1
; ZVFBFMIN-NEXT:    add a0, a0, a1
; ZVFBFMIN-NEXT:    add sp, sp, a0
; ZVFBFMIN-NEXT:    .cfi_def_cfa sp, 16
; ZVFBFMIN-NEXT:    addi sp, sp, 16
; ZVFBFMIN-NEXT:    .cfi_def_cfa_offset 0
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vv_nxv32bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vl8re16.v v24, (a0)
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m8, ta, ma
; ZVFBFA-NEXT:    vfmsac.vv v8, v16, v24
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vv_nxv32bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    addi sp, sp, -16
; ZVFBFWMA-NEXT:    .cfi_def_cfa_offset 16
; ZVFBFWMA-NEXT:    csrr a1, vlenb
; ZVFBFWMA-NEXT:    slli a1, a1, 3
; ZVFBFWMA-NEXT:    sub sp, sp, a1
; ZVFBFWMA-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; ZVFBFWMA-NEXT:    addi a1, sp, 16
; ZVFBFWMA-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFBFWMA-NEXT:    vl8re16.v v24, (a0)
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFBFWMA-NEXT:    vxor.vx v16, v8, a0
; ZVFBFWMA-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v0, v16
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v8, v20
; ZVFBFWMA-NEXT:    addi a0, sp, 16
; ZVFBFWMA-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v0, v24, v16
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v16, v0
; ZVFBFWMA-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v8, v28, v4
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v20, v8
; ZVFBFWMA-NEXT:    vmv8r.v v8, v16
; ZVFBFWMA-NEXT:    csrr a0, vlenb
; ZVFBFWMA-NEXT:    slli a0, a0, 3
; ZVFBFWMA-NEXT:    add sp, sp, a0
; ZVFBFWMA-NEXT:    .cfi_def_cfa sp, 16
; ZVFBFWMA-NEXT:    addi sp, sp, 16
; ZVFBFWMA-NEXT:    .cfi_def_cfa_offset 0
; ZVFBFWMA-NEXT:    ret
  %neg = fneg <vscale x 32 x bfloat> %va
  %vd = call <vscale x 32 x bfloat> @llvm.fma.v32bf16(<vscale x 32 x bfloat> %vc, <vscale x 32 x bfloat> %vb, <vscale x 32 x bfloat> %neg)
  ret <vscale x 32 x bfloat> %vd
}

define <vscale x 32 x bfloat> @vfmsub_vf_nxv32bf16(<vscale x 32 x bfloat> %va, <vscale x 32 x bfloat> %vb, bfloat %c) {
; ZVFBFMIN-LABEL: vfmsub_vf_nxv32bf16:
; ZVFBFMIN:       # %bb.0:
; ZVFBFMIN-NEXT:    addi sp, sp, -16
; ZVFBFMIN-NEXT:    .cfi_def_cfa_offset 16
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 3
; ZVFBFMIN-NEXT:    mv a1, a0
; ZVFBFMIN-NEXT:    slli a0, a0, 1
; ZVFBFMIN-NEXT:    add a0, a0, a1
; ZVFBFMIN-NEXT:    sub sp, sp, a0
; ZVFBFMIN-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; ZVFBFMIN-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; ZVFBFMIN-NEXT:    vmv8r.v v24, v16
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 3
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    fmv.x.h a0, fa0
; ZVFBFMIN-NEXT:    vmv.v.x v16, a0
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 4
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    lui a0, 8
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v24
; ZVFBFMIN-NEXT:    addi a1, sp, 16
; ZVFBFMIN-NEXT:    vs8r.v v16, (a1) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFBFMIN-NEXT:    vxor.vx v8, v8, a0
; ZVFBFMIN-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v8
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 4
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v0, v24
; ZVFBFMIN-NEXT:    addi a0, sp, 16
; ZVFBFMIN-NEXT:    vl8r.v v24, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v0, v24, v16
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 3
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v20
; ZVFBFMIN-NEXT:    addi a0, sp, 16
; ZVFBFMIN-NEXT:    vs8r.v v24, (a0) # vscale x 64-byte Folded Spill
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v24, v12
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 4
; ZVFBFMIN-NEXT:    add a0, sp, a0
; ZVFBFMIN-NEXT:    addi a0, a0, 16
; ZVFBFMIN-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vfwcvtbf16.f.f.v v16, v12
; ZVFBFMIN-NEXT:    addi a0, sp, 16
; ZVFBFMIN-NEXT:    vl8r.v v8, (a0) # vscale x 64-byte Folded Reload
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e32, m8, ta, ma
; ZVFBFMIN-NEXT:    vfmadd.vv v16, v8, v24
; ZVFBFMIN-NEXT:    vsetvli zero, zero, e16, m4, ta, ma
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v8, v0
; ZVFBFMIN-NEXT:    vfncvtbf16.f.f.w v12, v16
; ZVFBFMIN-NEXT:    csrr a0, vlenb
; ZVFBFMIN-NEXT:    slli a0, a0, 3
; ZVFBFMIN-NEXT:    mv a1, a0
; ZVFBFMIN-NEXT:    slli a0, a0, 1
; ZVFBFMIN-NEXT:    add a0, a0, a1
; ZVFBFMIN-NEXT:    add sp, sp, a0
; ZVFBFMIN-NEXT:    .cfi_def_cfa sp, 16
; ZVFBFMIN-NEXT:    addi sp, sp, 16
; ZVFBFMIN-NEXT:    .cfi_def_cfa_offset 0
; ZVFBFMIN-NEXT:    ret
;
; ZVFBFA-LABEL: vfmsub_vf_nxv32bf16:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m8, ta, ma
; ZVFBFA-NEXT:    vfmsac.vf v8, fa0, v16
; ZVFBFA-NEXT:    ret
;
; ZVFBFWMA-LABEL: vfmsub_vf_nxv32bf16:
; ZVFBFWMA:       # %bb.0:
; ZVFBFWMA-NEXT:    addi sp, sp, -16
; ZVFBFWMA-NEXT:    .cfi_def_cfa_offset 16
; ZVFBFWMA-NEXT:    csrr a0, vlenb
; ZVFBFWMA-NEXT:    slli a0, a0, 3
; ZVFBFWMA-NEXT:    sub sp, sp, a0
; ZVFBFWMA-NEXT:    .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; ZVFBFWMA-NEXT:    addi a0, sp, 16
; ZVFBFWMA-NEXT:    vs8r.v v16, (a0) # vscale x 64-byte Folded Spill
; ZVFBFWMA-NEXT:    fmv.x.h a0, fa0
; ZVFBFWMA-NEXT:    vsetvli a1, zero, e16, m8, ta, ma
; ZVFBFWMA-NEXT:    vmv.v.x v24, a0
; ZVFBFWMA-NEXT:    lui a0, 8
; ZVFBFWMA-NEXT:    vxor.vx v16, v8, a0
; ZVFBFWMA-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v0, v16
; ZVFBFWMA-NEXT:    vfwcvtbf16.f.f.v v8, v20
; ZVFBFWMA-NEXT:    addi a0, sp, 16
; ZVFBFWMA-NEXT:    vl8r.v v16, (a0) # vscale x 64-byte Folded Reload
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v0, v16, v24
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v16, v0
; ZVFBFWMA-NEXT:    vl8r.v v0, (a0) # vscale x 64-byte Folded Reload
; ZVFBFWMA-NEXT:    vfwmaccbf16.vv v8, v4, v28
; ZVFBFWMA-NEXT:    vfncvtbf16.f.f.w v20, v8
; ZVFBFWMA-NEXT:    vmv8r.v v8, v16
; ZVFBFWMA-NEXT:    csrr a0, vlenb
; ZVFBFWMA-NEXT:    slli a0, a0, 3
; ZVFBFWMA-NEXT:    add sp, sp, a0
; ZVFBFWMA-NEXT:    .cfi_def_cfa sp, 16
; ZVFBFWMA-NEXT:    addi sp, sp, 16
; ZVFBFWMA-NEXT:    .cfi_def_cfa_offset 0
; ZVFBFWMA-NEXT:    ret
  %head = insertelement <vscale x 32 x bfloat> poison, bfloat %c, i32 0
  %splat = shufflevector <vscale x 32 x bfloat> %head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
  %neg = fneg <vscale x 32 x bfloat> %va
  %vd = call <vscale x 32 x bfloat> @llvm.fma.v32bf16(<vscale x 32 x bfloat> %vb, <vscale x 32 x bfloat> %splat, <vscale x 32 x bfloat> %neg)
  ret <vscale x 32 x bfloat> %vd
}

define <vscale x 1 x half> @vfmsub_vv_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv1f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v9, v10
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 1 x half> %vc
  %vd = call <vscale x 1 x half> @llvm.fma.v1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, <vscale x 1 x half> %neg)
  ret <vscale x 1 x half> %vd
}

define <vscale x 1 x half> @vfmsub_vf_nxv1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %vb, half %c) {
; CHECK-LABEL: vfmsub_vf_nxv1f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x half> poison, half %c, i32 0
  %splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
  %neg = fneg <vscale x 1 x half> %vb
  %vd = call <vscale x 1 x half> @llvm.fma.v1f16(<vscale x 1 x half> %va, <vscale x 1 x half> %splat, <vscale x 1 x half> %neg)
  ret <vscale x 1 x half> %vd
}

define <vscale x 2 x half> @vfmsub_vv_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, <vscale x 2 x half> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv2f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v10, v9
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 2 x half> %vb
  %vd = call <vscale x 2 x half> @llvm.fma.v2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vc, <vscale x 2 x half> %neg)
  ret <vscale x 2 x half> %vd
}

define <vscale x 2 x half> @vfmsub_vf_nxv2f16(<vscale x 2 x half> %va, <vscale x 2 x half> %vb, half %c) {
; CHECK-LABEL: vfmsub_vf_nxv2f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; CHECK-NEXT:    vfmsac.vf v8, fa0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x half> poison, half %c, i32 0
  %splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
  %neg = fneg <vscale x 2 x half> %va
  %vd = call <vscale x 2 x half> @llvm.fma.v2f16(<vscale x 2 x half> %vb, <vscale x 2 x half> %splat, <vscale x 2 x half> %neg)
  ret <vscale x 2 x half> %vd
}

define <vscale x 4 x half> @vfmsub_vv_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, <vscale x 4 x half> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv4f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v9, v10
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 4 x half> %vc
  %vd = call <vscale x 4 x half> @llvm.fma.v4f16(<vscale x 4 x half> %vb, <vscale x 4 x half> %va, <vscale x 4 x half> %neg)
  ret <vscale x 4 x half> %vd
}

define <vscale x 4 x half> @vfmsub_vf_nxv4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %vb, half %c) {
; CHECK-LABEL: vfmsub_vf_nxv4f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x half> poison, half %c, i32 0
  %splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
  %neg = fneg <vscale x 4 x half> %vb
  %vd = call <vscale x 4 x half> @llvm.fma.v4f16(<vscale x 4 x half> %va, <vscale x 4 x half> %splat, <vscale x 4 x half> %neg)
  ret <vscale x 4 x half> %vd
}

define <vscale x 8 x half> @vfmsub_vv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, <vscale x 8 x half> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv8f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT:    vfmsac.vv v8, v12, v10
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 8 x half> %va
  %vd = call <vscale x 8 x half> @llvm.fma.v8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %vc, <vscale x 8 x half> %neg)
  ret <vscale x 8 x half> %vd
}

define <vscale x 8 x half> @vfmsub_vf_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x half> %vb, half %c) {
; CHECK-LABEL: vfmsub_vf_nxv8f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; CHECK-NEXT:    vfmsac.vf v8, fa0, v10
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x half> poison, half %c, i32 0
  %splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
  %neg = fneg <vscale x 8 x half> %va
  %vd = call <vscale x 8 x half> @llvm.fma.v8f16(<vscale x 8 x half> %vb, <vscale x 8 x half> %splat, <vscale x 8 x half> %neg)
  ret <vscale x 8 x half> %vd
}

define <vscale x 16 x half> @vfmsub_vv_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, <vscale x 16 x half> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv16f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v16, v12
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 16 x half> %vb
  %vd = call <vscale x 16 x half> @llvm.fma.v16f16(<vscale x 16 x half> %vc, <vscale x 16 x half> %va, <vscale x 16 x half> %neg)
  ret <vscale x 16 x half> %vd
}

define <vscale x 16 x half> @vfmsub_vf_nxv16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %vb, half %c) {
; CHECK-LABEL: vfmsub_vf_nxv16f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v12
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 16 x half> poison, half %c, i32 0
  %splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
  %neg = fneg <vscale x 16 x half> %vb
  %vd = call <vscale x 16 x half> @llvm.fma.v16f16(<vscale x 16 x half> %va, <vscale x 16 x half> %splat, <vscale x 16 x half> %neg)
  ret <vscale x 16 x half> %vd
}

define <vscale x 32 x half> @vfmsub_vv_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, <vscale x 32 x half> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv32f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl8re16.v v24, (a0)
; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT:    vfmsac.vv v8, v16, v24
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 32 x half> %va
  %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vc, <vscale x 32 x half> %vb, <vscale x 32 x half> %neg)
  ret <vscale x 32 x half> %vd
}

define <vscale x 32 x half> @vfmsub_vf_nxv32f16(<vscale x 32 x half> %va, <vscale x 32 x half> %vb, half %c) {
; CHECK-LABEL: vfmsub_vf_nxv32f16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e16, m8, ta, ma
; CHECK-NEXT:    vfmsac.vf v8, fa0, v16
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 32 x half> poison, half %c, i32 0
  %splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer
  %neg = fneg <vscale x 32 x half> %va
  %vd = call <vscale x 32 x half> @llvm.fma.v32f16(<vscale x 32 x half> %vb, <vscale x 32 x half> %splat, <vscale x 32 x half> %neg)
  ret <vscale x 32 x half> %vd
}

define <vscale x 1 x float> @vfmsub_vv_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv1f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v9, v10
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 1 x float> %vc
  %vd = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, <vscale x 1 x float> %neg)
  ret <vscale x 1 x float> %vd
}

define <vscale x 1 x float> @vfmsub_vf_nxv1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %vb, float %c) {
; CHECK-LABEL: vfmsub_vf_nxv1f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x float> poison, float %c, i32 0
  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
  %neg = fneg <vscale x 1 x float> %vb
  %vd = call <vscale x 1 x float> @llvm.fma.v1f32(<vscale x 1 x float> %va, <vscale x 1 x float> %splat, <vscale x 1 x float> %neg)
  ret <vscale x 1 x float> %vd
}

define <vscale x 2 x float> @vfmsub_vv_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x float> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv2f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v10, v9
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 2 x float> %vb
  %vd = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vc, <vscale x 2 x float> %neg)
  ret <vscale x 2 x float> %vd
}

define <vscale x 2 x float> @vfmsub_vf_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, float %c) {
; CHECK-LABEL: vfmsub_vf_nxv2f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vfmsac.vf v8, fa0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x float> poison, float %c, i32 0
  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
  %neg = fneg <vscale x 2 x float> %va
  %vd = call <vscale x 2 x float> @llvm.fma.v2f32(<vscale x 2 x float> %vb, <vscale x 2 x float> %splat, <vscale x 2 x float> %neg)
  ret <vscale x 2 x float> %vd
}

define <vscale x 4 x float> @vfmsub_vv_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, <vscale x 4 x float> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v10, v12
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 4 x float> %vc
  %vd = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %vb, <vscale x 4 x float> %va, <vscale x 4 x float> %neg)
  ret <vscale x 4 x float> %vd
}

define <vscale x 4 x float> @vfmsub_vf_nxv4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %vb, float %c) {
; CHECK-LABEL: vfmsub_vf_nxv4f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v10
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x float> poison, float %c, i32 0
  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
  %neg = fneg <vscale x 4 x float> %vb
  %vd = call <vscale x 4 x float> @llvm.fma.v4f32(<vscale x 4 x float> %va, <vscale x 4 x float> %splat, <vscale x 4 x float> %neg)
  ret <vscale x 4 x float> %vd
}

define <vscale x 8 x float> @vfmsub_vv_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, <vscale x 8 x float> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vfmsac.vv v8, v16, v12
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 8 x float> %va
  %vd = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vb, <vscale x 8 x float> %vc, <vscale x 8 x float> %neg)
  ret <vscale x 8 x float> %vd
}

define <vscale x 8 x float> @vfmsub_vf_nxv8f32(<vscale x 8 x float> %va, <vscale x 8 x float> %vb, float %c) {
; CHECK-LABEL: vfmsub_vf_nxv8f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vfmsac.vf v8, fa0, v12
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x float> poison, float %c, i32 0
  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
  %neg = fneg <vscale x 8 x float> %va
  %vd = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vb, <vscale x 8 x float> %splat, <vscale x 8 x float> %neg)
  ret <vscale x 8 x float> %vd
}

define <vscale x 16 x float> @vfmsub_vv_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, <vscale x 16 x float> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl8re32.v v24, (a0)
; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v24, v16
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 16 x float> %vb
  %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %vc, <vscale x 16 x float> %va, <vscale x 16 x float> %neg)
  ret <vscale x 16 x float> %vd
}

define <vscale x 16 x float> @vfmsub_vf_nxv16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %vb, float %c) {
; CHECK-LABEL: vfmsub_vf_nxv16f32:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m8, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v16
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 16 x float> poison, float %c, i32 0
  %splat = shufflevector <vscale x 16 x float> %head, <vscale x 16 x float> poison, <vscale x 16 x i32> zeroinitializer
  %neg = fneg <vscale x 16 x float> %vb
  %vd = call <vscale x 16 x float> @llvm.fma.v16f32(<vscale x 16 x float> %va, <vscale x 16 x float> %splat, <vscale x 16 x float> %neg)
  ret <vscale x 16 x float> %vd
}

define <vscale x 1 x double> @vfmsub_vv_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x double> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv1f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v9, v10
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 1 x double> %vc
  %vd = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x double> %neg)
  ret <vscale x 1 x double> %vd
}

define <vscale x 1 x double> @vfmsub_vf_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, double %c) {
; CHECK-LABEL: vfmsub_vf_nxv1f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x double> poison, double %c, i32 0
  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
  %neg = fneg <vscale x 1 x double> %vb
  %vd = call <vscale x 1 x double> @llvm.fma.v1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %splat, <vscale x 1 x double> %neg)
  ret <vscale x 1 x double> %vd
}

define <vscale x 2 x double> @vfmsub_vv_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, <vscale x 2 x double> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v12, v10
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 2 x double> %vb
  %vd = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vc, <vscale x 2 x double> %neg)
  ret <vscale x 2 x double> %vd
}

define <vscale x 2 x double> @vfmsub_vf_nxv2f64(<vscale x 2 x double> %va, <vscale x 2 x double> %vb, double %c) {
; CHECK-LABEL: vfmsub_vf_nxv2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, ma
; CHECK-NEXT:    vfmsac.vf v8, fa0, v10
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x double> poison, double %c, i32 0
  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
  %neg = fneg <vscale x 2 x double> %va
  %vd = call <vscale x 2 x double> @llvm.fma.v2f64(<vscale x 2 x double> %vb, <vscale x 2 x double> %splat, <vscale x 2 x double> %neg)
  ret <vscale x 2 x double> %vd
}

define <vscale x 4 x double> @vfmsub_vv_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, <vscale x 4 x double> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT:    vfmsub.vv v8, v12, v16
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 4 x double> %vc
  %vd = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %vb, <vscale x 4 x double> %va, <vscale x 4 x double> %neg)
  ret <vscale x 4 x double> %vd
}

define <vscale x 4 x double> @vfmsub_vf_nxv4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %vb, double %c) {
; CHECK-LABEL: vfmsub_vf_nxv4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, ma
; CHECK-NEXT:    vfmsub.vf v8, fa0, v12
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x double> poison, double %c, i32 0
  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
  %neg = fneg <vscale x 4 x double> %vb
  %vd = call <vscale x 4 x double> @llvm.fma.v4f64(<vscale x 4 x double> %va, <vscale x 4 x double> %splat, <vscale x 4 x double> %neg)
  ret <vscale x 4 x double> %vd
}

define <vscale x 8 x double> @vfmsub_vv_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, <vscale x 8 x double> %vc) {
; CHECK-LABEL: vfmsub_vv_nxv8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vl8re64.v v24, (a0)
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfmsac.vv v8, v16, v24
; CHECK-NEXT:    ret
  %neg = fneg <vscale x 8 x double> %va
  %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %vc, <vscale x 8 x double> %neg)
  ret <vscale x 8 x double> %vd
}

define <vscale x 8 x double> @vfmsub_vf_nxv8f64(<vscale x 8 x double> %va, <vscale x 8 x double> %vb, double %c) {
; CHECK-LABEL: vfmsub_vf_nxv8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT:    vfmsac.vf v8, fa0, v16
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x double> poison, double %c, i32 0
  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
  %neg = fneg <vscale x 8 x double> %va
  %vd = call <vscale x 8 x double> @llvm.fma.v8f64(<vscale x 8 x double> %vb, <vscale x 8 x double> %splat, <vscale x 8 x double> %neg)
  ret <vscale x 8 x double> %vd
}