; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=ilp32d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+zvfbfmin -target-abi=lp64d \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH
; RUN: llc -mtriple=riscv32 -mattr=+d,+zvfh,+v,+experimental-zvfbfa \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA
; RUN: llc -mtriple=riscv64 -mattr=+d,+zvfh,+v,+experimental-zvfbfa \
; RUN:     -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFBFA

define <vscale x 1 x double> @vfwmul_vv_nxv1f64(<vscale x 1 x float> %va, <vscale x 1 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv1f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfwmul.vv v10, v8, v9
; CHECK-NEXT:    vmv1r.v v8, v10
; CHECK-NEXT:    ret
  %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
  %vd = fpext <vscale x 1 x float> %vb to <vscale x 1 x double>
  %ve = fmul <vscale x 1 x double> %vc, %vd
  ret <vscale x 1 x double> %ve
}

define <vscale x 1 x double> @vfwmul_vf_nxv1f64(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv1f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfwmul.vf v9, v8, fa0
; CHECK-NEXT:    vmv1r.v v8, v9
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 1 x float> poison, float %b, i32 0
  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
  %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
  %vd = fpext <vscale x 1 x float> %splat to <vscale x 1 x double>
  %ve = fmul <vscale x 1 x double> %vc, %vd
  ret <vscale x 1 x double> %ve
}

define <vscale x 1 x double> @vfwmul_vf_nxv1f64_2(<vscale x 1 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv1f64_2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfwmul.vf v9, v8, fa0
; CHECK-NEXT:    vmv1r.v v8, v9
; CHECK-NEXT:    ret
  %fpext = fpext float %b to double
  %head = insertelement <vscale x 1 x double> poison, double %fpext, i32 0
  %splat = shufflevector <vscale x 1 x double> %head, <vscale x 1 x double> poison, <vscale x 1 x i32> zeroinitializer
  %vc = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
  %ve = fmul <vscale x 1 x double> %vc, %splat
  ret <vscale x 1 x double> %ve
}

define <vscale x 2 x double> @vfwmul_vv_nxv2f64(<vscale x 2 x float> %va, <vscale x 2 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv1r.v v10, v9
; CHECK-NEXT:    vmv1r.v v11, v8
; CHECK-NEXT:    vfwmul.vv v8, v11, v10
; CHECK-NEXT:    ret
  %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
  %vd = fpext <vscale x 2 x float> %vb to <vscale x 2 x double>
  %ve = fmul <vscale x 2 x double> %vc, %vd
  ret <vscale x 2 x double> %ve
}

define <vscale x 2 x double> @vfwmul_vf_nxv2f64(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv2f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv1r.v v10, v8
; CHECK-NEXT:    vfwmul.vf v8, v10, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 2 x float> poison, float %b, i32 0
  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
  %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
  %vd = fpext <vscale x 2 x float> %splat to <vscale x 2 x double>
  %ve = fmul <vscale x 2 x double> %vc, %vd
  ret <vscale x 2 x double> %ve
}

define <vscale x 2 x double> @vfwmul_vf_nxv2f64_2(<vscale x 2 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv2f64_2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT:    vmv1r.v v10, v8
; CHECK-NEXT:    vfwmul.vf v8, v10, fa0
; CHECK-NEXT:    ret
  %fpext = fpext float %b to double
  %head = insertelement <vscale x 2 x double> poison, double %fpext, i32 0
  %splat = shufflevector <vscale x 2 x double> %head, <vscale x 2 x double> poison, <vscale x 2 x i32> zeroinitializer
  %vc = fpext <vscale x 2 x float> %va to <vscale x 2 x double>
  %ve = fmul <vscale x 2 x double> %vc, %splat
  ret <vscale x 2 x double> %ve
}

define <vscale x 4 x double> @vfwmul_vv_nxv4f64(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv2r.v v12, v10
; CHECK-NEXT:    vmv2r.v v14, v8
; CHECK-NEXT:    vfwmul.vv v8, v14, v12
; CHECK-NEXT:    ret
  %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
  %vd = fpext <vscale x 4 x float> %vb to <vscale x 4 x double>
  %ve = fmul <vscale x 4 x double> %vc, %vd
  ret <vscale x 4 x double> %ve
}

define <vscale x 4 x double> @vfwmul_vf_nxv4f64(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv4f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv2r.v v12, v8
; CHECK-NEXT:    vfwmul.vf v8, v12, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 4 x float> poison, float %b, i32 0
  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
  %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
  %vd = fpext <vscale x 4 x float> %splat to <vscale x 4 x double>
  %ve = fmul <vscale x 4 x double> %vc, %vd
  ret <vscale x 4 x double> %ve
}

define <vscale x 4 x double> @vfwmul_vf_nxv4f64_2(<vscale x 4 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv4f64_2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT:    vmv2r.v v12, v8
; CHECK-NEXT:    vfwmul.vf v8, v12, fa0
; CHECK-NEXT:    ret
  %fpext = fpext float %b to double
  %head = insertelement <vscale x 4 x double> poison, double %fpext, i32 0
  %splat = shufflevector <vscale x 4 x double> %head, <vscale x 4 x double> poison, <vscale x 4 x i32> zeroinitializer
  %vc = fpext <vscale x 4 x float> %va to <vscale x 4 x double>
  %ve = fmul <vscale x 4 x double> %vc, %splat
  ret <vscale x 4 x double> %ve
}

define <vscale x 8 x double> @vfwmul_vv_nxv8f64(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfwmul_vv_nxv8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vmv4r.v v16, v12
; CHECK-NEXT:    vmv4r.v v20, v8
; CHECK-NEXT:    vfwmul.vv v8, v20, v16
; CHECK-NEXT:    ret
  %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
  %vd = fpext <vscale x 8 x float> %vb to <vscale x 8 x double>
  %ve = fmul <vscale x 8 x double> %vc, %vd
  ret <vscale x 8 x double> %ve
}

define <vscale x 8 x double> @vfwmul_vf_nxv8f64(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv8f64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vmv4r.v v16, v8
; CHECK-NEXT:    vfwmul.vf v8, v16, fa0
; CHECK-NEXT:    ret
  %head = insertelement <vscale x 8 x float> poison, float %b, i32 0
  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
  %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
  %vd = fpext <vscale x 8 x float> %splat to <vscale x 8 x double>
  %ve = fmul <vscale x 8 x double> %vc, %vd
  ret <vscale x 8 x double> %ve
}

define <vscale x 8 x double> @vfwmul_vf_nxv8f64_2(<vscale x 8 x float> %va, float %b) {
; CHECK-LABEL: vfwmul_vf_nxv8f64_2:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT:    vmv4r.v v16, v8
; CHECK-NEXT:    vfwmul.vf v8, v16, fa0
; CHECK-NEXT:    ret
  %fpext = fpext float %b to double
  %head = insertelement <vscale x 8 x double> poison, double %fpext, i32 0
  %splat = shufflevector <vscale x 8 x double> %head, <vscale x 8 x double> poison, <vscale x 8 x i32> zeroinitializer
  %vc = fpext <vscale x 8 x float> %va to <vscale x 8 x double>
  %ve = fmul <vscale x 8 x double> %vc, %splat
  ret <vscale x 8 x double> %ve
}

define <vscale x 1 x double> @vfwmul_vv_nxv1f64_same_op(<vscale x 1 x float> %va) {
; CHECK-LABEL: vfwmul_vv_nxv1f64_same_op:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT:    vfwmul.vv v9, v8, v8
; CHECK-NEXT:    vmv1r.v v8, v9
; CHECK-NEXT:    ret
  %vb = fpext <vscale x 1 x float> %va to <vscale x 1 x double>
  %vc = fmul <vscale x 1 x double> %vb, %vb
  ret <vscale x 1 x double> %vc
}

define <vscale x 1 x float> @vfwmul_vv_nxv1f32(<vscale x 1 x bfloat> %va, <vscale x 1 x bfloat> %vb) {
; ZVFH-LABEL: vfwmul_vv_nxv1f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v8, v9
; ZVFH-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFH-NEXT:    vfmul.vv v8, v10, v8
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vv_nxv1f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfwmul.vv v10, v8, v9
; ZVFBFA-NEXT:    vmv1r.v v8, v10
; ZVFBFA-NEXT:    ret
  %vc = fpext <vscale x 1 x bfloat> %va to <vscale x 1 x float>
  %vd = fpext <vscale x 1 x bfloat> %vb to <vscale x 1 x float>
  %ve = fmul <vscale x 1 x float> %vc, %vd
  ret <vscale x 1 x float> %ve
}

define <vscale x 1 x float> @vfwmul_vf_nxv1f32(<vscale x 1 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv1f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    vsetvli a1, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v9, v8
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v9, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv1f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfwmul.vf v9, v8, fa0
; ZVFBFA-NEXT:    vmv1r.v v8, v9
; ZVFBFA-NEXT:    ret
  %head = insertelement <vscale x 1 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
  %vc = fpext <vscale x 1 x bfloat> %va to <vscale x 1 x float>
  %vd = fpext <vscale x 1 x bfloat> %splat to <vscale x 1 x float>
  %ve = fmul <vscale x 1 x float> %vc, %vd
  ret <vscale x 1 x float> %ve
}

define <vscale x 1 x float> @vfwmul_vf_nxv1f32_2(<vscale x 1 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv1f32_2:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v9, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv1f32_2:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfwmul.vf v9, v8, fa0
; ZVFBFA-NEXT:    vmv1r.v v8, v9
; ZVFBFA-NEXT:    ret
  %fpext = fpext bfloat %b to float
  %head = insertelement <vscale x 1 x float> poison, float %fpext, i32 0
  %splat = shufflevector <vscale x 1 x float> %head, <vscale x 1 x float> poison, <vscale x 1 x i32> zeroinitializer
  %vc = fpext <vscale x 1 x bfloat> %va to <vscale x 1 x float>
  %ve = fmul <vscale x 1 x float> %vc, %splat
  ret <vscale x 1 x float> %ve
}

define <vscale x 2 x float> @vfwmul_vv_nxv2f32(<vscale x 2 x bfloat> %va, <vscale x 2 x bfloat> %vb) {
; ZVFH-LABEL: vfwmul_vv_nxv2f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v8, v9
; ZVFH-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFH-NEXT:    vfmul.vv v8, v10, v8
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vv_nxv2f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfwmul.vv v10, v8, v9
; ZVFBFA-NEXT:    vmv1r.v v8, v10
; ZVFBFA-NEXT:    ret
  %vc = fpext <vscale x 2 x bfloat> %va to <vscale x 2 x float>
  %vd = fpext <vscale x 2 x bfloat> %vb to <vscale x 2 x float>
  %ve = fmul <vscale x 2 x float> %vc, %vd
  ret <vscale x 2 x float> %ve
}

define <vscale x 2 x float> @vfwmul_vf_nxv2f32(<vscale x 2 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv2f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    vsetvli a1, zero, e16, mf2, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v9, v8
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v9, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv2f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfwmul.vf v9, v8, fa0
; ZVFBFA-NEXT:    vmv1r.v v8, v9
; ZVFBFA-NEXT:    ret
  %head = insertelement <vscale x 2 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
  %vc = fpext <vscale x 2 x bfloat> %va to <vscale x 2 x float>
  %vd = fpext <vscale x 2 x bfloat> %splat to <vscale x 2 x float>
  %ve = fmul <vscale x 2 x float> %vc, %vd
  ret <vscale x 2 x float> %ve
}

define <vscale x 2 x float> @vfwmul_vf_nxv2f32_2(<vscale x 2 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv2f32_2:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf2, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v9, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv2f32_2:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf2, ta, ma
; ZVFBFA-NEXT:    vfwmul.vf v9, v8, fa0
; ZVFBFA-NEXT:    vmv1r.v v8, v9
; ZVFBFA-NEXT:    ret
  %fpext = fpext bfloat %b to float
  %head = insertelement <vscale x 2 x float> poison, float %fpext, i32 0
  %splat = shufflevector <vscale x 2 x float> %head, <vscale x 2 x float> poison, <vscale x 2 x i32> zeroinitializer
  %vc = fpext <vscale x 2 x bfloat> %va to <vscale x 2 x float>
  %ve = fmul <vscale x 2 x float> %vc, %splat
  ret <vscale x 2 x float> %ve
}

define <vscale x 4 x float> @vfwmul_vv_nxv4f32(<vscale x 4 x bfloat> %va, <vscale x 4 x bfloat> %vb) {
; ZVFH-LABEL: vfwmul_vv_nxv4f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v12, v9
; ZVFH-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFH-NEXT:    vfmul.vv v8, v10, v12
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vv_nxv4f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vmv1r.v v10, v9
; ZVFBFA-NEXT:    vmv1r.v v11, v8
; ZVFBFA-NEXT:    vfwmul.vv v8, v11, v10
; ZVFBFA-NEXT:    ret
  %vc = fpext <vscale x 4 x bfloat> %va to <vscale x 4 x float>
  %vd = fpext <vscale x 4 x bfloat> %vb to <vscale x 4 x float>
  %ve = fmul <vscale x 4 x float> %vc, %vd
  ret <vscale x 4 x float> %ve
}

define <vscale x 4 x float> @vfwmul_vf_nxv4f32(<vscale x 4 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv4f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    vsetvli a1, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v10, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv4f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vmv1r.v v10, v8
; ZVFBFA-NEXT:    vfwmul.vf v8, v10, fa0
; ZVFBFA-NEXT:    ret
  %head = insertelement <vscale x 4 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
  %vc = fpext <vscale x 4 x bfloat> %va to <vscale x 4 x float>
  %vd = fpext <vscale x 4 x bfloat> %splat to <vscale x 4 x float>
  %ve = fmul <vscale x 4 x float> %vc, %vd
  ret <vscale x 4 x float> %ve
}

define <vscale x 4 x float> @vfwmul_vf_nxv4f32_2(<vscale x 4 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv4f32_2:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli a0, zero, e16, m1, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v10, v8
; ZVFH-NEXT:    vsetvli zero, zero, e32, m2, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v10, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv4f32_2:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m1, ta, ma
; ZVFBFA-NEXT:    vmv1r.v v10, v8
; ZVFBFA-NEXT:    vfwmul.vf v8, v10, fa0
; ZVFBFA-NEXT:    ret
  %fpext = fpext bfloat %b to float
  %head = insertelement <vscale x 4 x float> poison, float %fpext, i32 0
  %splat = shufflevector <vscale x 4 x float> %head, <vscale x 4 x float> poison, <vscale x 4 x i32> zeroinitializer
  %vc = fpext <vscale x 4 x bfloat> %va to <vscale x 4 x float>
  %ve = fmul <vscale x 4 x float> %vc, %splat
  ret <vscale x 4 x float> %ve
}

define <vscale x 8 x float> @vfwmul_vv_nxv8f32(<vscale x 8 x bfloat> %va, <vscale x 8 x bfloat> %vb) {
; ZVFH-LABEL: vfwmul_vv_nxv8f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v12, v8
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v16, v10
; ZVFH-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFH-NEXT:    vfmul.vv v8, v12, v16
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vv_nxv8f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vmv2r.v v12, v10
; ZVFBFA-NEXT:    vmv2r.v v14, v8
; ZVFBFA-NEXT:    vfwmul.vv v8, v14, v12
; ZVFBFA-NEXT:    ret
  %vc = fpext <vscale x 8 x bfloat> %va to <vscale x 8 x float>
  %vd = fpext <vscale x 8 x bfloat> %vb to <vscale x 8 x float>
  %ve = fmul <vscale x 8 x float> %vc, %vd
  ret <vscale x 8 x float> %ve
}

define <vscale x 8 x float> @vfwmul_vf_nxv8f32(<vscale x 8 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv8f32:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v12, v8
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v12, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv8f32:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vmv2r.v v12, v8
; ZVFBFA-NEXT:    vfwmul.vf v8, v12, fa0
; ZVFBFA-NEXT:    ret
  %head = insertelement <vscale x 8 x bfloat> poison, bfloat %b, i32 0
  %splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
  %vc = fpext <vscale x 8 x bfloat> %va to <vscale x 8 x float>
  %vd = fpext <vscale x 8 x bfloat> %splat to <vscale x 8 x float>
  %ve = fmul <vscale x 8 x float> %vc, %vd
  ret <vscale x 8 x float> %ve
}

define <vscale x 8 x float> @vfwmul_vf_nxv8f32_2(<vscale x 8 x bfloat> %va, bfloat %b) {
; ZVFH-LABEL: vfwmul_vf_nxv8f32_2:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    fmv.x.w a0, fa0
; ZVFH-NEXT:    slli a0, a0, 16
; ZVFH-NEXT:    fmv.w.x fa5, a0
; ZVFH-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v12, v8
; ZVFH-NEXT:    vsetvli zero, zero, e32, m4, ta, ma
; ZVFH-NEXT:    vfmul.vf v8, v12, fa5
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vf_nxv8f32_2:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, m2, ta, ma
; ZVFBFA-NEXT:    vmv2r.v v12, v8
; ZVFBFA-NEXT:    vfwmul.vf v8, v12, fa0
; ZVFBFA-NEXT:    ret
  %fpext = fpext bfloat %b to float
  %head = insertelement <vscale x 8 x float> poison, float %fpext, i32 0
  %splat = shufflevector <vscale x 8 x float> %head, <vscale x 8 x float> poison, <vscale x 8 x i32> zeroinitializer
  %vc = fpext <vscale x 8 x bfloat> %va to <vscale x 8 x float>
  %ve = fmul <vscale x 8 x float> %vc, %splat
  ret <vscale x 8 x float> %ve
}

define <vscale x 1 x float> @vfwmul_vv_nxv1f32_same_op(<vscale x 1 x bfloat> %va) {
; ZVFH-LABEL: vfwmul_vv_nxv1f32_same_op:
; ZVFH:       # %bb.0:
; ZVFH-NEXT:    vsetvli a0, zero, e16, mf4, ta, ma
; ZVFH-NEXT:    vfwcvtbf16.f.f.v v9, v8
; ZVFH-NEXT:    vsetvli zero, zero, e32, mf2, ta, ma
; ZVFH-NEXT:    vfmul.vv v8, v9, v9
; ZVFH-NEXT:    ret
;
; ZVFBFA-LABEL: vfwmul_vv_nxv1f32_same_op:
; ZVFBFA:       # %bb.0:
; ZVFBFA-NEXT:    vsetvli a0, zero, e16alt, mf4, ta, ma
; ZVFBFA-NEXT:    vfwmul.vv v9, v8, v8
; ZVFBFA-NEXT:    vmv1r.v v8, v9
; ZVFBFA-NEXT:    ret
  %vb = fpext <vscale x 1 x bfloat> %va to <vscale x 1 x float>
  %vc = fmul <vscale x 1 x float> %vb, %vb
  ret <vscale x 1 x float> %vc
}