; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -verify-machineinstrs | FileCheck %s define @sew1_srli( %a, %b) { ; CHECK-LABEL: sew1_srli: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: vmand.mm v0, v0, v8 ; CHECK-NEXT: ret %vlmax = call i32 @llvm.vscale() %x = call @llvm.vp.and.nxv1i1( %a, %b, splat (i1 true), i32 %vlmax) ret %x } define @sew64_srli( %a, %b) { ; CHECK-LABEL: sew64_srli: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: ret %vlmax = call i32 @llvm.vscale() %x = call @llvm.vp.add.nxv1i64( %a, %b, splat (i1 true), i32 %vlmax) ret %x } define @sew64( %a, %b) { ; CHECK-LABEL: sew64: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vscale = call i32 @llvm.vscale() %vlmax = shl i32 %vscale, 3 %x = call @llvm.vp.add.nxv8i64( %a, %b, splat (i1 true), i32 %vlmax) ret %x } define @sew32_sll( %a, %b) { ; CHECK-LABEL: sew32_sll: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v16 ; CHECK-NEXT: ret %vscale = call i32 @llvm.vscale() %vlmax = shl i32 %vscale, 4 %x = call @llvm.vp.add.nxv16i32( %a, %b, splat (i1 true), i32 %vlmax) ret %x }