; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+f,+v -verify-machineinstrs < %s | FileCheck %s define @test_reverse_load_combiner(* %ptr, i32 zeroext %evl) { ; CHECK-LABEL: test_reverse_load_combiner: ; CHECK: # %bb.0: ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: add a0, a2, a0 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: li a2, -4 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a2 ; CHECK-NEXT: ret %load = call @llvm.vp.load.nxv2f32.p0nxv2f32(* %ptr, splat (i1 true), i32 %evl) %rev = call @llvm.experimental.vp.reverse.nxv2f32( %load, splat (i1 true), i32 %evl) ret %rev } define @test_load_mask_is_vp_reverse(* %ptr, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_load_mask_is_vp_reverse: ; CHECK: # %bb.0: ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: add a0, a2, a0 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: li a2, -4 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a2, v0.t ; CHECK-NEXT: ret %loadmask = call @llvm.experimental.vp.reverse.nxv2i1( %mask, splat (i1 true), i32 %evl) %load = call @llvm.vp.load.nxv2f32.p0nxv2f32(* %ptr, %loadmask, i32 %evl) %rev = call @llvm.experimental.vp.reverse.nxv2f32( %load, splat (i1 true), i32 %evl) ret %rev } define @test_load_mask_is_vp_reverse_with_mask(* %ptr, %mask, %revmask, i32 zeroext %evl) { ; CHECK-LABEL: test_load_mask_is_vp_reverse_with_mask: ; CHECK: # %bb.0: ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: add a0, a2, a0 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: li a2, -4 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a2, v0.t ; CHECK-NEXT: ret %loadmask = call @llvm.experimental.vp.reverse.nxv2i1( %mask, %revmask, i32 %evl) %load = call @llvm.vp.load.nxv2f32.p0nxv2f32(* %ptr, %loadmask, i32 %evl) %rev = call @llvm.experimental.vp.reverse.nxv2f32( %load, splat (i1 true), i32 %evl) ret %rev } define @test_load_mask_not_all_one(* %ptr, %notallones, i32 zeroext %evl) { ; CHECK-LABEL: test_load_mask_not_all_one: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v9, (a0), v0.t ; CHECK-NEXT: vid.v v8, v0.t ; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: vrsub.vx v10, v8, a1, v0.t ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret %load = call @llvm.vp.load.nxv2f32.p0nxv2f32(* %ptr, %notallones, i32 %evl) %rev = call @llvm.experimental.vp.reverse.nxv2f32( %load, %notallones, i32 %evl) ret %rev } define @test_load_reverse_mask_not_all_one(ptr %ptr, %notallones, i32 zeroext %evl) { ; CHECK-LABEL: test_load_reverse_mask_not_all_one: ; CHECK: # %bb.0: ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: add a0, a2, a0 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: li a2, -4 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a2 ; CHECK-NEXT: ret %load = call @llvm.vp.load.nxv2f32.p0nxv2f32(ptr %ptr, splat (i1 true), i32 %evl) %rev = call @llvm.experimental.vp.reverse.nxv2f32( %load, %notallones, i32 %evl) ret %rev } define @test_different_evl(* %ptr, %mask, i32 zeroext %evl1, i32 zeroext %evl2) { ; CHECK-LABEL: test_different_evl: ; CHECK: # %bb.0: ; CHECK-NEXT: addi a3, a1, -1 ; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 ; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; CHECK-NEXT: vrsub.vx v8, v8, a3 ; CHECK-NEXT: vsetvli zero, zero, e8, mf4, ta, ma ; CHECK-NEXT: vmerge.vim v9, v9, 1, v0 ; CHECK-NEXT: vrgatherei16.vv v10, v9, v8 ; CHECK-NEXT: vmsne.vi v0, v10, 0 ; CHECK-NEXT: vsetvli zero, a2, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v9, (a0), v0.t ; CHECK-NEXT: addi a2, a2, -1 ; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vrsub.vx v10, v8, a2 ; CHECK-NEXT: vrgather.vv v8, v9, v10 ; CHECK-NEXT: ret %loadmask = call @llvm.experimental.vp.reverse.nxv2i1( %mask, splat (i1 true), i32 %evl1) %load = call @llvm.vp.load.nxv2f32.p0nxv2f32(* %ptr, %loadmask, i32 %evl2) %rev = call @llvm.experimental.vp.reverse.nxv2f32( %load, splat (i1 true), i32 %evl2) ret %rev } define @test_reverse_load_combiner_splice(ptr %ptr, i32 zeroext %evl) { ; CHECK-LABEL: test_reverse_load_combiner_splice: ; CHECK: # %bb.0: ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: add a0, a2, a0 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: li a2, -4 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a2 ; CHECK-NEXT: ret %load = call @llvm.vp.load(ptr %ptr, splat (i1 true), i32 %evl) %rev = call @llvm.vector.reverse( %load) %splice = call @llvm.vector.splice.right( %rev, poison, i32 %evl) ret %splice } define @test_load_mask_is_reverse_splice(ptr %ptr, %mask, i32 zeroext %evl) { ; CHECK-LABEL: test_load_mask_is_reverse_splice: ; CHECK: # %bb.0: ; CHECK-NEXT: slli a2, a1, 2 ; CHECK-NEXT: add a0, a2, a0 ; CHECK-NEXT: addi a0, a0, -4 ; CHECK-NEXT: li a2, -4 ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vlse32.v v8, (a0), a2, v0.t ; CHECK-NEXT: ret %loadmask.rev = call @llvm.vector.reverse( %mask) %loadmask.splice = call @llvm.vector.splice.right( %loadmask.rev, poison, i32 %evl) %load = call @llvm.vp.load(ptr %ptr, %loadmask.splice, i32 %evl) %rev = call @llvm.vector.reverse( %load) %splice = call @llvm.vector.splice.right( %rev, poison, i32 %evl) ret %splice } define @test_different_evl_splice(ptr %ptr, i32 zeroext %evl1, i32 zeroext %evl2) { ; CHECK-LABEL: test_different_evl_splice: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vle32.v v8, (a0) ; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vid.v v9 ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: addi a1, a0, -1 ; CHECK-NEXT: vrsub.vx v9, v9, a1 ; CHECK-NEXT: vrgather.vv v10, v8, v9 ; CHECK-NEXT: sub a0, a0, a2 ; CHECK-NEXT: vslidedown.vx v8, v10, a0 ; CHECK-NEXT: ret %load = call @llvm.vp.load(ptr %ptr, splat (i1 true), i32 %evl1) %rev = call @llvm.vector.reverse( %load) %splice = call @llvm.vector.splice.right( %rev, poison, i32 %evl2) ret %splice }