; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=riscv32 -mattr=+m | FileCheck %s --check-prefixes=RV32I-M
; RUN: llc < %s -mtriple=riscv64 -mattr=+m | FileCheck %s --check-prefixes=RV64I-M
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-ialu | \
; RUN:   FileCheck %s --check-prefixes=RV32I-SFB-M
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-ialu | \
; RUN:   FileCheck %s --check-prefixes=RV64I-SFB-M
; RUN: llc < %s -mtriple=riscv32 -mattr=+m,+short-forward-branch-imul | \
; RUN:   FileCheck %s --check-prefixes=RV32I-SFBIMul-M
; RUN: llc < %s -mtriple=riscv64 -mattr=+m,+short-forward-branch-imul | \
; RUN:   FileCheck %s --check-prefixes=RV64I-SFBIMul-M

define i32 @select_example_mul_i32(i32 %a, i32 %b, i1 zeroext %x, i32 %y) {
; RV32I-M-LABEL: select_example_mul_i32:
; RV32I-M:       # %bb.0: # %entry
; RV32I-M-NEXT:    beqz a2, .LBB0_2
; RV32I-M-NEXT:  # %bb.1:
; RV32I-M-NEXT:    mul a1, a0, a3
; RV32I-M-NEXT:  .LBB0_2: # %entry
; RV32I-M-NEXT:    mv a0, a1
; RV32I-M-NEXT:    ret
;
; RV64I-M-LABEL: select_example_mul_i32:
; RV64I-M:       # %bb.0: # %entry
; RV64I-M-NEXT:    beqz a2, .LBB0_2
; RV64I-M-NEXT:  # %bb.1:
; RV64I-M-NEXT:    mulw a1, a0, a3
; RV64I-M-NEXT:  .LBB0_2: # %entry
; RV64I-M-NEXT:    mv a0, a1
; RV64I-M-NEXT:    ret
;
; RV32I-SFB-M-LABEL: select_example_mul_i32:
; RV32I-SFB-M:       # %bb.0: # %entry
; RV32I-SFB-M-NEXT:    mul a0, a0, a3
; RV32I-SFB-M-NEXT:    bnez a2, .LBB0_2
; RV32I-SFB-M-NEXT:  # %bb.1: # %entry
; RV32I-SFB-M-NEXT:    mv a0, a1
; RV32I-SFB-M-NEXT:  .LBB0_2: # %entry
; RV32I-SFB-M-NEXT:    ret
;
; RV64I-SFB-M-LABEL: select_example_mul_i32:
; RV64I-SFB-M:       # %bb.0: # %entry
; RV64I-SFB-M-NEXT:    mulw a0, a0, a3
; RV64I-SFB-M-NEXT:    bnez a2, .LBB0_2
; RV64I-SFB-M-NEXT:  # %bb.1: # %entry
; RV64I-SFB-M-NEXT:    mv a0, a1
; RV64I-SFB-M-NEXT:  .LBB0_2: # %entry
; RV64I-SFB-M-NEXT:    ret
;
; RV32I-SFBIMul-M-LABEL: select_example_mul_i32:
; RV32I-SFBIMul-M:       # %bb.0: # %entry
; RV32I-SFBIMul-M-NEXT:    beqz a2, .LBB0_2
; RV32I-SFBIMul-M-NEXT:  # %bb.1: # %entry
; RV32I-SFBIMul-M-NEXT:    mul a1, a0, a3
; RV32I-SFBIMul-M-NEXT:  .LBB0_2: # %entry
; RV32I-SFBIMul-M-NEXT:    mv a0, a1
; RV32I-SFBIMul-M-NEXT:    ret
;
; RV64I-SFBIMul-M-LABEL: select_example_mul_i32:
; RV64I-SFBIMul-M:       # %bb.0: # %entry
; RV64I-SFBIMul-M-NEXT:    mulw a0, a0, a3
; RV64I-SFBIMul-M-NEXT:    bnez a2, .LBB0_2
; RV64I-SFBIMul-M-NEXT:  # %bb.1: # %entry
; RV64I-SFBIMul-M-NEXT:    mv a0, a1
; RV64I-SFBIMul-M-NEXT:  .LBB0_2: # %entry
; RV64I-SFBIMul-M-NEXT:    ret
entry:
  %res = mul i32 %a, %y
  %sel = select i1 %x, i32 %res, i32 %b
  ret i32 %sel
}

define i64 @select_example_mul_i64(i64 %a, i64 %b, i1 zeroext %x, i64 %y) {
; RV32I-M-LABEL: select_example_mul_i64:
; RV32I-M:       # %bb.0: # %entry
; RV32I-M-NEXT:    beqz a4, .LBB1_2
; RV32I-M-NEXT:  # %bb.1:
; RV32I-M-NEXT:    mul a2, a0, a6
; RV32I-M-NEXT:    mulhu a3, a0, a5
; RV32I-M-NEXT:    mul a1, a1, a5
; RV32I-M-NEXT:    add a2, a3, a2
; RV32I-M-NEXT:    add a3, a2, a1
; RV32I-M-NEXT:    mul a2, a0, a5
; RV32I-M-NEXT:  .LBB1_2: # %entry
; RV32I-M-NEXT:    mv a0, a2
; RV32I-M-NEXT:    mv a1, a3
; RV32I-M-NEXT:    ret
;
; RV64I-M-LABEL: select_example_mul_i64:
; RV64I-M:       # %bb.0: # %entry
; RV64I-M-NEXT:    beqz a2, .LBB1_2
; RV64I-M-NEXT:  # %bb.1:
; RV64I-M-NEXT:    mul a1, a0, a3
; RV64I-M-NEXT:  .LBB1_2: # %entry
; RV64I-M-NEXT:    mv a0, a1
; RV64I-M-NEXT:    ret
;
; RV32I-SFB-M-LABEL: select_example_mul_i64:
; RV32I-SFB-M:       # %bb.0: # %entry
; RV32I-SFB-M-NEXT:    mul a6, a0, a6
; RV32I-SFB-M-NEXT:    mulhu a7, a0, a5
; RV32I-SFB-M-NEXT:    mul a1, a1, a5
; RV32I-SFB-M-NEXT:    mul a0, a0, a5
; RV32I-SFB-M-NEXT:    add a6, a7, a6
; RV32I-SFB-M-NEXT:    beqz a4, .LBB1_2
; RV32I-SFB-M-NEXT:  # %bb.1: # %entry
; RV32I-SFB-M-NEXT:    add a3, a6, a1
; RV32I-SFB-M-NEXT:  .LBB1_2: # %entry
; RV32I-SFB-M-NEXT:    bnez a4, .LBB1_4
; RV32I-SFB-M-NEXT:  # %bb.3: # %entry
; RV32I-SFB-M-NEXT:    mv a0, a2
; RV32I-SFB-M-NEXT:  .LBB1_4: # %entry
; RV32I-SFB-M-NEXT:    mv a1, a3
; RV32I-SFB-M-NEXT:    ret
;
; RV64I-SFB-M-LABEL: select_example_mul_i64:
; RV64I-SFB-M:       # %bb.0: # %entry
; RV64I-SFB-M-NEXT:    mul a0, a0, a3
; RV64I-SFB-M-NEXT:    bnez a2, .LBB1_2
; RV64I-SFB-M-NEXT:  # %bb.1: # %entry
; RV64I-SFB-M-NEXT:    mv a0, a1
; RV64I-SFB-M-NEXT:  .LBB1_2: # %entry
; RV64I-SFB-M-NEXT:    ret
;
; RV32I-SFBIMul-M-LABEL: select_example_mul_i64:
; RV32I-SFBIMul-M:       # %bb.0: # %entry
; RV32I-SFBIMul-M-NEXT:    mul a6, a0, a6
; RV32I-SFBIMul-M-NEXT:    mulhu a7, a0, a5
; RV32I-SFBIMul-M-NEXT:    mul a1, a1, a5
; RV32I-SFBIMul-M-NEXT:    add a6, a7, a6
; RV32I-SFBIMul-M-NEXT:    beqz a4, .LBB1_2
; RV32I-SFBIMul-M-NEXT:  # %bb.1: # %entry
; RV32I-SFBIMul-M-NEXT:    add a3, a6, a1
; RV32I-SFBIMul-M-NEXT:  .LBB1_2: # %entry
; RV32I-SFBIMul-M-NEXT:    beqz a4, .LBB1_4
; RV32I-SFBIMul-M-NEXT:  # %bb.3: # %entry
; RV32I-SFBIMul-M-NEXT:    mul a2, a0, a5
; RV32I-SFBIMul-M-NEXT:  .LBB1_4: # %entry
; RV32I-SFBIMul-M-NEXT:    mv a0, a2
; RV32I-SFBIMul-M-NEXT:    mv a1, a3
; RV32I-SFBIMul-M-NEXT:    ret
;
; RV64I-SFBIMul-M-LABEL: select_example_mul_i64:
; RV64I-SFBIMul-M:       # %bb.0: # %entry
; RV64I-SFBIMul-M-NEXT:    beqz a2, .LBB1_2
; RV64I-SFBIMul-M-NEXT:  # %bb.1: # %entry
; RV64I-SFBIMul-M-NEXT:    mul a1, a0, a3
; RV64I-SFBIMul-M-NEXT:  .LBB1_2: # %entry
; RV64I-SFBIMul-M-NEXT:    mv a0, a1
; RV64I-SFBIMul-M-NEXT:    ret
entry:
  %res = mul i64 %a, %y
  %sel = select i1 %x, i64 %res, i64 %b
  ret i64 %sel
}