# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple thumbv6m-arm-none-eabi -run-pass regallocbasic %s -o - | FileCheck %s # RUN: llc -mtriple thumbv6m-arm-none-eabi -run-pass greedy %s -o - | FileCheck %s # RUN: llc -mtriple thumbv6m-arm-none-eabi -run-pass regallocfast %s -o - | FileCheck %s --check-prefix=FAST # RUN: llc -mtriple thumbv6m-arm-none-eabi -passes=regallocfast %s -o - | FileCheck %s --check-prefix=FAST # RUN: llc -mtriple thumbv6m-arm-none-eabi -passes=greedy %s -o - | FileCheck %s ... --- name: constraint_h alignment: 2 tracksRegLiveness: true registers: - { id: 0, class: tgpr } - { id: 1, class: hgpr } - { id: 2, class: tgpr } liveins: - { reg: '$r0', virtual-reg: '%0' } frameInfo: maxAlignment: 4 maxCallFrameSize: 0 localFrameSize: 4 stack: - { id: 0, size: 4, alignment: 4, local-offset: -4 } machineFunctionInfo: {} body: | bb.0.entry: liveins: $r0 ; CHECK-LABEL: name: constraint_h ; CHECK: liveins: $r0 ; CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0 ; CHECK: tSTRspi [[COPY]], %stack.0, 0, 14 /* CC::al */, $noreg ; CHECK: [[tLDRspi:%[0-9]+]]:tgpr = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg ; CHECK: [[COPY1:%[0-9]+]]:hgpr = COPY [[tLDRspi]] ; CHECK: INLINEASM &"mov r12, $0", sideeffect attdialect, reguse:hGPR, %1, clobber, implicit-def early-clobber $r12 ; CHECK: tBX_RET 14 /* CC::al */, $noreg ; FAST-LABEL: name: constraint_h ; FAST: liveins: $r0 ; FAST: tSTRspi killed renamable $r0, %stack.0, 0, 14 /* CC::al */, $noreg ; FAST: renamable $r0 = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg ; FAST: renamable $r8 = COPY killed renamable $r0 ; FAST: INLINEASM &"mov r12, $0", sideeffect attdialect, reguse:hGPR, killed renamable $r8, clobber, implicit-def dead early-clobber $r12 ; FAST: tBX_RET 14 /* CC::al */, $noreg %0:tgpr = COPY $r0 tSTRspi %0, %stack.0, 0, 14 /* CC::al */, $noreg %2:tgpr = tLDRspi %stack.0, 0, 14 /* CC::al */, $noreg %1:hgpr = COPY %2 INLINEASM &"mov r12, $0", sideeffect attdialect, reguse:hGPR, %1, clobber, implicit-def early-clobber $r12 tBX_RET 14 /* CC::al */, $noreg ...