# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s

# From bug #162644. The _wrong_ output of this test is to generate the
# body of the tail-predicated loop like this:
#
#     $q2 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q2
#     renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, renamable $lr :: (load unknown-size from %ir.13, align 4)
#     $q0 = MVE_VORR $q1, $q1, 0, $noreg, $noreg, undef $q0
#     renamable $q0 = MVE_VADDf32 killed renamable $q2, killed renamable $q3, 0, killed $noreg, renamable $lr, killed renamable $q0
#     $lr = MVE_LETP killed renamable $lr, %bb.1
#
# in which the second MVE_VORR, copying q1 into q0, is an invalid conversion of
# the input MQPRCopy, because it won't copy the vector lanes disabled by
# FPSCR.LTPSIZE, and those are needed in the output value of the loop.
#
# In the right output, that MQPRCopy is expanded into a pair of VMOVD copying
# d2,d3 into d0,d1 respectively, which are unaffected by LTPSIZE.

--- |
  target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
  target triple = "thumbv8.1m.main-unknown-none-eabihf"

  @inactive = dso_local local_unnamed_addr global <4 x float> zeroinitializer, align 16

  define <4 x float> @test_func(ptr %0, i32 %1) {
    %3 = load <4 x float>, ptr @inactive, align 16
    %4 = add i32 %1, 3
    %5 = call i32 @llvm.smin.i32(i32 %1, i32 4)
    %6 = sub i32 %4, %5
    %7 = lshr i32 %6, 2
    %8 = add nuw nsw i32 %7, 1
    %9 = call i32 @llvm.start.loop.iterations.i32(i32 %8)
    br label %10

  10:                                               ; preds = %10, %2
    %11 = phi <4 x float> [ splat (float 0x3FB99999A0000000), %2 ], [ %17, %10 ]
    %12 = phi i32 [ %1, %2 ], [ %19, %10 ]
    %13 = phi ptr [ %0, %2 ], [ %18, %10 ]
    %14 = phi i32 [ %9, %2 ], [ %20, %10 ]
    %15 = tail call <4 x i1> @llvm.arm.mve.vctp32(i32 %12)
    %16 = tail call <4 x float> @llvm.masked.load.v4f32.p0(ptr %13, i32 4, <4 x i1> %15, <4 x float> zeroinitializer)
    %17 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %11, <4 x float> %16, <4 x i1> %15, <4 x float> %3)
    %18 = getelementptr inbounds nuw i8, ptr %13, i32 16
    %19 = add i32 %12, -4
    %20 = call i32 @llvm.loop.decrement.reg.i32(i32 %14, i32 1)
    %21 = icmp ne i32 %20, 0
    br i1 %21, label %10, label %22

  22:                                               ; preds = %10
    ret <4 x float> %17
  }
...
---
name:            test_func
alignment:       4
legalized:       false
tracksRegLiveness: true
registers:       []
liveins:
  - { reg: '$r0', virtual-reg: '' }
  - { reg: '$r1', virtual-reg: '' }
stack:
  - { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
  - { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
      stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
body:             |
  ; CHECK-LABEL: name: test_func
  ; CHECK: bb.0 (%ir-block.2):
  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
  ; CHECK-NEXT:   liveins: $lr, $r0, $r1, $r7
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION def_cfa_offset 8
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $lr, -4
  ; CHECK-NEXT:   frame-setup CFI_INSTRUCTION offset $r7, -8
  ; CHECK-NEXT:   $r2 = t2MOVi16 target-flags(arm-lo16) @inactive, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @inactive, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   renamable $q1 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (dereferenceable load (s128) from @inactive)
  ; CHECK-NEXT:   $r3 = t2MOVi16 52429, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   $r3 = t2MOVTi16 killed $r3, 15820, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   renamable $q0 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q0
  ; CHECK-NEXT:   $lr = MVE_DLSTP_32 killed renamable $r1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1 (%ir-block.10, align 4):
  ; CHECK-NEXT:   successors: %bb.1(0x7c000000), %bb.2(0x04000000)
  ; CHECK-NEXT:   liveins: $lr, $d2, $d3, $q0, $r0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $q2 = MVE_VORR killed $q0, killed $q0, 0, $noreg, $noreg, undef $q2
  ; CHECK-NEXT:   renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 16, 0, $noreg, renamable $lr :: (load unknown-size from %ir.13, align 4)
  ; CHECK-NEXT:   $d0 = VMOVD $d2, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   $d1 = VMOVD $d3, 14 /* CC::al */, $noreg
  ; CHECK-NEXT:   renamable $q0 = MVE_VADDf32 killed renamable $q2, killed renamable $q3, 0, killed $noreg, renamable $lr, killed renamable $q0
  ; CHECK-NEXT:   $lr = MVE_LETP killed renamable $lr, %bb.1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2 (%ir-block.22):
  ; CHECK-NEXT:   liveins: $q0
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $q0
  bb.0 (%ir-block.2):
    successors: %bb.1(0x80000000)
    liveins: $r0, $r1, $r7, $lr

    frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
    frame-setup CFI_INSTRUCTION def_cfa_offset 8
    frame-setup CFI_INSTRUCTION offset $lr, -4
    frame-setup CFI_INSTRUCTION offset $r7, -8
    $r2 = t2MOVi16 target-flags(arm-lo16) @inactive, 14 /* CC::al */, $noreg
    tCMPi8 renamable $r1, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
    $r2 = t2MOVTi16 killed $r2, target-flags(arm-hi16) @inactive, 14 /* CC::al */, $noreg
    renamable $r3 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
    renamable $q1 = MVE_VLDRWU32 killed renamable $r2, 0, 0, $noreg, $noreg :: (dereferenceable load (s128) from @inactive)
    $r2 = tMOVr $r1, 14 /* CC::al */, $noreg
    t2IT 10, 8, implicit-def $itstate
    renamable $r2 = tMOVi8 $noreg, 4, 10 /* CC::ge */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
    renamable $r2, dead $cpsr = tSUBrr renamable $r1, killed renamable $r2, 14 /* CC::al */, $noreg
    renamable $r2, dead $cpsr = tADDi8 killed renamable $r2, 3, 14 /* CC::al */, $noreg
    renamable $r2 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r2, 19, 14 /* CC::al */, $noreg, $noreg
    $r3 = t2MOVi16 52429, 14 /* CC::al */, $noreg
    $r3 = t2MOVTi16 killed $r3, 15820, 14 /* CC::al */, $noreg
    renamable $q0 = MVE_VDUP32 killed renamable $r3, 0, $noreg, $noreg, undef renamable $q0
    renamable $lr = t2DoLoopStartTP killed renamable $r2, renamable $r1

  bb.1 (%ir-block.10, align 4):
    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
    liveins: $lr, $q0, $q1, $r0, $r1

    renamable $vpr = MVE_VCTP32 renamable $r1, 0, $noreg, $noreg
    $q2 = MQPRCopy killed $q0
    MVE_VPST 8, implicit $vpr
    renamable $r0, renamable $q3 = MVE_VLDRWU32_post killed renamable $r0, 16, 1, renamable $vpr, renamable $lr :: (load unknown-size from %ir.13, align 4)
    $q0 = MQPRCopy $q1
    MVE_VPST 8, implicit $vpr
    renamable $q0 = MVE_VADDf32 killed renamable $q2, killed renamable $q3, 1, killed renamable $vpr, renamable $lr, killed renamable $q0
    renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
    renamable $lr = t2LoopEndDec killed renamable $lr, %bb.1, implicit-def dead $cpsr
    tB %bb.2, 14 /* CC::al */, $noreg

  bb.2 (%ir-block.22):
    liveins: $q0

    frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $q0
...