; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc < %s -mtriple=thumbv8m.main-none-eabi -mattr=+mve | FileCheck %s ; Test that fptosi and fptoui work with just `+mve` (which implies `-mve.fp`), ; which means that float registers exist but float operations do not. define i32 @fptosi_sat_i32_f32(float %x) { ; CHECK-LABEL: fptosi_sat_i32_f32: ; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, r5, r6, lr} ; CHECK-NEXT: push {r4, r5, r6, lr} ; CHECK-NEXT: ldr r1, .LCPI0_0 ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: bl __aeabi_fcmpge ; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: bl __aeabi_f2iz ; CHECK-NEXT: ldr r1, .LCPI0_1 ; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: it eq ; CHECK-NEXT: moveq.w r6, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: it ne ; CHECK-NEXT: mvnne r6, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpun ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r6, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: pop {r4, r5, r6, pc} ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI0_0: ; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-NEXT: .LCPI0_1: ; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 %i = call i32 @llvm.fptosi.sat.i32.f32(float %x) ret i32 %i } define i32 @fptoui_sat_i32_f32(float %x) { ; CHECK-LABEL: fptoui_sat_i32_f32: ; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, r5, r7, lr} ; CHECK-NEXT: push {r4, r5, r7, lr} ; CHECK-NEXT: ldr r1, .LCPI1_0 ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: bl __aeabi_fcmpge ; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: bl __aeabi_f2uiz ; CHECK-NEXT: ldr r1, .LCPI1_1 ; CHECK-NEXT: cmp r5, #0 ; CHECK-NEXT: csel r5, r0, r5, ne ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: bl __aeabi_fcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne.w r5, #-1 ; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: pop {r4, r5, r7, pc} ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI1_0: ; CHECK-NEXT: .long 0x00000000 @ float 0 ; CHECK-NEXT: .LCPI1_1: ; CHECK-NEXT: .long 0x4f7fffff @ float 4.29496704E+9 %i = call i32 @llvm.fptoui.sat.i32.f32(float %x) ret i32 %i } define i64 @fptosi_sat_i64_f64(double %x) { ; CHECK-LABEL: fptosi_sat_i64_f64: ; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: mov r4, r1 ; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: bl __aeabi_d2lz ; CHECK-NEXT: vldr d0, .LCPI2_0 ; CHECK-NEXT: mov r7, r0 ; CHECK-NEXT: mov r5, r1 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: vmov r9, r8, d0 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r9 ; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: vldr d0, .LCPI2_1 ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: csel r7, r7, r0, ne ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: vmov r11, r10, d0 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r11 ; CHECK-NEXT: mov r3, r10 ; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r6 ; CHECK-NEXT: mov r3, r4 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne.w r7, #-1 ; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r9 ; CHECK-NEXT: mov r3, r8 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r7, #0 ; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r11 ; CHECK-NEXT: mov r3, r10 ; CHECK-NEXT: it eq ; CHECK-NEXT: moveq.w r5, #-2147483648 ; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r6 ; CHECK-NEXT: mov r3, r4 ; CHECK-NEXT: it ne ; CHECK-NEXT: mvnne r5, #-2147483648 ; CHECK-NEXT: bl __aeabi_dcmpun ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r1, r5 ; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI2_0: ; CHECK-NEXT: .long 0 @ double -9.2233720368547758E+18 ; CHECK-NEXT: .long 3286237184 ; CHECK-NEXT: .LCPI2_1: ; CHECK-NEXT: .long 4294967295 @ double 9.2233720368547748E+18 ; CHECK-NEXT: .long 1138753535 %i = call i64 @llvm.fptosi.sat.i64.f64(double %x) ret i64 %i } define i64 @fptosu_sat_i64_f64(double %x) { ; CHECK-LABEL: fptosu_sat_i64_f64: ; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-NEXT: .pad #4 ; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: mov r4, r1 ; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: bl __aeabi_d2ulz ; CHECK-NEXT: vldr d0, .LCPI3_0 ; CHECK-NEXT: mov r7, r0 ; CHECK-NEXT: mov r6, r1 ; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: vmov r10, r9, d0 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: vldr d0, .LCPI3_1 ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: csel r7, r7, r0, ne ; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: vmov r8, r11, d0 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: mov r3, r11 ; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: mov r2, r10 ; CHECK-NEXT: mov r3, r9 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne.w r7, #-1 ; CHECK-NEXT: bl __aeabi_dcmpge ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: csel r6, r6, r0, ne ; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r2, r8 ; CHECK-NEXT: mov r3, r11 ; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne.w r6, #-1 ; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} ; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI3_0: ; CHECK-NEXT: .long 0 @ double 0 ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .LCPI3_1: ; CHECK-NEXT: .long 4294967295 @ double 1.844674407370955E+19 ; CHECK-NEXT: .long 1139802111 %i = call i64 @llvm.fptoui.sat.i64.f64(double %x) ret i64 %i } define <4 x i32> @fptosi_sat_v4i32_v4f32(<4 x float> %x) { ; CHECK-LABEL: fptosi_sat_v4i32_v4f32: ; CHECK: @ %bb.0: ; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr} ; CHECK-NEXT: mov r10, r3 ; CHECK-NEXT: mov r6, r2 ; CHECK-NEXT: mov r4, r1 ; CHECK-NEXT: mov r7, r0 ; CHECK-NEXT: bl __aeabi_f2iz ; CHECK-NEXT: ldr.w r8, .LCPI4_0 ; CHECK-NEXT: mov r5, r0 ; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: bl __aeabi_fcmpge ; CHECK-NEXT: ldr.w r9, .LCPI4_1 ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: it eq ; CHECK-NEXT: moveq.w r5, #-2147483648 ; CHECK-NEXT: mov r1, r9 ; CHECK-NEXT: bl __aeabi_fcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r7 ; CHECK-NEXT: mov r1, r7 ; CHECK-NEXT: it ne ; CHECK-NEXT: mvnne r5, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpun ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r5, #0 ; CHECK-NEXT: bl __aeabi_f2iz ; CHECK-NEXT: mov r7, r0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: bl __aeabi_fcmpge ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r1, r9 ; CHECK-NEXT: it eq ; CHECK-NEXT: moveq.w r7, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r4 ; CHECK-NEXT: mov r1, r4 ; CHECK-NEXT: it ne ; CHECK-NEXT: mvnne r7, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpun ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r7, #0 ; CHECK-NEXT: bl __aeabi_f2iz ; CHECK-NEXT: mov r4, r0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: bl __aeabi_fcmpge ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r1, r9 ; CHECK-NEXT: it eq ; CHECK-NEXT: moveq.w r4, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r6 ; CHECK-NEXT: mov r1, r6 ; CHECK-NEXT: it ne ; CHECK-NEXT: mvnne r4, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpun ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r4, #0 ; CHECK-NEXT: bl __aeabi_f2iz ; CHECK-NEXT: mov r6, r0 ; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r1, r8 ; CHECK-NEXT: bl __aeabi_fcmpge ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r1, r9 ; CHECK-NEXT: it eq ; CHECK-NEXT: moveq.w r6, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpgt ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: mov r0, r10 ; CHECK-NEXT: mov r1, r10 ; CHECK-NEXT: it ne ; CHECK-NEXT: mvnne r6, #-2147483648 ; CHECK-NEXT: bl __aeabi_fcmpun ; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: it ne ; CHECK-NEXT: movne r6, #0 ; CHECK-NEXT: mov r0, r5 ; CHECK-NEXT: mov r1, r7 ; CHECK-NEXT: mov r2, r4 ; CHECK-NEXT: mov r3, r6 ; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc} ; CHECK-NEXT: .p2align 2 ; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: .LCPI4_0: ; CHECK-NEXT: .long 0xcf000000 @ float -2.14748365E+9 ; CHECK-NEXT: .LCPI4_1: ; CHECK-NEXT: .long 0x4effffff @ float 2.14748352E+9 %i = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %x) ret <4 x i32> %i }