# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 # RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X86 # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,X64 --- | define void @test_copy() { ret void } define void @test_copy2() { ret void } define void @test_copy3() { ret void } define void @test_copy4() { ret void } define void @test_copy5() { ret void } define void @test_copy6() { ret void } ... --- name: test_copy alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: $eax ; CHECK-LABEL: name: test_copy ; CHECK: liveins: $eax ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $al ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]] ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]] ; CHECK-NEXT: RET 0, implicit $eax %0(s8) = COPY $al %1(s32) = G_ZEXT %0(s8) $eax = COPY %1(s32) RET 0, implicit $eax ... --- name: test_copy2 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: $eax ; CHECK-LABEL: name: test_copy2 ; CHECK: liveins: $eax ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr8 = COPY $al ; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]] ; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]] ; CHECK-NEXT: RET 0, implicit $eax %0(s8) = COPY $al %1(s32) = G_ZEXT %0(s8) $eax = COPY %1(s32) RET 0, implicit $eax ... --- name: test_copy3 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } - { id: 2, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: $eax ; X86-LABEL: name: test_copy3 ; X86: liveins: $eax ; X86-NEXT: {{ $}} ; X86-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $ax ; X86-NEXT: [[COPY1:%[0-9]+]]:gr16_abcd = COPY [[COPY]] ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]] ; X86-NEXT: $eax = COPY [[MOVZX32rr8_]] ; X86-NEXT: RET 0, implicit $eax ; ; X64-LABEL: name: test_copy3 ; X64: liveins: $eax ; X64-NEXT: {{ $}} ; X64-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $ax ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit ; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] ; X64-NEXT: $eax = COPY [[MOVZX32rr8_]] ; X64-NEXT: RET 0, implicit $eax %0(s16) = COPY $ax %1(s8) = G_TRUNC %0(s16) %2(s32) = G_ZEXT %1(s8) $eax = COPY %2(s32) RET 0, implicit $eax ... --- name: test_copy4 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } - { id: 2, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: $eax ; CHECK-LABEL: name: test_copy4 ; CHECK: liveins: $eax ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $eax ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit ; CHECK-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]] ; CHECK-NEXT: $eax = COPY [[MOVZX32rr16_]] ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $eax %1(s16) = G_TRUNC %0(s32) %2(s32) = G_ZEXT %1(s16) $eax = COPY %2(s32) RET 0, implicit $eax ... --- name: test_copy5 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } - { id: 2, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: $eax,$edx ; X86-LABEL: name: test_copy5 ; X86: liveins: $eax, $edx ; X86-NEXT: {{ $}} ; X86-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx ; X86-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]] ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]] ; X86-NEXT: $eax = COPY [[MOVZX32rr8_]] ; X86-NEXT: RET 0, implicit $eax ; ; X64-LABEL: name: test_copy5 ; X64: liveins: $eax, $edx ; X64-NEXT: {{ $}} ; X64-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit ; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]] ; X64-NEXT: $eax = COPY [[MOVZX32rr8_]] ; X64-NEXT: RET 0, implicit $eax %0(s32) = COPY $edx %1(s8) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s8) $eax = COPY %2(s32) RET 0, implicit $eax ... --- name: test_copy6 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: gpr, preferred-register: '' } - { id: 1, class: gpr, preferred-register: '' } - { id: 2, class: gpr, preferred-register: '' } body: | bb.1 (%ir-block.0): liveins: $eax,$edx ; CHECK-LABEL: name: test_copy6 ; CHECK: liveins: $eax, $edx ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edx ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit ; CHECK-NEXT: [[DEF:%[0-9]+]]:low32_addr_access_rbp = IMPLICIT_DEF ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:low32_addr_access_rbp = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_16bit ; CHECK-NEXT: $eax = COPY [[INSERT_SUBREG]] ; CHECK-NEXT: RET 0, implicit $eax %0(s32) = COPY $edx %1(s16) = G_TRUNC %0(s32) %2(s32) = G_ANYEXT %1(s16) $eax = COPY %2(s32) RET 0, implicit $eax ...