; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64    | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512

define <4 x double> @concat_sqrt_v4f64_v2f64(<2 x double> %a0, <2 x double> %a1) {
; SSE-LABEL: concat_sqrt_v4f64_v2f64:
; SSE:       # %bb.0:
; SSE-NEXT:    sqrtpd %xmm0, %xmm0
; SSE-NEXT:    sqrtpd %xmm1, %xmm1
; SSE-NEXT:    retq
;
; AVX-LABEL: concat_sqrt_v4f64_v2f64:
; AVX:       # %bb.0:
; AVX-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT:    vsqrtpd %ymm0, %ymm0
; AVX-NEXT:    retq
  %v0 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a0)
  %v1 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a1)
  %res  = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  ret <4 x double> %res
}

define <8 x float> @concat_sqrt_v8f32_v4f32(<4 x float> %a0, <4 x float> %a1) {
; SSE-LABEL: concat_sqrt_v8f32_v4f32:
; SSE:       # %bb.0:
; SSE-NEXT:    sqrtps %xmm0, %xmm0
; SSE-NEXT:    sqrtps %xmm1, %xmm1
; SSE-NEXT:    retq
;
; AVX-LABEL: concat_sqrt_v8f32_v4f32:
; AVX:       # %bb.0:
; AVX-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX-NEXT:    vsqrtps %ymm0, %ymm0
; AVX-NEXT:    retq
  %v0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a0)
  %v1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a1)
  %res  = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  ret <8 x float> %res
}

define <8 x double> @concat_sqrt_v8f64_v2f64(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3) {
; SSE-LABEL: concat_sqrt_v8f64_v2f64:
; SSE:       # %bb.0:
; SSE-NEXT:    sqrtpd %xmm0, %xmm0
; SSE-NEXT:    sqrtpd %xmm1, %xmm1
; SSE-NEXT:    sqrtpd %xmm2, %xmm2
; SSE-NEXT:    sqrtpd %xmm3, %xmm3
; SSE-NEXT:    retq
;
; AVX1OR2-LABEL: concat_sqrt_v8f64_v2f64:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX1OR2-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1OR2-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1OR2-NEXT:    vsqrtpd %ymm0, %ymm0
; AVX1OR2-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm1
; AVX1OR2-NEXT:    vsqrtpd %ymm1, %ymm1
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: concat_sqrt_v8f64_v2f64:
; AVX512:       # %bb.0:
; AVX512-NEXT:    # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX512-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512-NEXT:    vsqrtpd %zmm0, %zmm0
; AVX512-NEXT:    retq
  %v0 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a0)
  %v1 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a1)
  %v2 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a2)
  %v3 = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %a3)
  %r01 = shufflevector <2 x double> %v0, <2 x double> %v1, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %r23 = shufflevector <2 x double> %v2, <2 x double> %v3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %res  = shufflevector <4 x double> %r01, <4 x double> %r23, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  ret <8 x double> %res
}

define <16 x float> @concat_sqrt_v16f32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {
; SSE-LABEL: concat_sqrt_v16f32_v4f32:
; SSE:       # %bb.0:
; SSE-NEXT:    sqrtps %xmm0, %xmm0
; SSE-NEXT:    sqrtps %xmm1, %xmm1
; SSE-NEXT:    sqrtps %xmm2, %xmm2
; SSE-NEXT:    sqrtps %xmm3, %xmm3
; SSE-NEXT:    retq
;
; AVX1OR2-LABEL: concat_sqrt_v16f32_v4f32:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX1OR2-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1OR2-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1OR2-NEXT:    vsqrtps %ymm0, %ymm0
; AVX1OR2-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm1
; AVX1OR2-NEXT:    vsqrtps %ymm1, %ymm1
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: concat_sqrt_v16f32_v4f32:
; AVX512:       # %bb.0:
; AVX512-NEXT:    # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX512-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
; AVX512-NEXT:    vsqrtps %zmm0, %zmm0
; AVX512-NEXT:    retq
  %v0 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a0)
  %v1 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a1)
  %v2 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a2)
  %v3 = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a3)
  %r01 = shufflevector <4 x float> %v0, <4 x float> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %r23 = shufflevector <4 x float> %v2, <4 x float> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  %res  = shufflevector <8 x float> %r01, <8 x float> %r23, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <16 x float> %res
}

define <8 x double> @concat_sqrt_v8f64_v4f64(<4 x double> %a0, <4 x double> %a1) {
; SSE-LABEL: concat_sqrt_v8f64_v4f64:
; SSE:       # %bb.0:
; SSE-NEXT:    sqrtpd %xmm0, %xmm0
; SSE-NEXT:    sqrtpd %xmm1, %xmm1
; SSE-NEXT:    sqrtpd %xmm2, %xmm2
; SSE-NEXT:    sqrtpd %xmm3, %xmm3
; SSE-NEXT:    retq
;
; AVX1OR2-LABEL: concat_sqrt_v8f64_v4f64:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vsqrtpd %ymm0, %ymm0
; AVX1OR2-NEXT:    vsqrtpd %ymm1, %ymm1
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: concat_sqrt_v8f64_v4f64:
; AVX512:       # %bb.0:
; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512-NEXT:    vsqrtpd %zmm0, %zmm0
; AVX512-NEXT:    retq
  %v0 = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a0)
  %v1 = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a1)
  %res  = shufflevector <4 x double> %v0, <4 x double> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  ret <8 x double> %res
}

define <16 x float> @concat_sqrt_v16f32_v8f32(<8 x float> %a0, <8 x float> %a1) {
; SSE-LABEL: concat_sqrt_v16f32_v8f32:
; SSE:       # %bb.0:
; SSE-NEXT:    sqrtps %xmm0, %xmm0
; SSE-NEXT:    sqrtps %xmm1, %xmm1
; SSE-NEXT:    sqrtps %xmm2, %xmm2
; SSE-NEXT:    sqrtps %xmm3, %xmm3
; SSE-NEXT:    retq
;
; AVX1OR2-LABEL: concat_sqrt_v16f32_v8f32:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vsqrtps %ymm0, %ymm0
; AVX1OR2-NEXT:    vsqrtps %ymm1, %ymm1
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: concat_sqrt_v16f32_v8f32:
; AVX512:       # %bb.0:
; AVX512-NEXT:    # kill: def $ymm0 killed $ymm0 def $zmm0
; AVX512-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
; AVX512-NEXT:    vsqrtps %zmm0, %zmm0
; AVX512-NEXT:    retq
  %v0 = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %a0)
  %v1 = call <8 x float> @llvm.sqrt.v8f32(<8 x float> %a1)
  %res  = shufflevector <8 x float> %v0, <8 x float> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
  ret <16 x float> %res
}

; We are concatenating the sqrt operands, so the fadd can be cheaply concatenated as well.
define void @concat_sqrt_fadd_v8f32_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %y0, <4 x float> %y1, ptr %p0){
; SSE-LABEL: concat_sqrt_fadd_v8f32_v4f32:
; SSE:       # %bb.0:
; SSE-NEXT:    addps %xmm0, %xmm2
; SSE-NEXT:    addps %xmm1, %xmm3
; SSE-NEXT:    movaps %xmm3, 16(%rdi)
; SSE-NEXT:    movaps %xmm2, (%rdi)
; SSE-NEXT:    sqrtps %xmm0, %xmm0
; SSE-NEXT:    sqrtps %xmm1, %xmm1
; SSE-NEXT:    movaps %xmm1, 48(%rdi)
; SSE-NEXT:    movaps %xmm0, 32(%rdi)
; SSE-NEXT:    retq
;
; AVX1-LABEL: concat_sqrt_fadd_v8f32_v4f32:
; AVX1:       # %bb.0:
; AVX1-NEXT:    # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX1-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT:    vaddps %ymm2, %ymm0, %ymm1
; AVX1-NEXT:    vmovaps %ymm1, (%rdi)
; AVX1-NEXT:    vsqrtps %ymm0, %ymm0
; AVX1-NEXT:    vmovaps %ymm0, 32(%rdi)
; AVX1-NEXT:    vzeroupper
; AVX1-NEXT:    retq
;
; AVX2-LABEL: concat_sqrt_fadd_v8f32_v4f32:
; AVX2:       # %bb.0:
; AVX2-NEXT:    # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX2-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX2-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX2-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT:    vaddps %ymm2, %ymm0, %ymm1
; AVX2-NEXT:    vsqrtps %ymm0, %ymm0
; AVX2-NEXT:    vmovaps %ymm1, (%rdi)
; AVX2-NEXT:    vmovaps %ymm0, 32(%rdi)
; AVX2-NEXT:    vzeroupper
; AVX2-NEXT:    retq
;
; AVX512-LABEL: concat_sqrt_fadd_v8f32_v4f32:
; AVX512:       # %bb.0:
; AVX512-NEXT:    # kill: def $xmm2 killed $xmm2 def $ymm2
; AVX512-NEXT:    # kill: def $xmm0 killed $xmm0 def $ymm0
; AVX512-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
; AVX512-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT:    vaddps %ymm2, %ymm0, %ymm1
; AVX512-NEXT:    vmovaps %ymm1, (%rdi)
; AVX512-NEXT:    vsqrtps %ymm0, %ymm0
; AVX512-NEXT:    vmovaps %ymm0, 32(%rdi)
; AVX512-NEXT:    vzeroupper
; AVX512-NEXT:    retq
  %add0 = fadd <4 x float> %x0, %y0
  %add1 = fadd <4 x float> %x1, %y1
  %add = shufflevector <4 x float> %add0, <4 x float> %add1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  store <8 x float> %add, ptr %p0, align 32

  %p1 = getelementptr inbounds nuw i8, ptr %p0, i64 32
  %sqrt0 = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x0)
  %sqrt1 = tail call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x1)
  %sqrt = shufflevector <4 x float> %sqrt0, <4 x float> %sqrt1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
  store <8 x float> %sqrt, ptr %p1, align 32
  ret void
}