; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=X86
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=SSE
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX

define float @PR178410(ptr %p0) nounwind {
; X86-LABEL: PR178410:
; X86:       # %bb.0:
; X86-NEXT:    pushl %ebp
; X86-NEXT:    movl %esp, %ebp
; X86-NEXT:    andl $-8, %esp
; X86-NEXT:    subl $8, %esp
; X86-NEXT:    movl 8(%ebp), %eax
; X86-NEXT:    movl (%eax), %ecx
; X86-NEXT:    movl 4(%eax), %eax
; X86-NEXT:    movl %eax, {{[0-9]+}}(%esp)
; X86-NEXT:    movl %ecx, (%esp)
; X86-NEXT:    fildll (%esp)
; X86-NEXT:    movl %ebp, %esp
; X86-NEXT:    popl %ebp
; X86-NEXT:    retl
;
; SSE-LABEL: PR178410:
; SSE:       # %bb.0:
; SSE-NEXT:    cvtsi2ssq (%rdi), %xmm0
; SSE-NEXT:    retq
;
; AVX-LABEL: PR178410:
; AVX:       # %bb.0:
; AVX-NEXT:    vcvtsi2ssq (%rdi), %xmm15, %xmm0
; AVX-NEXT:    retq
  %load = load <13 x i64>, ptr %p0, align 8
  %elt = extractelement <13 x i64> %load, i64 0
  %cvt = sitofp i64 %elt to float
  ret float %cvt
}