; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64    | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s

define i128 @hot_end_mask(ptr %token, i32 %end) {
; CHECK-LABEL: hot_end_mask:
; CHECK:       # %bb.0:
; CHECK-NEXT:    # kill: def $esi killed $esi def $rsi
; CHECK-NEXT:    movq 8(%rdi), %rdx
; CHECK-NEXT:    movl (%rdi), %eax
; CHECK-NEXT:    shlq $32, %rsi
; CHECK-NEXT:    orq %rsi, %rax
; CHECK-NEXT:    movq %rax, (%rdi)
; CHECK-NEXT:    retq
  %load = load i128, ptr %token, align 16
  %mask = and i128 %load, -18446744069414584321
  %zext = zext i32 %end to i128
  %shl = shl nuw nsw i128 %zext, 32
  %blend = or disjoint i128 %mask, %shl
  store i128 %blend, ptr %token, align 16
  ret i128 %blend
}

define i128 @hot_start_mask(ptr %token, i32 %start) {
; CHECK-LABEL: hot_start_mask:
; CHECK:       # %bb.0:
; CHECK-NEXT:    movq 8(%rdi), %rdx
; CHECK-NEXT:    movl 4(%rdi), %ecx
; CHECK-NEXT:    shlq $32, %rcx
; CHECK-NEXT:    movl %esi, %eax
; CHECK-NEXT:    orq %rcx, %rax
; CHECK-NEXT:    movq %rax, (%rdi)
; CHECK-NEXT:    retq
  %load = load i128, ptr %token, align 16
  %mask = and i128 %load, -4294967296
  %zext = zext i32 %start to i128
  %blend = or disjoint i128 %mask, %zext
  store i128 %blend, ptr %token, align 16
  ret i128 %blend
}