; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2    | FileCheck %s --check-prefixes=SSE,SSE2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1  | FileCheck %s --check-prefixes=SSE,SSE4
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx     | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2    | FileCheck %s --check-prefixes=AVX,AVX1OR2,AVX2
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512

define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
; SSE2-LABEL: fold_urem_vec_1:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [0,65535,65535,0,65535,65535,65535,65535]
; SSE2-NEXT:    pandn %xmm0, %xmm1
; SSE2-NEXT:    movq {{.*#+}} xmm2 = [0,0,0,64,0,128,0,0,0,0,0,0,0,0,0,0]
; SSE2-NEXT:    pmulhuw %xmm0, %xmm2
; SSE2-NEXT:    por %xmm1, %xmm2
; SSE2-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [44151,16913,2675,1373,u,u,u,u]
; SSE2-NEXT:    movdqa %xmm0, %xmm1
; SSE2-NEXT:    psubw %xmm2, %xmm1
; SSE2-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [0,0,0,32768,u,u,u,u]
; SSE2-NEXT:    paddw %xmm2, %xmm1
; SSE2-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [1024,8192,32768,128,u,u,u,u]
; SSE2-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [95,124,98,1003,u,u,u,u]
; SSE2-NEXT:    psubw %xmm1, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: fold_urem_vec_1:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movq {{.*#+}} xmm1 = [0,16384,32768,0,0,0,0,0]
; SSE4-NEXT:    pmulhuw %xmm0, %xmm1
; SSE4-NEXT:    pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2],xmm0[3],xmm1[4,5,6,7]
; SSE4-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [44151,16913,2675,1373,u,u,u,u]
; SSE4-NEXT:    movdqa %xmm0, %xmm2
; SSE4-NEXT:    psubw %xmm1, %xmm2
; SSE4-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [0,0,0,32768,u,u,u,u]
; SSE4-NEXT:    paddw %xmm1, %xmm2
; SSE4-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [1024,8192,32768,128,u,u,u,u]
; SSE4-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [95,124,98,1003,u,u,u,u]
; SSE4-NEXT:    psubw %xmm2, %xmm0
; SSE4-NEXT:    retq
;
; AVX1OR2-LABEL: fold_urem_vec_1:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [u,16384,32768,u,u,u,u,u]
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2],xmm0[3],xmm1[4,5,6,7]
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [44151,16913,2675,1373,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm2
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [0,0,0,32768,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1024,8192,32768,128,u,u,u,u]
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,124,98,1003,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: fold_urem_vec_1:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
; AVX512-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [44151,16913,2675,1373,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm2
; AVX512-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [0,0,0,32768,u,u,u,u]
; AVX512-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX512-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,124,98,1003,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:    retq
  %1 = urem <4 x i16> %x, <i16 95, i16 124, i16 98, i16 1003>
  ret <4 x i16> %1
}

define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; SSE-LABEL: fold_urem_vec_2:
; SSE:       # %bb.0:
; SSE-NEXT:    movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,u,u,u,u]
; SSE-NEXT:    pmulhuw %xmm0, %xmm1
; SSE-NEXT:    psrlw $6, %xmm1
; SSE-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 # [95,95,95,95,u,u,u,u]
; SSE-NEXT:    psubw %xmm1, %xmm0
; SSE-NEXT:    retq
;
; AVX-LABEL: fold_urem_vec_2:
; AVX:       # %bb.0:
; AVX-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [44151,44151,44151,44151,u,u,u,u]
; AVX-NEXT:    vpsrlw $6, %xmm1, %xmm1
; AVX-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [95,95,95,95,u,u,u,u]
; AVX-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX-NEXT:    retq
  %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
  ret <4 x i16> %1
}


; Don't fold if we can combine urem with udiv.
define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; SSE2-LABEL: combine_urem_udiv:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,u,u,u,u]
; SSE2-NEXT:    pmulhuw %xmm0, %xmm1
; SSE2-NEXT:    psrlw $6, %xmm1
; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [95,95,95,95,u,u,u,u]
; SSE2-NEXT:    pmullw %xmm1, %xmm2
; SSE2-NEXT:    psubw %xmm2, %xmm0
; SSE2-NEXT:    paddw %xmm1, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: combine_urem_udiv:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movdqa {{.*#+}} xmm1 = [44151,44151,44151,44151,u,u,u,u]
; SSE4-NEXT:    pmulhuw %xmm0, %xmm1
; SSE4-NEXT:    psrlw $6, %xmm1
; SSE4-NEXT:    pmovsxbw {{.*#+}} xmm2 = [95,95,95,95,95,95,95,95]
; SSE4-NEXT:    pmullw %xmm1, %xmm2
; SSE4-NEXT:    psubw %xmm2, %xmm0
; SSE4-NEXT:    paddw %xmm1, %xmm0
; SSE4-NEXT:    retq
;
; AVX-LABEL: combine_urem_udiv:
; AVX:       # %bb.0:
; AVX-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [44151,44151,44151,44151,u,u,u,u]
; AVX-NEXT:    vpsrlw $6, %xmm1, %xmm1
; AVX-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm2 # [95,95,95,95,u,u,u,u]
; AVX-NEXT:    vpsubw %xmm2, %xmm0, %xmm0
; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
; AVX-NEXT:    retq
  %1 = urem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
  %2 = udiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>
  %3 = add <4 x i16> %1, %2
  ret <4 x i16> %3
}

; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; SSE2-LABEL: dont_fold_urem_power_of_two:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movq {{.*#+}} xmm1 = [1024,2048,8192,44151,0,0,0,0]
; SSE2-NEXT:    pmulhuw %xmm0, %xmm1
; SSE2-NEXT:    movdqa {{.*#+}} xmm2 = [65535,65535,65535,0,65535,65535,65535,65535]
; SSE2-NEXT:    movdqa %xmm1, %xmm3
; SSE2-NEXT:    pand %xmm2, %xmm3
; SSE2-NEXT:    psrlw $6, %xmm1
; SSE2-NEXT:    pandn %xmm1, %xmm2
; SSE2-NEXT:    por %xmm3, %xmm2
; SSE2-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [64,32,8,95,u,u,u,u]
; SSE2-NEXT:    psubw %xmm2, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: dont_fold_urem_power_of_two:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movq {{.*#+}} xmm1 = [1024,2048,8192,44151,0,0,0,0]
; SSE4-NEXT:    pmulhuw %xmm0, %xmm1
; SSE4-NEXT:    movdqa %xmm1, %xmm2
; SSE4-NEXT:    psrlw $6, %xmm2
; SSE4-NEXT:    pblendw {{.*#+}} xmm2 = xmm1[0,1,2],xmm2[3],xmm1[4,5,6,7]
; SSE4-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [64,32,8,95,u,u,u,u]
; SSE4-NEXT:    psubw %xmm2, %xmm0
; SSE4-NEXT:    retq
;
; AVX1OR2-LABEL: dont_fold_urem_power_of_two:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1024,2048,8192,44151,u,u,u,u]
; AVX1OR2-NEXT:    vpsrlw $6, %xmm1, %xmm2
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3],xmm1[4,5,6,7]
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: dont_fold_urem_power_of_two:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [1024,2048,8192,44151,u,u,u,u]
; AVX512-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [64,32,8,95,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:    retq
  %1 = urem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>
  ret <4 x i16> %1
}

; Don't fold if the divisor is one.
define <4 x i16> @dont_fold_urem_one(<4 x i16> %x) {
; SSE2-LABEL: dont_fold_urem_one:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
; SSE2-NEXT:    pandn %xmm0, %xmm1
; SSE2-NEXT:    movq {{.*#+}} xmm2 = [0,51307,25645,12375,0,0,0,0]
; SSE2-NEXT:    pmulhuw %xmm0, %xmm2
; SSE2-NEXT:    movdqa %xmm0, %xmm3
; SSE2-NEXT:    psubw %xmm2, %xmm3
; SSE2-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [u,0,32768,0,u,u,u,u]
; SSE2-NEXT:    paddw %xmm2, %xmm3
; SSE2-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [0,0,128,0,0,16,64,0,u,u,u,u,u,u,u,u]
; SSE2-NEXT:    por %xmm1, %xmm3
; SSE2-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm3 # [1,654,23,5423,u,u,u,u]
; SSE2-NEXT:    psubw %xmm3, %xmm0
; SSE2-NEXT:    retq
;
; SSE4-LABEL: dont_fold_urem_one:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movq {{.*#+}} xmm1 = [0,51307,25645,12375,0,0,0,0]
; SSE4-NEXT:    pmulhuw %xmm0, %xmm1
; SSE4-NEXT:    movdqa %xmm0, %xmm2
; SSE4-NEXT:    psubw %xmm1, %xmm2
; SSE4-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [u,0,32768,0,u,u,u,u]
; SSE4-NEXT:    paddw %xmm1, %xmm2
; SSE4-NEXT:    pmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [u,128,4096,64,u,u,u,u]
; SSE4-NEXT:    pblendw {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3,4,5,6,7]
; SSE4-NEXT:    pmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2 # [1,654,23,5423,u,u,u,u]
; SSE4-NEXT:    psubw %xmm2, %xmm0
; SSE4-NEXT:    retq
;
; AVX1OR2-LABEL: dont_fold_urem_one:
; AVX1OR2:       # %bb.0:
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [u,51307,25645,12375,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm2
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,0,32768,0,u,u,u,u]
; AVX1OR2-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX1OR2-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [u,128,4096,64,u,u,u,u]
; AVX1OR2-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; AVX1OR2-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
; AVX1OR2-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX1OR2-NEXT:    retq
;
; AVX512-LABEL: dont_fold_urem_one:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [u,51307,25645,12375,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm2
; AVX512-NEXT:    vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2 # [u,0,32768,0,u,u,u,u]
; AVX512-NEXT:    vpaddw %xmm1, %xmm2, %xmm1
; AVX512-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
; AVX512-NEXT:    vpblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3,4,5,6,7]
; AVX512-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 # [1,654,23,5423,u,u,u,u]
; AVX512-NEXT:    vpsubw %xmm1, %xmm0, %xmm0
; AVX512-NEXT:    retq
  %1 = urem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>
  ret <4 x i16> %1
}

; Don't fold if the divisor is 2^16.
define <4 x i16> @dont_fold_urem_i16_smax(<4 x i16> %x) {
; CHECK-LABEL: dont_fold_urem_i16_smax:
; CHECK:       # %bb.0:
; CHECK-NEXT:    retq
; SSE-LABEL: dont_fold_urem_i16_smax:
; SSE:       # %bb.0:
; SSE-NEXT:    retq
;
; AVX-LABEL: dont_fold_urem_i16_smax:
; AVX:       # %bb.0:
; AVX-NEXT:    retq
  %1 = urem <4 x i16> %x, <i16 1, i16 65536, i16 23, i16 5423>
  ret <4 x i16> %1
}

; Don't fold i64 urem.
define <4 x i64> @dont_fold_urem_i64(<4 x i64> %x) {
; SSE2-LABEL: dont_fold_urem_i64:
; SSE2:       # %bb.0:
; SSE2-NEXT:    movdqa %xmm1, %xmm2
; SSE2-NEXT:    movq %xmm1, %rcx
; SSE2-NEXT:    movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
; SSE2-NEXT:    movq %rcx, %rax
; SSE2-NEXT:    mulq %rdx
; SSE2-NEXT:    movq %rcx, %rax
; SSE2-NEXT:    subq %rdx, %rax
; SSE2-NEXT:    shrq %rax
; SSE2-NEXT:    addq %rdx, %rax
; SSE2-NEXT:    shrq $4, %rax
; SSE2-NEXT:    leaq (%rax,%rax,2), %rdx
; SSE2-NEXT:    shlq $3, %rdx
; SSE2-NEXT:    subq %rdx, %rax
; SSE2-NEXT:    addq %rcx, %rax
; SSE2-NEXT:    movq %rax, %xmm1
; SSE2-NEXT:    pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
; SSE2-NEXT:    movq %xmm2, %rcx
; SSE2-NEXT:    movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D
; SSE2-NEXT:    movq %rcx, %rax
; SSE2-NEXT:    mulq %rdx
; SSE2-NEXT:    shrq $12, %rdx
; SSE2-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; SSE2-NEXT:    subq %rax, %rcx
; SSE2-NEXT:    movq %rcx, %xmm2
; SSE2-NEXT:    punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; SSE2-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
; SSE2-NEXT:    movq %xmm0, %rcx
; SSE2-NEXT:    movq %rcx, %rax
; SSE2-NEXT:    shrq %rax
; SSE2-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; SSE2-NEXT:    mulq %rdx
; SSE2-NEXT:    shrq $7, %rdx
; SSE2-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; SSE2-NEXT:    subq %rax, %rcx
; SSE2-NEXT:    movq %rcx, %xmm0
; SSE2-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE2-NEXT:    retq
;
; SSE4-LABEL: dont_fold_urem_i64:
; SSE4:       # %bb.0:
; SSE4-NEXT:    movq %xmm1, %rcx
; SSE4-NEXT:    movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
; SSE4-NEXT:    movq %rcx, %rax
; SSE4-NEXT:    mulq %rdx
; SSE4-NEXT:    movq %rcx, %rax
; SSE4-NEXT:    subq %rdx, %rax
; SSE4-NEXT:    shrq %rax
; SSE4-NEXT:    addq %rdx, %rax
; SSE4-NEXT:    shrq $4, %rax
; SSE4-NEXT:    leaq (%rax,%rax,2), %rdx
; SSE4-NEXT:    shlq $3, %rdx
; SSE4-NEXT:    subq %rdx, %rax
; SSE4-NEXT:    addq %rcx, %rax
; SSE4-NEXT:    movq %rax, %xmm2
; SSE4-NEXT:    pextrq $1, %xmm1, %rcx
; SSE4-NEXT:    movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D
; SSE4-NEXT:    movq %rcx, %rax
; SSE4-NEXT:    mulq %rdx
; SSE4-NEXT:    shrq $12, %rdx
; SSE4-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; SSE4-NEXT:    subq %rax, %rcx
; SSE4-NEXT:    movq %rcx, %xmm1
; SSE4-NEXT:    punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm1[0]
; SSE4-NEXT:    pextrq $1, %xmm0, %rcx
; SSE4-NEXT:    movq %rcx, %rax
; SSE4-NEXT:    shrq %rax
; SSE4-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; SSE4-NEXT:    mulq %rdx
; SSE4-NEXT:    shrq $7, %rdx
; SSE4-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; SSE4-NEXT:    subq %rax, %rcx
; SSE4-NEXT:    movq %rcx, %xmm0
; SSE4-NEXT:    pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; SSE4-NEXT:    movdqa %xmm2, %xmm1
; SSE4-NEXT:    retq
;
; AVX1-LABEL: dont_fold_urem_i64:
; AVX1:       # %bb.0:
; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
; AVX1-NEXT:    vmovq %xmm1, %rcx
; AVX1-NEXT:    movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
; AVX1-NEXT:    movq %rcx, %rax
; AVX1-NEXT:    mulq %rdx
; AVX1-NEXT:    movq %rcx, %rax
; AVX1-NEXT:    subq %rdx, %rax
; AVX1-NEXT:    shrq %rax
; AVX1-NEXT:    addq %rdx, %rax
; AVX1-NEXT:    shrq $4, %rax
; AVX1-NEXT:    leaq (%rax,%rax,2), %rdx
; AVX1-NEXT:    shlq $3, %rdx
; AVX1-NEXT:    subq %rdx, %rax
; AVX1-NEXT:    addq %rcx, %rax
; AVX1-NEXT:    vmovq %rax, %xmm2
; AVX1-NEXT:    vpextrq $1, %xmm1, %rcx
; AVX1-NEXT:    movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D
; AVX1-NEXT:    movq %rcx, %rax
; AVX1-NEXT:    mulq %rdx
; AVX1-NEXT:    shrq $12, %rdx
; AVX1-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; AVX1-NEXT:    subq %rax, %rcx
; AVX1-NEXT:    vmovq %rcx, %xmm1
; AVX1-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX1-NEXT:    vpextrq $1, %xmm0, %rcx
; AVX1-NEXT:    movq %rcx, %rax
; AVX1-NEXT:    shrq %rax
; AVX1-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX1-NEXT:    mulq %rdx
; AVX1-NEXT:    shrq $7, %rdx
; AVX1-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; AVX1-NEXT:    subq %rax, %rcx
; AVX1-NEXT:    vmovq %rcx, %xmm0
; AVX1-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX1-NEXT:    retq
;
; AVX2-LABEL: dont_fold_urem_i64:
; AVX2:       # %bb.0:
; AVX2-NEXT:    vextracti128 $1, %ymm0, %xmm1
; AVX2-NEXT:    vmovq %xmm1, %rcx
; AVX2-NEXT:    movabsq $7218291159277650633, %rdx # imm = 0x642C8590B21642C9
; AVX2-NEXT:    movq %rcx, %rax
; AVX2-NEXT:    mulq %rdx
; AVX2-NEXT:    movq %rcx, %rax
; AVX2-NEXT:    subq %rdx, %rax
; AVX2-NEXT:    shrq %rax
; AVX2-NEXT:    addq %rdx, %rax
; AVX2-NEXT:    shrq $4, %rax
; AVX2-NEXT:    leaq (%rax,%rax,2), %rdx
; AVX2-NEXT:    shlq $3, %rdx
; AVX2-NEXT:    subq %rdx, %rax
; AVX2-NEXT:    addq %rcx, %rax
; AVX2-NEXT:    vmovq %rax, %xmm2
; AVX2-NEXT:    vpextrq $1, %xmm1, %rcx
; AVX2-NEXT:    movabsq $-4513890722074972339, %rdx # imm = 0xC15B704DCBCA2F4D
; AVX2-NEXT:    movq %rcx, %rax
; AVX2-NEXT:    mulq %rdx
; AVX2-NEXT:    shrq $12, %rdx
; AVX2-NEXT:    imulq $5423, %rdx, %rax # imm = 0x152F
; AVX2-NEXT:    subq %rax, %rcx
; AVX2-NEXT:    vmovq %rcx, %xmm1
; AVX2-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
; AVX2-NEXT:    vpextrq $1, %xmm0, %rcx
; AVX2-NEXT:    movq %rcx, %rax
; AVX2-NEXT:    shrq %rax
; AVX2-NEXT:    movabsq $7220743857598845893, %rdx # imm = 0x64353C48064353C5
; AVX2-NEXT:    mulq %rdx
; AVX2-NEXT:    shrq $7, %rdx
; AVX2-NEXT:    imulq $654, %rdx, %rax # imm = 0x28E
; AVX2-NEXT:    subq %rax, %rcx
; AVX2-NEXT:    vmovq %rcx, %xmm0
; AVX2-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; AVX2-NEXT:    vinserti128 $1, %xmm1, %ymm0, %ymm0
; AVX2-NEXT:    retq
;
; AVX512-LABEL: dont_fold_urem_i64:
; AVX512:       # %bb.0:
; AVX512-NEXT:    vextracti128 $1, %ymm0, %xmm1
; AVX512-NEXT:    vmovq %xmm1, %rdx
; AVX512-NEXT:    movabsq $7218291159277650633, %rax # imm = 0x642C8590B21642C9
; AVX512-NEXT:    mulxq %rax, %rax, %rax
; AVX512-NEXT:    movq %rdx, %rcx
; AVX512-NEXT:    subq %rax, %rcx
; AVX512-NEXT:    shrq %rcx
; AVX512-NEXT:    addq %rax, %rcx
; AVX512-NEXT:    shrq $4, %rcx
; AVX512-NEXT:    leaq (%rcx,%rcx,2), %rax
; AVX512-NEXT:    shlq $3, %rax
; AVX512-NEXT:    subq %rax, %rcx
; AVX512-NEXT:    addq %rdx, %rcx
; AVX512-NEXT:    vpextrq $1, %xmm1, %rdx
; AVX512-NEXT:    movabsq $-4513890722074972339, %rax # imm = 0xC15B704DCBCA2F4D
; AVX512-NEXT:    mulxq %rax, %rax, %rax
; AVX512-NEXT:    vmovq %rcx, %xmm1
; AVX512-NEXT:    shrq $12, %rax
; AVX512-NEXT:    imulq $5423, %rax, %rax # imm = 0x152F
; AVX512-NEXT:    subq %rax, %rdx
; AVX512-NEXT:    vmovq %rdx, %xmm2
; AVX512-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; AVX512-NEXT:    vpextrq $1, %xmm0, %rax
; AVX512-NEXT:    movq %rax, %rdx
; AVX512-NEXT:    shrq %rdx
; AVX512-NEXT:    movabsq $7220743857598845893, %rcx # imm = 0x64353C48064353C5
; AVX512-NEXT:    mulxq %rcx, %rcx, %rcx
; AVX512-NEXT:    shrq $7, %rcx
; AVX512-NEXT:    imulq $654, %rcx, %rcx # imm = 0x28E
; AVX512-NEXT:    subq %rcx, %rax
; AVX512-NEXT:    vmovq %rax, %xmm0
; AVX512-NEXT:    vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7]
; AVX512-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
; AVX512-NEXT:    retq
  %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
  ret <4 x i64> %1
}