; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter "(callq|ptrue)" --version 5
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-SSE
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-AVX
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-AVX2
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=AMDLIBM < %s | FileCheck %s --check-prefixes=CHECK,AMD,AMD-AVX512
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-SSE
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v2 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-AVX
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-AVX2
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 -vector-library=LIBMVEC < %s | FileCheck %s --check-prefixes=CHECK,GLIBC,GLIBC-AVX512

define void @test_sincos_v4f32(<4 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
; AMD-LABEL: test_sincos_v4f32:
; AMD:    callq amd_vrs4_sincosf@PLT
;
; GLIBC-LABEL: test_sincos_v4f32:
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
  %result = call { <4 x float>, <4 x float> } @llvm.sincos.v4f32(<4 x float> %x)
  %result.0 = extractvalue { <4 x float>, <4 x float> } %result, 0
  %result.1 = extractvalue { <4 x float>, <4 x float> } %result, 1
  store <4 x float> %result.0, ptr %out_sin, align 16
  store <4 x float> %result.1, ptr %out_cos, align 16
  ret void
}

define void @test_sincos_v8f32(<8 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
; AMD-SSE-LABEL: test_sincos_v8f32:
; AMD-SSE:    callq amd_vrs4_sincosf@PLT
; AMD-SSE:    callq amd_vrs4_sincosf@PLT
;
; AMD-AVX-LABEL: test_sincos_v8f32:
; AMD-AVX:    callq amd_vrs4_sincosf@PLT
; AMD-AVX:    callq amd_vrs4_sincosf@PLT
;
; AMD-AVX2-LABEL: test_sincos_v8f32:
; AMD-AVX2:    callq amd_vrs8_sincosf@PLT
;
; AMD-AVX512-LABEL: test_sincos_v8f32:
; AMD-AVX512:    callq amd_vrs8_sincosf@PLT
;
; GLIBC-LABEL: test_sincos_v8f32:
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
  %result = call { <8 x float>, <8 x float> } @llvm.sincos.v8f32(<8 x float> %x)
  %result.0 = extractvalue { <8 x float>, <8 x float> } %result, 0
  %result.1 = extractvalue { <8 x float>, <8 x float> } %result, 1
  store <8 x float> %result.0, ptr %out_sin, align 32
  store <8 x float> %result.1, ptr %out_cos, align 32
  ret void
}

define void @test_sincos_v16f32(<16 x float> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
; AMD-SSE-LABEL: test_sincos_v16f32:
; AMD-SSE:    callq amd_vrs4_sincosf@PLT
; AMD-SSE:    callq amd_vrs4_sincosf@PLT
; AMD-SSE:    callq amd_vrs4_sincosf@PLT
; AMD-SSE:    callq amd_vrs4_sincosf@PLT
;
; AMD-AVX-LABEL: test_sincos_v16f32:
; AMD-AVX:    callq amd_vrs4_sincosf@PLT
; AMD-AVX:    callq amd_vrs4_sincosf@PLT
; AMD-AVX:    callq amd_vrs4_sincosf@PLT
; AMD-AVX:    callq amd_vrs4_sincosf@PLT
;
; AMD-AVX2-LABEL: test_sincos_v16f32:
; AMD-AVX2:    callq amd_vrs8_sincosf@PLT
; AMD-AVX2:    callq amd_vrs8_sincosf@PLT
;
; AMD-AVX512-LABEL: test_sincos_v16f32:
; AMD-AVX512:    callq amd_vrs16_sincosf@PLT
;
; GLIBC-LABEL: test_sincos_v16f32:
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
; GLIBC:    callq sincosf@PLT
  %result = call { <16 x float>, <16 x float> } @llvm.sincos.v16f32(<16 x float> %x)
  %result.0 = extractvalue { <16 x float>, <16 x float> } %result, 0
  %result.1 = extractvalue { <16 x float>, <16 x float> } %result, 1
  store <16 x float> %result.0, ptr %out_sin, align 64
  store <16 x float> %result.1, ptr %out_cos, align 64
  ret void
}

define void @test_sincos_v2f64(<2 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
; AMD-LABEL: test_sincos_v2f64:
; AMD:    callq amd_vrd2_sincos@PLT
;
; GLIBC-LABEL: test_sincos_v2f64:
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
  %result = call { <2 x double>, <2 x double> } @llvm.sincos.v2f64(<2 x double> %x)
  %result.0 = extractvalue { <2 x double>, <2 x double> } %result, 0
  %result.1 = extractvalue { <2 x double>, <2 x double> } %result, 1
  store <2 x double> %result.0, ptr %out_sin, align 16
  store <2 x double> %result.1, ptr %out_cos, align 16
  ret void
}

define void @test_sincos_v4f64(<4 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
; AMD-SSE-LABEL: test_sincos_v4f64:
; AMD-SSE:    callq amd_vrd2_sincos@PLT
; AMD-SSE:    callq amd_vrd2_sincos@PLT
;
; AMD-AVX-LABEL: test_sincos_v4f64:
; AMD-AVX:    callq amd_vrd2_sincos@PLT
; AMD-AVX:    callq amd_vrd2_sincos@PLT
;
; AMD-AVX2-LABEL: test_sincos_v4f64:
; AMD-AVX2:    callq amd_vrd4_sincos@PLT
;
; AMD-AVX512-LABEL: test_sincos_v4f64:
; AMD-AVX512:    callq amd_vrd4_sincos@PLT
;
; GLIBC-LABEL: test_sincos_v4f64:
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
  %result = call { <4 x double>, <4 x double> } @llvm.sincos.v4f64(<4 x double> %x)
  %result.0 = extractvalue { <4 x double>, <4 x double> } %result, 0
  %result.1 = extractvalue { <4 x double>, <4 x double> } %result, 1
  store <4 x double> %result.0, ptr %out_sin, align 32
  store <4 x double> %result.1, ptr %out_cos, align 32
  ret void
}

define void @test_sincos_v8f64(<8 x double> %x, ptr noalias %out_sin, ptr noalias %out_cos) {
; AMD-SSE-LABEL: test_sincos_v8f64:
; AMD-SSE:    callq amd_vrd2_sincos@PLT
; AMD-SSE:    callq amd_vrd2_sincos@PLT
; AMD-SSE:    callq amd_vrd2_sincos@PLT
; AMD-SSE:    callq amd_vrd2_sincos@PLT
;
; AMD-AVX-LABEL: test_sincos_v8f64:
; AMD-AVX:    callq amd_vrd2_sincos@PLT
; AMD-AVX:    callq amd_vrd2_sincos@PLT
; AMD-AVX:    callq amd_vrd2_sincos@PLT
; AMD-AVX:    callq amd_vrd2_sincos@PLT
;
; AMD-AVX2-LABEL: test_sincos_v8f64:
; AMD-AVX2:    callq amd_vrd4_sincos@PLT
; AMD-AVX2:    callq amd_vrd4_sincos@PLT
;
; AMD-AVX512-LABEL: test_sincos_v8f64:
; AMD-AVX512:    callq amd_vrd8_sincos@PLT
;
; GLIBC-LABEL: test_sincos_v8f64:
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
; GLIBC:    callq sincos@PLT
  %result = call { <8 x double>, <8 x double> } @llvm.sincos.v8f64(<8 x double> %x)
  %result.0 = extractvalue { <8 x double>, <8 x double> } %result, 0
  %result.1 = extractvalue { <8 x double>, <8 x double> } %result, 1
  store <8 x double> %result.0, ptr %out_sin, align 64
  store <8 x double> %result.1, ptr %out_cos, align 64
  ret void
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}
; GLIBC-AVX: {{.*}}
; GLIBC-AVX2: {{.*}}
; GLIBC-AVX512: {{.*}}
; GLIBC-SSE: {{.*}}