; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -S -passes=msan -msan-check-access-address=0 2>&1 | FileCheck %s
; RUN: opt < %s -S -passes=msan -msan-check-access-address=0 -msan-track-origins=1 2>&1 | FileCheck %s --check-prefixes=ORIGIN

target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon-unknown-linux-musl"

define void @Store(ptr nocapture %p, i32 %x) nounwind sanitize_memory {
; CHECK-LABEL: define void @Store(
; CHECK-SAME: ptr captures(none) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i32 8), align 8
; CHECK-NEXT:    call void @llvm.donothing()
; CHECK-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[P]] to i32
; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP2]], 536870912
; CHECK-NEXT:    [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr
; CHECK-NEXT:    store i32 [[TMP1]], ptr [[TMP4]], align 4
; CHECK-NEXT:    store i32 [[X]], ptr [[P]], align 4
; CHECK-NEXT:    ret void
;
; ORIGIN-LABEL: define void @Store(
; ORIGIN-SAME: ptr captures(none) [[P:%.*]], i32 [[X:%.*]]) #[[ATTR0:[0-9]+]] {
; ORIGIN-NEXT:  [[ENTRY:.*:]]
; ORIGIN-NEXT:    [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i32 8), align 8
; ORIGIN-NEXT:    [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i32 8), align 4
; ORIGIN-NEXT:    call void @llvm.donothing()
; ORIGIN-NEXT:    [[TMP3:%.*]] = ptrtoint ptr [[P]] to i32
; ORIGIN-NEXT:    [[TMP4:%.*]] = xor i32 [[TMP3]], 536870912
; ORIGIN-NEXT:    [[TMP5:%.*]] = inttoptr i32 [[TMP4]] to ptr
; ORIGIN-NEXT:    [[TMP6:%.*]] = add i32 [[TMP4]], 1342177280
; ORIGIN-NEXT:    [[TMP7:%.*]] = inttoptr i32 [[TMP6]] to ptr
; ORIGIN-NEXT:    store i32 [[TMP1]], ptr [[TMP5]], align 4
; ORIGIN-NEXT:    [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0
; ORIGIN-NEXT:    br i1 [[_MSCMP]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1:![0-9]+]]
; ORIGIN:       [[BB8]]:
; ORIGIN-NEXT:    store i32 [[TMP2]], ptr [[TMP7]], align 4
; ORIGIN-NEXT:    br label %[[BB9]]
; ORIGIN:       [[BB9]]:
; ORIGIN-NEXT:    store i32 [[X]], ptr [[P]], align 4
; ORIGIN-NEXT:    ret void
;
entry:
  store i32 %x, ptr %p, align 4
  ret void
}

define i32 @Load(ptr nocapture %p) nounwind sanitize_memory {
; CHECK-LABEL: define i32 @Load(
; CHECK-SAME: ptr captures(none) [[P:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
; CHECK-NEXT:    call void @llvm.donothing()
; CHECK-NEXT:    [[TMP1:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[P]] to i32
; CHECK-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP2]], 536870912
; CHECK-NEXT:    [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr
; CHECK-NEXT:    [[_MSLD:%.*]] = load i32, ptr [[TMP4]], align 4
; CHECK-NEXT:    store i32 [[_MSLD]], ptr @__msan_retval_tls, align 8
; CHECK-NEXT:    ret i32 [[TMP1]]
;
; ORIGIN-LABEL: define i32 @Load(
; ORIGIN-SAME: ptr captures(none) [[P:%.*]]) #[[ATTR0]] {
; ORIGIN-NEXT:  [[ENTRY:.*:]]
; ORIGIN-NEXT:    [[TMP0:%.*]] = load i32, ptr @__msan_va_arg_overflow_size_tls, align 4
; ORIGIN-NEXT:    call void @llvm.donothing()
; ORIGIN-NEXT:    [[TMP1:%.*]] = load i32, ptr [[P]], align 4
; ORIGIN-NEXT:    [[TMP2:%.*]] = ptrtoint ptr [[P]] to i32
; ORIGIN-NEXT:    [[TMP3:%.*]] = xor i32 [[TMP2]], 536870912
; ORIGIN-NEXT:    [[TMP4:%.*]] = inttoptr i32 [[TMP3]] to ptr
; ORIGIN-NEXT:    [[TMP5:%.*]] = add i32 [[TMP3]], 1342177280
; ORIGIN-NEXT:    [[TMP6:%.*]] = inttoptr i32 [[TMP5]] to ptr
; ORIGIN-NEXT:    [[_MSLD:%.*]] = load i32, ptr [[TMP4]], align 4
; ORIGIN-NEXT:    [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
; ORIGIN-NEXT:    store i32 [[_MSLD]], ptr @__msan_retval_tls, align 8
; ORIGIN-NEXT:    store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 4
; ORIGIN-NEXT:    ret i32 [[TMP1]]
;
entry:
  %0 = load i32, ptr %p, align 4
  ret i32 %0
}
;.
; ORIGIN: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}
;.