; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --filter "call i32 @(test_single_bb_resolver|test_multi_bb_resolver|test_caller_feats_not_implied|test_non_fmv_caller|test_priority|test_alternative_names|test_unrelated_callers|test_known_bits|test_priority_override)" --version 4

; REQUIRES: aarch64-registered-target

; RUN: opt --passes=globalopt -o - -S < %s | FileCheck %s

target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64-unknown-linux-gnu"

$test_single_bb_resolver.resolver = comdat any
$test_multi_bb_resolver.resolver = comdat any
$test_caller_feats_not_implied.resolver = comdat any
$test_non_fmv_caller.resolver = comdat any
$test_priority.resolver = comdat any
$test_alternative_names.resolver = comdat any
$test_unrelated_callers.resolver = comdat any
$test_known_bits.resolver = comdat any
$test_priority_override.resolver = comdat any
$caller1.resolver = comdat any
$caller2.resolver = comdat any
$caller3.resolver = comdat any
$caller6.resolver = comdat any
$caller7.resolver = comdat any
$caller8.resolver = comdat any
$caller9.resolver = comdat any
$caller11.resolver = comdat any
$caller12.resolver = comdat any

@__aarch64_cpu_features = external local_unnamed_addr global { i64 }

@test_single_bb_resolver = weak_odr ifunc i32 (), ptr @test_single_bb_resolver.resolver
@test_multi_bb_resolver = weak_odr ifunc i32 (), ptr @test_multi_bb_resolver.resolver
@test_caller_feats_not_implied = weak_odr ifunc i32 (), ptr @test_caller_feats_not_implied.resolver
@test_non_fmv_caller = weak_odr ifunc i32 (), ptr @test_non_fmv_caller.resolver
@test_priority = weak_odr ifunc i32 (), ptr @test_priority.resolver
@test_alternative_names = weak_odr ifunc i32 (), ptr @test_alternative_names.resolver
@test_unrelated_callers = weak_odr ifunc i32 (), ptr @test_unrelated_callers.resolver
@test_known_bits = weak_odr ifunc i32 (), ptr @test_known_bits.resolver
@test_priority_override = weak_odr ifunc i32 (), ptr @test_priority_override.resolver
@caller1 = weak_odr ifunc i32 (), ptr @caller1.resolver
@caller2 = weak_odr ifunc i32 (), ptr @caller2.resolver
@caller3 = weak_odr ifunc i32 (), ptr @caller3.resolver
@caller6 = weak_odr ifunc i32 (), ptr @caller6.resolver
@caller7 = weak_odr ifunc i32 (), ptr @caller7.resolver
@caller8 = weak_odr ifunc i32 (), ptr @caller8.resolver
@caller9 = weak_odr ifunc i32 (), ptr @caller9.resolver
@caller11 = weak_odr ifunc i32 (), ptr @caller11.resolver
@caller12 = weak_odr ifunc i32 (), ptr @caller12.resolver

declare void @__init_cpu_features_resolver() local_unnamed_addr

declare i32 @test_single_bb_resolver.default() #0
declare i32 @test_single_bb_resolver._Msve() #1
declare i32 @test_single_bb_resolver._Msve2() #2

define weak_odr ptr @test_single_bb_resolver.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_single_bb_resolver.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 69793284352
  %2 = icmp eq i64 %1, 69793284352
  %3 = and i64 %0, 1073807616
  %4 = icmp eq i64 %3, 1073807616
  %test_single_bb_resolver._Msve.test_single_bb_resolver.default = select i1 %4, ptr @test_single_bb_resolver._Msve, ptr @test_single_bb_resolver.default
  %common.ret.op = select i1 %2, ptr @test_single_bb_resolver._Msve2, ptr %test_single_bb_resolver._Msve.test_single_bb_resolver.default
  ret ptr %common.ret.op
}

define i32 @caller1._Msve() #1 {
; CHECK-LABEL: define i32 @caller1._Msve(
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_single_bb_resolver._Msve()
;
entry:
  %call = tail call i32 @test_single_bb_resolver()
  ret i32 %call
}

define i32 @caller1._Msve2() #2 {
; CHECK-LABEL: define i32 @caller1._Msve2(
; CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_single_bb_resolver._Msve2()
;
entry:
  %call = tail call i32 @test_single_bb_resolver()
  ret i32 %call
}

define i32 @caller1.default() #0 {
; CHECK-LABEL: define i32 @caller1.default(
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_single_bb_resolver.default()
;
entry:
  %call = tail call i32 @test_single_bb_resolver()
  ret i32 %call
}

define weak_odr ptr @caller1.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller1.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 69793284352
  %2 = icmp eq i64 %1, 69793284352
  %3 = and i64 %0, 1073807616
  %4 = icmp eq i64 %3, 1073807616
  %caller1._Msve.caller1.default = select i1 %4, ptr @caller1._Msve, ptr @caller1.default
  %common.ret.op = select i1 %2, ptr @caller1._Msve2, ptr %caller1._Msve.caller1.default
  ret ptr %common.ret.op
}

declare i32 @test_multi_bb_resolver._Mmops() #3
declare i32 @test_multi_bb_resolver._Msve2() #2
declare i32 @test_multi_bb_resolver._Msve() #1
declare i32 @test_multi_bb_resolver.default() #0

define weak_odr ptr @test_multi_bb_resolver.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_multi_bb_resolver.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460752303423488
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %resolver_else, label %common.ret

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @test_multi_bb_resolver._Mmops, %resolver_entry ], [ @test_multi_bb_resolver._Msve2, %resolver_else ], [ %test_multi_bb_resolver._Msve.test_multi_bb_resolver.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %2 = and i64 %0, 69793284352
  %3 = icmp eq i64 %2, 69793284352
  br i1 %3, label %common.ret, label %resolver_else2

resolver_else2:                                   ; preds = %resolver_else
  %4 = and i64 %0, 1073807616
  %5 = icmp eq i64 %4, 1073807616
  %test_multi_bb_resolver._Msve.test_multi_bb_resolver.default = select i1 %5, ptr @test_multi_bb_resolver._Msve, ptr @test_multi_bb_resolver.default
  br label %common.ret
}

define i32 @caller2._MmopsMsve2() #4 {
; CHECK-LABEL: define i32 @caller2._MmopsMsve2(
; CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_multi_bb_resolver._Mmops()
;
entry:
  %call = tail call i32 @test_multi_bb_resolver()
  ret i32 %call
}

define i32 @caller2._Mmops() #3 {
; CHECK-LABEL: define i32 @caller2._Mmops(
; CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_multi_bb_resolver._Mmops()
;
entry:
  %call = tail call i32 @test_multi_bb_resolver()
  ret i32 %call
}

define i32 @caller2._Msve() #1 {
; CHECK-LABEL: define i32 @caller2._Msve(
; CHECK-SAME: ) #[[ATTR1]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_multi_bb_resolver()
;
entry:
  %call = tail call i32 @test_multi_bb_resolver()
  ret i32 %call
}

define i32 @caller2.default() #0 {
; CHECK-LABEL: define i32 @caller2.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_multi_bb_resolver.default()
;
entry:
  %call = tail call i32 @test_multi_bb_resolver()
  ret i32 %call
}

define weak_odr ptr @caller2.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller2.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460822096707840
  %2 = icmp eq i64 %1, 576460822096707840
  br i1 %2, label %common.ret, label %resolver_else

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @caller2._MmopsMsve2, %resolver_entry ], [ @caller2._Mmops, %resolver_else ], [ %caller2._Msve.caller2.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %3 = and i64 %0, 576460752303423488
  %.not = icmp eq i64 %3, 0
  br i1 %.not, label %resolver_else2, label %common.ret

resolver_else2:                                   ; preds = %resolver_else
  %4 = and i64 %0, 1073807616
  %5 = icmp eq i64 %4, 1073807616
  %caller2._Msve.caller2.default = select i1 %5, ptr @caller2._Msve, ptr @caller2.default
  br label %common.ret
}

declare i32 @test_caller_feats_not_implied._Mmops() #3
declare i32 @test_caller_feats_not_implied._Msme() #5
declare i32 @test_caller_feats_not_implied._Msve() #1
declare i32 @test_caller_feats_not_implied.default() #0

define weak_odr ptr @test_caller_feats_not_implied.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_caller_feats_not_implied.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460752303423488
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %resolver_else, label %common.ret

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @test_caller_feats_not_implied._Mmops, %resolver_entry ], [ @test_caller_feats_not_implied._Msme, %resolver_else ], [ %test_caller_feats_not_implied._Msve.test_caller_feats_not_implied.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %2 = and i64 %0, 4398180795136
  %3 = icmp eq i64 %2, 4398180795136
  br i1 %3, label %common.ret, label %resolver_else2

resolver_else2:                                   ; preds = %resolver_else
  %4 = and i64 %0, 1073807616
  %5 = icmp eq i64 %4, 1073807616
  %test_caller_feats_not_implied._Msve.test_caller_feats_not_implied.default = select i1 %5, ptr @test_caller_feats_not_implied._Msve, ptr @test_caller_feats_not_implied.default
  br label %common.ret
}

define i32 @caller3._Mmops() #3 {
; CHECK-LABEL: define i32 @caller3._Mmops(
; CHECK-SAME: ) #[[ATTR3]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_caller_feats_not_implied._Mmops()
;
entry:
  %call = tail call i32 @test_caller_feats_not_implied()
  ret i32 %call
}

define i32 @caller3._Msve() #1 {
; CHECK-LABEL: define i32 @caller3._Msve(
; CHECK-SAME: ) #[[ATTR1]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_caller_feats_not_implied()
;
entry:
  %call = tail call i32 @test_caller_feats_not_implied()
  ret i32 %call
}

define i32 @caller3.default() #0 {
; CHECK-LABEL: define i32 @caller3.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_caller_feats_not_implied()
;
entry:
  %call = tail call i32 @test_caller_feats_not_implied()
  ret i32 %call
}

define weak_odr ptr @caller3.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller3.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460752303423488
  %.not = icmp eq i64 %1, 0
  %2 = and i64 %0, 1073807616
  %3 = icmp eq i64 %2, 1073807616
  %caller3._Msve.caller3.default = select i1 %3, ptr @caller3._Msve, ptr @caller3.default
  %common.ret.op = select i1 %.not, ptr %caller3._Msve.caller3.default, ptr @caller3._Mmops
  ret ptr %common.ret.op
}

declare i32 @test_non_fmv_caller._Maes() #6
declare i32 @test_non_fmv_caller._Msm4() #7
declare i32 @test_non_fmv_caller.default() #0

define weak_odr ptr @test_non_fmv_caller.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_non_fmv_caller.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 33536
  %2 = icmp eq i64 %1, 33536
  %3 = and i64 %0, 800
  %4 = icmp eq i64 %3, 800
  %test_non_fmv_caller._Msm4.test_non_fmv_caller.default = select i1 %4, ptr @test_non_fmv_caller._Msm4, ptr @test_non_fmv_caller.default
  %common.ret.op = select i1 %2, ptr @test_non_fmv_caller._Maes, ptr %test_non_fmv_caller._Msm4.test_non_fmv_caller.default
  ret ptr %common.ret.op
}

define i32 @caller4() #8 {
; CHECK-LABEL: define i32 @caller4(
; CHECK-SAME: ) local_unnamed_addr #[[ATTR8:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_non_fmv_caller._Maes()
;
entry:
  %call = tail call i32 @test_non_fmv_caller()
  ret i32 %call
}

define i32 @caller5() #9 {
; CHECK-LABEL: define i32 @caller5(
; CHECK-SAME: ) local_unnamed_addr #[[ATTR9:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_non_fmv_caller()
;
entry:
  %call = tail call i32 @test_non_fmv_caller()
  ret i32 %call
}

declare i32 @test_priority._Msve2-sha3() #10
declare i32 @test_priority._McsscMssbs() #11
declare i32 @test_priority._MflagmMlseMrng() #12
declare i32 @test_priority.default() #0

define weak_odr ptr @test_priority.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_priority.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 562949953423360
  %2 = icmp eq i64 %1, 562949953423360
  br i1 %2, label %common.ret, label %resolver_else

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @test_priority._McsscMssbs, %resolver_entry ], [ @test_priority._Msve2-sha3, %resolver_else ], [ %test_priority._MflagmMlseMrng.test_priority.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %3 = and i64 %0, 1169304924928
  %4 = icmp eq i64 %3, 1169304924928
  br i1 %4, label %common.ret, label %resolver_else2

resolver_else2:                                   ; preds = %resolver_else
  %5 = and i64 %0, 131
  %6 = icmp eq i64 %5, 131
  %test_priority._MflagmMlseMrng.test_priority.default = select i1 %6, ptr @test_priority._MflagmMlseMrng, ptr @test_priority.default
  br label %common.ret
}

define i32 @caller6._McsscMflagmMlseMrngMssbsMsve2-sha3() #13 {
; CHECK-LABEL: define i32 @caller6._McsscMflagmMlseMrngMssbsMsve2-sha3(
; CHECK-SAME: ) #[[ATTR13:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_priority._McsscMssbs()
;
entry:
  %call = tail call i32 @test_priority()
  ret i32 %call
}

define i32 @caller6.default() #0 {
; CHECK-LABEL: define i32 @caller6.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_priority()
;
entry:
  %call = tail call i32 @test_priority()
  ret i32 %call
}

define weak_odr ptr @caller6.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller6.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 564119258348419
  %2 = icmp eq i64 %1, 564119258348419
  %caller6._McsscMflagmMlseMrngMssbsMsve2-sha3.caller6.default = select i1 %2, ptr @caller6._McsscMflagmMlseMrngMssbsMsve2-sha3, ptr @caller6.default
  ret ptr %caller6._McsscMflagmMlseMrngMssbsMsve2-sha3.caller6.default
}

declare i32 @test_alternative_names._Mdpb2Mfrintts() #14
declare i32 @test_alternative_names._Mflagm2Mfrintts() #15
declare i32 @test_alternative_names._Mrcpc2() #16
declare i32 @test_alternative_names.default() #0

define weak_odr ptr @test_alternative_names.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_alternative_names.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 17563904
  %2 = icmp eq i64 %1, 17563904
  br i1 %2, label %common.ret, label %resolver_else

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @test_alternative_names._Mdpb2Mfrintts, %resolver_entry ], [ @test_alternative_names._Mflagm2Mfrintts, %resolver_else ], [ %test_alternative_names._Mrcpc2.test_alternative_names.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %3 = and i64 %0, 16777478
  %4 = icmp eq i64 %3, 16777478
  br i1 %4, label %common.ret, label %resolver_else2

resolver_else2:                                   ; preds = %resolver_else
  %5 = and i64 %0, 12582912
  %6 = icmp eq i64 %5, 12582912
  %test_alternative_names._Mrcpc2.test_alternative_names.default = select i1 %6, ptr @test_alternative_names._Mrcpc2, ptr @test_alternative_names.default
  br label %common.ret
}

define i32 @caller7._Mdpb2Mfrintts() #14 {
; CHECK-LABEL: define i32 @caller7._Mdpb2Mfrintts(
; CHECK-SAME: ) #[[ATTR14:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_alternative_names._Mdpb2Mfrintts()
;
entry:
  %call = tail call i32 @test_alternative_names()
  ret i32 %call
}

define i32 @caller7._Mfrintts() #17 {
; CHECK-LABEL: define i32 @caller7._Mfrintts(
; CHECK-SAME: ) #[[ATTR17:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_alternative_names()
;
entry:
  %call = tail call i32 @test_alternative_names()
  ret i32 %call
}

define i32 @caller7._Mrcpc2() #16 {
; CHECK-LABEL: define i32 @caller7._Mrcpc2(
; CHECK-SAME: ) #[[ATTR16:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_alternative_names._Mrcpc2()
;
entry:
  %call = tail call i32 @test_alternative_names()
  ret i32 %call
}

define i32 @caller7.default() #0 {
; CHECK-LABEL: define i32 @caller7.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_alternative_names.default()
;
entry:
  %call = tail call i32 @test_alternative_names()
  ret i32 %call
}

define weak_odr ptr @caller7.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller7.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 17563904
  %2 = icmp eq i64 %1, 17563904
  br i1 %2, label %common.ret, label %resolver_else

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @caller7._Mdpb2Mfrintts, %resolver_entry ], [ @caller7._Mfrintts, %resolver_else ], [ %caller7._Mrcpc2.caller7.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %3 = and i64 %0, 16777472
  %4 = icmp eq i64 %3, 16777472
  br i1 %4, label %common.ret, label %resolver_else2

resolver_else2:                                   ; preds = %resolver_else
  %5 = and i64 %0, 12582912
  %6 = icmp eq i64 %5, 12582912
  %caller7._Mrcpc2.caller7.default = select i1 %6, ptr @caller7._Mrcpc2, ptr @caller7.default
  br label %common.ret
}

declare i32 @test_unrelated_callers._Mmops() #3
declare i32 @test_unrelated_callers._Msve2() #2
declare i32 @test_unrelated_callers._Msve() #1
declare i32 @test_unrelated_callers.default() #0

define weak_odr ptr @test_unrelated_callers.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_unrelated_callers.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460752303423488
  %.not = icmp eq i64 %1, 0
  br i1 %.not, label %resolver_else, label %common.ret

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @test_unrelated_callers._Mmops, %resolver_entry ], [ @test_unrelated_callers._Msve2, %resolver_else ], [ %test_unrelated_callers._Msve.test_unrelated_callers.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %2 = and i64 %0, 69793284352
  %3 = icmp eq i64 %2, 69793284352
  br i1 %3, label %common.ret, label %resolver_else2

resolver_else2:                                   ; preds = %resolver_else
  %4 = and i64 %0, 1073807616
  %5 = icmp eq i64 %4, 1073807616
  %test_unrelated_callers._Msve.test_unrelated_callers.default = select i1 %5, ptr @test_unrelated_callers._Msve, ptr @test_unrelated_callers.default
  br label %common.ret
}

define i32 @caller8._MmopsMsve2() #4 {
; CHECK-LABEL: define i32 @caller8._MmopsMsve2(
; CHECK-SAME: ) #[[ATTR4]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_unrelated_callers._Mmops()
;
entry:
  %call = tail call i32 @test_unrelated_callers()
  ret i32 %call
}

define dso_local i32 @caller8._Msve2() #2 {
; CHECK-LABEL: define dso_local i32 @caller8._Msve2(
; CHECK-SAME: ) #[[ATTR2]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_unrelated_callers._Msve2()
;
entry:
  %call = tail call i32 @test_unrelated_callers()
  ret i32 %call
}

define i32 @caller8.default() #0 {
; CHECK-LABEL: define i32 @caller8.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_unrelated_callers()
;
entry:
  %call = tail call i32 @test_unrelated_callers()
  ret i32 %call
}

define weak_odr ptr @caller8.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller8.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460822096707840
  %2 = icmp eq i64 %1, 576460822096707840
  %3 = and i64 %0, 69793284352
  %4 = icmp eq i64 %3, 69793284352
  %caller8._Msve2.caller8.default = select i1 %4, ptr @caller8._Msve2, ptr @caller8.default
  %common.ret.op = select i1 %2, ptr @caller8._MmopsMsve2, ptr %caller8._Msve2.caller8.default
  ret ptr %common.ret.op
}

define i32 @caller9._Mmops() #3 {
; CHECK-LABEL: define i32 @caller9._Mmops(
; CHECK-SAME: ) #[[ATTR3]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_unrelated_callers._Mmops()
;
entry:
  %call = tail call i32 @test_unrelated_callers()
  ret i32 %call
}

define i32 @caller9._Msve() #1 {
; CHECK-LABEL: define i32 @caller9._Msve(
; CHECK-SAME: ) #[[ATTR1]] {
entry:
  ret i32 1
}

define i32 @caller9.default() #0 {
; CHECK-LABEL: define i32 @caller9.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_unrelated_callers.default()
;
entry:
  %call = tail call i32 @test_unrelated_callers()
  ret i32 %call
}

define weak_odr ptr @caller9.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller9.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460752303423488
  %.not = icmp eq i64 %1, 0
  %2 = and i64 %0, 1073807616
  %3 = icmp eq i64 %2, 1073807616
  %caller9._Msve.caller9.default = select i1 %3, ptr @caller9._Msve, ptr @caller9.default
  %common.ret.op = select i1 %.not, ptr %caller9._Msve.caller9.default, ptr @caller9._Mmops
  ret ptr %common.ret.op
}

define i32 @caller10() #18 {
; CHECK-LABEL: define i32 @caller10(
; CHECK-SAME: ) local_unnamed_addr #[[ATTR18:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_unrelated_callers._Mmops()
;
entry:
  %call = tail call i32 @test_unrelated_callers()
  ret i32 %call
}

declare i32 @test_known_bits._Mmops() #3
declare i32 @test_known_bits._Maes() #6
declare i32 @test_known_bits.default() #0

define weak_odr ptr @test_known_bits.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_known_bits.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460752303423488
  %.not = icmp eq i64 %1, 0
  %2 = and i64 %0, 33536
  %3 = icmp eq i64 %2, 33536
  %test_known_bits._Maes.test_known_bits.default = select i1 %3, ptr @test_known_bits._Maes, ptr @test_known_bits.default
  %common.ret.op = select i1 %.not, ptr %test_known_bits._Maes.test_known_bits.default, ptr @test_known_bits._Mmops
  ret ptr %common.ret.op
}

define i32 @caller11._MmopsMsve2() #4 {
; CHECK-LABEL: define i32 @caller11._MmopsMsve2(
; CHECK-SAME: ) #[[ATTR4]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_known_bits._Mmops()
;
entry:
  %call = tail call i32 @test_known_bits()
  ret i32 %call
}

define i32 @caller11._Msme() #5 {
; CHECK-LABEL: define i32 @caller11._Msme(
; CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_known_bits()
;
entry:
  %call = tail call i32 @test_known_bits()
  ret i32 %call
}

define noundef i32 @caller11._MaesMsve2() #19 {
; CHECK-LABEL: define noundef i32 @caller11._MaesMsve2(
; CHECK-SAME: ) #[[ATTR19:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_known_bits._Maes()
;
entry:
  %call = tail call i32 @test_known_bits()
  ret i32 %call
}

define i32 @caller11.default() #0 {
; CHECK-LABEL: define i32 @caller11.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_known_bits()
;
entry:
  %call = tail call i32 @test_known_bits()
  ret i32 %call
}

define weak_odr ptr @caller11.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller11.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 576460822096707840
  %2 = icmp eq i64 %1, 576460822096707840
  br i1 %2, label %common.ret, label %resolver_else

common.ret:                                       ; preds = %resolver_else2, %resolver_else, %resolver_entry
  %common.ret.op = phi ptr [ @caller11._MmopsMsve2, %resolver_entry ], [ @caller11._Msme, %resolver_else ], [ %caller11._MaesMsve2.caller11.default, %resolver_else2 ]
  ret ptr %common.ret.op

resolver_else:                                    ; preds = %resolver_entry
  %3 = and i64 %0, 4398180795136
  %4 = icmp eq i64 %3, 4398180795136
  br i1 %4, label %common.ret, label %resolver_else2

resolver_else2:                                   ; preds = %resolver_else
  %5 = and i64 %0, 69793317632
  %6 = icmp eq i64 %5, 69793317632
  %caller11._MaesMsve2.caller11.default = select i1 %6, ptr @caller11._MaesMsve2, ptr @caller11.default
  br label %common.ret
}

declare i32 @test_priority_override._Maes() #20
declare i32 @test_priority_override._Msme() #21
declare i32 @test_priority_override.default() #0

define weak_odr ptr @test_priority_override.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @test_priority_override.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 33536
  %2 = icmp eq i64 %1, 33536
  %3 = and i64 %0, 4398180795136
  %4 = icmp eq i64 %3, 4398180795136
  %test_priority_override._Msme.test_priority_override.default = select i1 %4, ptr @test_priority_override._Msme, ptr @test_priority_override.default
  %common.ret.op = select i1 %2, ptr @test_priority_override._Maes, ptr %test_priority_override._Msme.test_priority_override.default
  ret ptr %common.ret.op
}

define i32 @caller12._Maes() #22 {
; CHECK-LABEL: define i32 @caller12._Maes(
; CHECK-SAME: ) #[[ATTR6:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_priority_override._Maes()
;
entry:
  %call = tail call i32 @test_priority_override()
  ret i32 %call
}

define i32 @caller12._Mbf16() #23 {
; CHECK-LABEL: define i32 @caller12._Mbf16(
; CHECK-SAME: ) #[[ATTR19:[0-9]+]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_priority_override()
;
entry:
  %call = tail call i32 @test_priority_override()
  ret i32 %call
}

define noundef i32 @caller12.default() #0 {
; CHECK-LABEL: define noundef i32 @caller12.default(
; CHECK-SAME: ) #[[ATTR0]] {
; CHECK:    [[CALL:%.*]] = tail call i32 @test_priority_override.default()
;
entry:
  %call = tail call i32 @test_priority_override()
  ret i32 %call
}

define weak_odr ptr @caller12.resolver() comdat {
; CHECK-LABEL: define weak_odr ptr @caller12.resolver() comdat {
resolver_entry:
  tail call void @__init_cpu_features_resolver()
  %0 = load i64, ptr @__aarch64_cpu_features, align 8
  %1 = and i64 %0, 33536
  %2 = icmp eq i64 %1, 33536
  %3 = and i64 %0, 134218496
  %4 = icmp eq i64 %3, 134218496
  %caller12._Mbf16.caller12.default = select i1 %4, ptr @caller12._Mbf16, ptr @caller12.default
  %common.ret.op = select i1 %2, ptr @caller12._Maes, ptr %caller12._Mbf16.caller12.default
  ret ptr %common.ret.op
}

attributes #0 = { "fmv-features" }
attributes #1 = { "fmv-features"="sve" }
attributes #2 = { "fmv-features"="sve2" }
attributes #3 = { "fmv-features"="mops" }
attributes #4 = { "fmv-features"="mops,sve2" }
attributes #5 = { "fmv-features"="sme" }
attributes #6 = { "fmv-features"="aes" }
attributes #7 = { "fmv-features"="sm4" }
attributes #8 = { "target-features"="+aes,+fp-armv8,+neon,+outline-atomics,+v8a" }
attributes #9 = { "target-features"="+fp-armv8,+neon,+outline-atomics,+v8a,+sm4" }
attributes #10 = { "fmv-features"="sve2-sha3" }
attributes #11 = { "fmv-features"="cssc,ssbs" }
attributes #12 = { "fmv-features"="flagm,lse,rng" }
attributes #13 = { "fmv-features"="cssc,flagm,lse,rng,ssbs,sve2-sha3" }
attributes #14 = { "fmv-features"="dpb2,frintts" }
attributes #15 = { "fmv-features"="flagm2,frintts" }
attributes #16 = { "fmv-features"="rcpc2" }
attributes #17 = { "fmv-features"="frintts" }
attributes #18 = { "target-features"="+fp-armv8,+mops,+neon,+outline-atomics,+sve,+v8a" }
attributes #19 = { "fmv-features"="aes,sve2" }
attributes #20 = { "fmv-features"="P1,P4,P5,aes" } ; priority=50
attributes #21 = { "fmv-features"="P1,P2,P3,P4,sme" } ; priority=30
attributes #22 = { "fmv-features"="P3,P6,P7,aes" } ; priority=200
attributes #23 = { "fmv-features"="P2,P5,P6,bf16" } ; priority=100