; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -loop-reduce -S | FileCheck %s
;
; Test LSR's ability to prune formulae that refer to nonexistent
; AddRecs in other loops.
;
; Unable to reduce this case further because it requires LSR to exceed
; ComplexityLimit.
;
; We really just want to ensure that LSR can process this loop without
; finding an unsatisfactory solution and bailing out. I've added
; dummyout, an obvious candidate for postinc replacement so we can
; verify that LSR removes it.

target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-darwin"

define i64 @test(i64 %count, ptr nocapture %srcrow, ptr nocapture %destrow) nounwind uwtable ssp {
; CHECK-LABEL: define i64 @test(
; CHECK-SAME: i64 [[COUNT:%.*]], ptr captures(none) [[SRCROW:%.*]], ptr captures(none) [[DESTROW:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*]]:
; CHECK-NEXT:    [[CMP34:%.*]] = icmp eq i64 [[COUNT]], 0
; CHECK-NEXT:    br i1 [[CMP34]], label %[[FOR_END29:.*]], label %[[FOR_BODY_PREHEADER:.*]]
; CHECK:       [[FOR_BODY_PREHEADER]]:
; CHECK-NEXT:    [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[SRCROW]], i64 4
; CHECK-NEXT:    br label %[[FOR_BODY:.*]]
; CHECK:       [[FOR_BODY]]:
; CHECK-NEXT:    [[LSR_IV:%.*]] = phi ptr [ [[SCEVGEP4]], %[[FOR_BODY_PREHEADER]] ], [ [[SCEVGEP5:%.*]], %[[FOR_BODY]] ]
; CHECK-NEXT:    [[DUMMYIV:%.*]] = phi i64 [ [[DUMMYCNT:%.*]], %[[FOR_BODY]] ], [ 0, %[[FOR_BODY_PREHEADER]] ]
; CHECK-NEXT:    [[INDVARS_IV39:%.*]] = phi i64 [ [[INDVARS_IV_NEXT40:%.*]], %[[FOR_BODY]] ], [ 0, %[[FOR_BODY_PREHEADER]] ]
; CHECK-NEXT:    [[DP_036:%.*]] = phi ptr [ [[SCEVGEP16:%.*]], %[[FOR_BODY]] ], [ [[DESTROW]], %[[FOR_BODY_PREHEADER]] ]
; CHECK-NEXT:    [[TMP0:%.*]] = load float, ptr [[LSR_IV]], align 4
; CHECK-NEXT:    [[SCEVGEP9:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 4
; CHECK-NEXT:    [[TMP1:%.*]] = load float, ptr [[SCEVGEP9]], align 4
; CHECK-NEXT:    [[SCEVGEP8:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 8
; CHECK-NEXT:    [[TMP2:%.*]] = load float, ptr [[SCEVGEP8]], align 4
; CHECK-NEXT:    [[SCEVGEP7:%.*]] = getelementptr i8, ptr [[LSR_IV]], i64 12
; CHECK-NEXT:    [[TMP3:%.*]] = load float, ptr [[SCEVGEP7]], align 4
; CHECK-NEXT:    [[TMP4:%.*]] = load i32, ptr [[DP_036]], align 4
; CHECK-NEXT:    [[CONV5:%.*]] = fptoui float [[TMP0]] to i32
; CHECK-NEXT:    [[OR:%.*]] = or i32 [[TMP4]], [[CONV5]]
; CHECK-NEXT:    [[SCEVGEP10:%.*]] = getelementptr i8, ptr [[DP_036]], i64 4
; CHECK-NEXT:    [[TMP5:%.*]] = load i32, ptr [[SCEVGEP10]], align 4
; CHECK-NEXT:    [[CONV7:%.*]] = fptoui float [[TMP1]] to i32
; CHECK-NEXT:    [[OR8:%.*]] = or i32 [[TMP5]], [[CONV7]]
; CHECK-NEXT:    [[SCEVGEP11:%.*]] = getelementptr i8, ptr [[DP_036]], i64 8
; CHECK-NEXT:    [[TMP6:%.*]] = load i32, ptr [[SCEVGEP11]], align 4
; CHECK-NEXT:    [[CONV10:%.*]] = fptoui float [[TMP2]] to i32
; CHECK-NEXT:    [[OR11:%.*]] = or i32 [[TMP6]], [[CONV10]]
; CHECK-NEXT:    [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[DP_036]], i64 12
; CHECK-NEXT:    [[TMP7:%.*]] = load i32, ptr [[SCEVGEP12]], align 4
; CHECK-NEXT:    [[CONV13:%.*]] = fptoui float [[TMP3]] to i32
; CHECK-NEXT:    [[OR14:%.*]] = or i32 [[TMP7]], [[CONV13]]
; CHECK-NEXT:    store i32 [[OR]], ptr [[DP_036]], align 4
; CHECK-NEXT:    [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[DP_036]], i64 4
; CHECK-NEXT:    store i32 [[OR8]], ptr [[SCEVGEP13]], align 4
; CHECK-NEXT:    [[SCEVGEP14:%.*]] = getelementptr i8, ptr [[DP_036]], i64 8
; CHECK-NEXT:    store i32 [[OR11]], ptr [[SCEVGEP14]], align 4
; CHECK-NEXT:    [[SCEVGEP15:%.*]] = getelementptr i8, ptr [[DP_036]], i64 12
; CHECK-NEXT:    store i32 [[OR14]], ptr [[SCEVGEP15]], align 4
; CHECK-NEXT:    [[ADD_PTR:%.*]] = getelementptr inbounds i32, ptr [[DP_036]], i64 4
; CHECK-NEXT:    [[INDVARS_IV_NEXT40]] = add i64 [[INDVARS_IV39]], 4
; CHECK-NEXT:    [[DUMMYCNT]] = add i64 [[DUMMYIV]], 1
; CHECK-NEXT:    [[SCEVGEP5]] = getelementptr i8, ptr [[LSR_IV]], i64 16
; CHECK-NEXT:    [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV_NEXT40]], [[COUNT]]
; CHECK-NEXT:    [[SCEVGEP16]] = getelementptr i8, ptr [[DP_036]], i64 16
; CHECK-NEXT:    br i1 [[CMP]], label %[[FOR_BODY]], label %[[FOR_COND19_PREHEADER:.*]]
; CHECK:       [[FOR_COND19_PREHEADER]]:
; CHECK-NEXT:    [[DUMMYCNT_LCSSA:%.*]] = phi i64 [ [[DUMMYCNT]], %[[FOR_BODY]] ]
; CHECK-NEXT:    [[REM:%.*]] = and i64 [[COUNT]], 3
; CHECK-NEXT:    [[CMP2130:%.*]] = icmp eq i64 [[REM]], 0
; CHECK-NEXT:    br i1 [[CMP2130]], label %[[FOR_COND19_PREHEADER_FOR_END29_CRIT_EDGE:.*]], label %[[FOR_BODY23_LR_PH:.*]]
; CHECK:       [[FOR_COND19_PREHEADER_FOR_END29_CRIT_EDGE]]:
; CHECK-NEXT:    br label %[[FOR_END29]]
; CHECK:       [[FOR_BODY23_LR_PH]]:
; CHECK-NEXT:    [[TMP8:%.*]] = and i64 [[COUNT]], 3
; CHECK-NEXT:    br label %[[FOR_BODY23:.*]]
; CHECK:       [[FOR_BODY23]]:
; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[FOR_BODY23_LR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[FOR_BODY23]] ]
; CHECK-NEXT:    [[TMP9:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 2
; CHECK-NEXT:    [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[TMP9]]
; CHECK-NEXT:    [[TMP10:%.*]] = shl nuw nsw i64 [[INDVARS_IV]], 2
; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[TMP10]]
; CHECK-NEXT:    [[SCEVGEP6:%.*]] = getelementptr i8, ptr [[SCEVGEP5]], i64 [[TMP10]]
; CHECK-NEXT:    [[TMP11:%.*]] = load float, ptr [[SCEVGEP6]], align 4
; CHECK-NEXT:    [[TMP12:%.*]] = load i32, ptr [[SCEVGEP1]], align 4
; CHECK-NEXT:    [[CONV25:%.*]] = fptoui float [[TMP11]] to i32
; CHECK-NEXT:    [[OR26:%.*]] = or i32 [[TMP12]], [[CONV25]]
; CHECK-NEXT:    store i32 [[OR26]], ptr [[SCEVGEP]], align 4
; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp eq i64 [[TMP8]], [[INDVARS_IV_NEXT]]
; CHECK-NEXT:    br i1 [[EXITCOND]], label %[[FOR_END29_LOOPEXIT:.*]], label %[[FOR_BODY23]]
; CHECK:       [[FOR_END29_LOOPEXIT]]:
; CHECK-NEXT:    br label %[[FOR_END29]]
; CHECK:       [[FOR_END29]]:
; CHECK-NEXT:    [[RESULT:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[DUMMYCNT_LCSSA]], %[[FOR_COND19_PREHEADER_FOR_END29_CRIT_EDGE]] ], [ [[DUMMYCNT_LCSSA]], %[[FOR_END29_LOOPEXIT]] ]
; CHECK-NEXT:    ret i64 [[RESULT]]
;
entry:
  %cmp34 = icmp eq i64 %count, 0
  br i1 %cmp34, label %for.end29, label %for.body

for.body:                                         ; preds = %entry, %for.body
  %dummyiv = phi i64 [ %dummycnt, %for.body ], [ 0, %entry ]
  %indvars.iv39 = phi i64 [ %indvars.iv.next40, %for.body ], [ 0, %entry ]
  %dp.036 = phi ptr [ %add.ptr, %for.body ], [ %destrow, %entry ]
  %p.035 = phi ptr [ %incdec.ptr4, %for.body ], [ %srcrow, %entry ]
  %incdec.ptr = getelementptr inbounds float, ptr %p.035, i64 1
  %0 = load float, ptr %incdec.ptr, align 4
  %incdec.ptr2 = getelementptr inbounds float, ptr %p.035, i64 2
  %1 = load float, ptr %incdec.ptr2, align 4
  %incdec.ptr3 = getelementptr inbounds float, ptr %p.035, i64 3
  %2 = load float, ptr %incdec.ptr3, align 4
  %incdec.ptr4 = getelementptr inbounds float, ptr %p.035, i64 4
  %3 = load float, ptr %incdec.ptr4, align 4
  %4 = load i32, ptr %dp.036, align 4
  %conv5 = fptoui float %0 to i32
  %or = or i32 %4, %conv5
  %arrayidx6 = getelementptr inbounds i32, ptr %dp.036, i64 1
  %5 = load i32, ptr %arrayidx6, align 4
  %conv7 = fptoui float %1 to i32
  %or8 = or i32 %5, %conv7
  %arrayidx9 = getelementptr inbounds i32, ptr %dp.036, i64 2
  %6 = load i32, ptr %arrayidx9, align 4
  %conv10 = fptoui float %2 to i32
  %or11 = or i32 %6, %conv10
  %arrayidx12 = getelementptr inbounds i32, ptr %dp.036, i64 3
  %7 = load i32, ptr %arrayidx12, align 4
  %conv13 = fptoui float %3 to i32
  %or14 = or i32 %7, %conv13
  store i32 %or, ptr %dp.036, align 4
  store i32 %or8, ptr %arrayidx6, align 4
  store i32 %or11, ptr %arrayidx9, align 4
  store i32 %or14, ptr %arrayidx12, align 4
  %add.ptr = getelementptr inbounds i32, ptr %dp.036, i64 4
  %indvars.iv.next40 = add i64 %indvars.iv39, 4
  %dummycnt = add i64 %dummyiv, 1
  %cmp = icmp ult i64 %indvars.iv.next40, %count
  br i1 %cmp, label %for.body, label %for.cond19.preheader

for.cond19.preheader:                             ; preds = %for.body
  %dummyout = add i64 %dummyiv, 1
  %rem = and i64 %count, 3
  %cmp2130 = icmp eq i64 %rem, 0
  br i1 %cmp2130, label %for.end29, label %for.body23.lr.ph

for.body23.lr.ph:                                 ; preds = %for.cond19.preheader
  %8 = and i64 %count, 3
  br label %for.body23

for.body23:                                       ; preds = %for.body23, %for.body23.lr.ph
  %indvars.iv = phi i64 [ 0, %for.body23.lr.ph ], [ %indvars.iv.next, %for.body23 ]
  %dp.132 = phi ptr [ %add.ptr, %for.body23.lr.ph ], [ %incdec.ptr28, %for.body23 ]
  %p.131 = phi ptr [ %incdec.ptr4, %for.body23.lr.ph ], [ %incdec.ptr24, %for.body23 ]
  %incdec.ptr24 = getelementptr inbounds float, ptr %p.131, i64 1
  %9 = load float, ptr %incdec.ptr24, align 4
  %10 = load i32, ptr %dp.132, align 4
  %conv25 = fptoui float %9 to i32
  %or26 = or i32 %10, %conv25
  store i32 %or26, ptr %dp.132, align 4
  %indvars.iv.next = add i64 %indvars.iv, 1
  %incdec.ptr28 = getelementptr inbounds i32, ptr %dp.132, i64 1
  %exitcond = icmp eq i64 %indvars.iv.next, %8
  br i1 %exitcond, label %for.end29, label %for.body23

for.end29:                                        ; preds = %entry, %for.body23, %for.cond19.preheader
  %result = phi i64 [ 0, %entry ], [ %dummyout, %for.body23 ], [ %dummyout, %for.cond19.preheader ]
  ret i64 %result
}