; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=pre-isel-intrinsic-lowering -mattr=+sve -S < %s | FileCheck %s
target triple = "aarch64"

define <vscale x 4 x float> @scalable_vec_acos(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_acos(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.acos.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.acos.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_asin(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_asin(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.asin.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.asin.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_atan(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_atan(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.atan.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.atan.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_canonicalize(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_canonicalize(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP8:%.*]] = call <vscale x 4 x float> @llvm.canonicalize.nxv4f32(<vscale x 4 x float> [[INPUT]])
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.canonicalize.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_cos(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_cos(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.cos.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.cos.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_cosh(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_cosh(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.cosh.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.cosh.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_exp10(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_exp10(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.exp10.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.exp10.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_log2(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_log2(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.log2.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.log2.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_log10(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_log10(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.log10.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.log10.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_sin(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_sin(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.sin.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.sin.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_sinh(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_sinh(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.sinh.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.sinh.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_tan(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_tan(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.tan.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.tan.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_tanh(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_tanh(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; CHECK-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT:    br label %[[BB3:.*]]
; CHECK:       [[BB3]]:
; CHECK-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP7:%.*]] = call float @llvm.tanh.f32(float [[TMP6]])
; CHECK-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; CHECK-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; CHECK-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; CHECK-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; CHECK:       [[BB11]]:
; CHECK-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.tanh.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}