; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=pre-isel-intrinsic-lowering -mtriple=riscv32 -S < %s | FileCheck %s --check-prefix=RV32
; RUN: opt -passes=pre-isel-intrinsic-lowering -mtriple=riscv64 -S < %s | FileCheck %s --check-prefix=RV64

define <vscale x 4 x float> @scalable_vec_sin(<vscale x 4 x float> %input) {
; RV32-LABEL: define <vscale x 4 x float> @scalable_vec_sin(
; RV32-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; RV32-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vscale.i32()
; RV32-NEXT:    [[TMP2:%.*]] = mul nuw i32 [[TMP1]], 4
; RV32-NEXT:    br label %[[BB3:.*]]
; RV32:       [[BB3]]:
; RV32-NEXT:    [[TMP4:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; RV32-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; RV32-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i32 [[TMP4]]
; RV32-NEXT:    [[TMP7:%.*]] = call float @llvm.sin.f32(float [[TMP6]])
; RV32-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i32 [[TMP4]]
; RV32-NEXT:    [[TMP9]] = add i32 [[TMP4]], 1
; RV32-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[TMP9]], [[TMP2]]
; RV32-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV32:       [[BB11]]:
; RV32-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
; RV64-LABEL: define <vscale x 4 x float> @scalable_vec_sin(
; RV64-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; RV64-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; RV64-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; RV64-NEXT:    br label %[[BB3:.*]]
; RV64:       [[BB3]]:
; RV64-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; RV64-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; RV64-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; RV64-NEXT:    [[TMP7:%.*]] = call float @llvm.sin.f32(float [[TMP6]])
; RV64-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; RV64-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; RV64-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; RV64-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV64:       [[BB11]]:
; RV64-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.sin.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_exp(<vscale x 4 x float> %input) {
; RV32-LABEL: define <vscale x 4 x float> @scalable_vec_exp(
; RV32-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; RV32-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vscale.i32()
; RV32-NEXT:    [[TMP2:%.*]] = mul nuw i32 [[TMP1]], 4
; RV32-NEXT:    br label %[[BB3:.*]]
; RV32:       [[BB3]]:
; RV32-NEXT:    [[TMP4:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; RV32-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; RV32-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i32 [[TMP4]]
; RV32-NEXT:    [[TMP7:%.*]] = call float @llvm.exp.f32(float [[TMP6]])
; RV32-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i32 [[TMP4]]
; RV32-NEXT:    [[TMP9]] = add i32 [[TMP4]], 1
; RV32-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[TMP9]], [[TMP2]]
; RV32-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV32:       [[BB11]]:
; RV32-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
; RV64-LABEL: define <vscale x 4 x float> @scalable_vec_exp(
; RV64-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; RV64-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; RV64-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; RV64-NEXT:    br label %[[BB3:.*]]
; RV64:       [[BB3]]:
; RV64-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; RV64-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; RV64-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; RV64-NEXT:    [[TMP7:%.*]] = call float @llvm.exp.f32(float [[TMP6]])
; RV64-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; RV64-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; RV64-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; RV64-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV64:       [[BB11]]:
; RV64-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.exp.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}

define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
; RV32-LABEL: define <vscale x 4 x float> @scalable_vec_log(
; RV32-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; RV32-NEXT:    [[TMP1:%.*]] = call i32 @llvm.vscale.i32()
; RV32-NEXT:    [[TMP2:%.*]] = mul nuw i32 [[TMP1]], 4
; RV32-NEXT:    br label %[[BB3:.*]]
; RV32:       [[BB3]]:
; RV32-NEXT:    [[TMP4:%.*]] = phi i32 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; RV32-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; RV32-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i32 [[TMP4]]
; RV32-NEXT:    [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])
; RV32-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i32 [[TMP4]]
; RV32-NEXT:    [[TMP9]] = add i32 [[TMP4]], 1
; RV32-NEXT:    [[TMP10:%.*]] = icmp eq i32 [[TMP9]], [[TMP2]]
; RV32-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV32:       [[BB11]]:
; RV32-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
; RV64-LABEL: define <vscale x 4 x float> @scalable_vec_log(
; RV64-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; RV64-NEXT:    [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
; RV64-NEXT:    [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; RV64-NEXT:    br label %[[BB3:.*]]
; RV64:       [[BB3]]:
; RV64-NEXT:    [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
; RV64-NEXT:    [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
; RV64-NEXT:    [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
; RV64-NEXT:    [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])
; RV64-NEXT:    [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
; RV64-NEXT:    [[TMP9]] = add i64 [[TMP4]], 1
; RV64-NEXT:    [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
; RV64-NEXT:    br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
; RV64:       [[BB11]]:
; RV64-NEXT:    ret <vscale x 4 x float> [[TMP8]]
;
  %output = call <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float> %input)
  ret <vscale x 4 x float> %output
}