; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: %if x86-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux < %s | FileCheck %s --check-prefix=X86 %}
; RUN: %if aarch64-registered-target %{ opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux < %s | FileCheck %s --check-prefix=AARCH64 %}

define i64 @src(i32 %a) {
; X86-LABEL: define i64 @src(
; X86-SAME: i32 [[A:%.*]]) {
; X86-NEXT:  [[ENTRY:.*:]]
; X86-NEXT:    [[TMP0:%.*]] = sext i32 [[A]] to i64
; X86-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
; X86-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; X86-NEXT:    [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>
; X86-NEXT:    [[TMP4:%.*]] = add nsw <4 x i64> [[TMP3]], splat (i64 4294967297)
; X86-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
; X86-NEXT:    [[TMP8:%.*]] = and <8 x i64> [[TMP5]], <i64 1, i64 1, i64 1, i64 1, i64 -1, i64 -1, i64 -1, i64 -1>
; X86-NEXT:    [[TMP9:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[TMP8]])
; X86-NEXT:    [[OP_RDX:%.*]] = add i64 [[TMP9]], 4294967297
; X86-NEXT:    [[OP_RDX1:%.*]] = add i64 [[OP_RDX]], [[TMP0]]
; X86-NEXT:    ret i64 [[OP_RDX1]]
;
; AARCH64-LABEL: define i64 @src(
; AARCH64-SAME: i32 [[A:%.*]]) {
; AARCH64-NEXT:  [[ENTRY:.*:]]
; AARCH64-NEXT:    [[TMP0:%.*]] = sext i32 [[A]] to i64
; AARCH64-NEXT:    [[TMP1:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i32 0
; AARCH64-NEXT:    [[TMP2:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> poison, <4 x i32> zeroinitializer
; AARCH64-NEXT:    [[TMP3:%.*]] = sext <4 x i32> [[TMP2]] to <4 x i64>
; AARCH64-NEXT:    [[TMP4:%.*]] = add nsw <4 x i64> [[TMP3]], splat (i64 4294967297)
; AARCH64-NEXT:    [[TMP5:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
; AARCH64-NEXT:    [[TMP8:%.*]] = and <8 x i64> [[TMP5]], <i64 1, i64 1, i64 1, i64 1, i64 -1, i64 -1, i64 -1, i64 -1>
; AARCH64-NEXT:    [[TMP9:%.*]] = call i64 @llvm.vector.reduce.add.v8i64(<8 x i64> [[TMP8]])
; AARCH64-NEXT:    [[OP_RDX:%.*]] = add i64 [[TMP9]], 4294967297
; AARCH64-NEXT:    [[OP_RDX1:%.*]] = add i64 [[OP_RDX]], [[TMP0]]
; AARCH64-NEXT:    ret i64 [[OP_RDX1]]
;
entry:
  %0 = sext i32 %a to i64
  %1 = add nsw i64 %0, 4294967297
  %2 = sext i32 %a to i64
  %3 = add nsw i64 %2, 4294967297
  %4 = add i64 %3, %1
  %5 = and i64 %3, 1
  %6 = add i64 %4, %5
  %7 = sext i32 %a to i64
  %8 = add nsw i64 %7, 4294967297
  %9 = add i64 %8, %6
  %10 = and i64 %8, 1
  %11 = add i64 %9, %10
  %12 = sext i32 %a to i64
  %13 = add nsw i64 %12, 4294967297
  %14 = add i64 %13, %11
  %15 = and i64 %13, 1
  %16 = add i64 %14, %15
  %17 = sext i32 %a to i64
  %18 = add nsw i64 %17, 4294967297
  %19 = add i64 %18, %16
  %20 = and i64 %18, 1
  %21 = add i64 %19, %20
  ret i64 %21
}