; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -mtriple=amdgcn-- -passes='loop(simple-loop-unswitch<nontrivial>),verify<loops>' -S < %s | FileCheck %s
; RUN: opt -mtriple=amdgcn-- -passes='loop-mssa(simple-loop-unswitch<nontrivial>),verify<loops>' -S < %s | FileCheck %s
; RUN: opt -mtriple=amdgcn-- -passes='simple-loop-unswitch<nontrivial>' -verify-memoryssa -S < %s | FileCheck %s

declare i32 @a()
declare i32 @b()
declare i32 @c()

; Non-trivial loop unswitching where there are two distinct trivial
; conditions to unswitch within the loop. The conditions are divergent
; and should not unswitch.
define void @test1(ptr %ptr, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: define void @test1(
; CHECK-SAME: ptr [[PTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[LOOP_BEGIN:.*]]
; CHECK:       [[LOOP_BEGIN]]:
; CHECK-NEXT:    br i1 [[COND1]], label %[[LOOP_A:.*]], label %[[LOOP_B:.*]]
; CHECK:       [[LOOP_A]]:
; CHECK-NEXT:    [[UNUSED_A:%.*]] = call i32 @a()
; CHECK-NEXT:    br label %[[LATCH:.*]]
; CHECK:       [[LOOP_B]]:
; CHECK-NEXT:    br i1 [[COND2]], label %[[LOOP_B_A:.*]], label %[[LOOP_B_B:.*]]
; CHECK:       [[LOOP_B_A]]:
; CHECK-NEXT:    [[UNUSED_B:%.*]] = call i32 @b()
; CHECK-NEXT:    br label %[[LATCH]]
; CHECK:       [[LOOP_B_B]]:
; CHECK-NEXT:    [[UNUSED_C:%.*]] = call i32 @c()
; CHECK-NEXT:    br label %[[LATCH]]
; CHECK:       [[LATCH]]:
; CHECK-NEXT:    [[V:%.*]] = load i1, ptr [[PTR]], align 1
; CHECK-NEXT:    br i1 [[V]], label %[[LOOP_BEGIN]], label %[[LOOP_EXIT:.*]]
; CHECK:       [[LOOP_EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop_begin

loop_begin:
  br i1 %cond1, label %loop_a, label %loop_b

loop_a:
  %unused.a = call i32 @a()
  br label %latch

loop_b:
  br i1 %cond2, label %loop_b_a, label %loop_b_b

loop_b_a:
  %unused.b = call i32 @b()
  br label %latch

loop_b_b:
  %unused.c = call i32 @c()
  br label %latch

latch:
  %v = load i1, ptr %ptr
  br i1 %v, label %loop_begin, label %loop_exit

loop_exit:
  ret void
}

; Non-trivial loop unswitching where there are two distinct trivial
; conditions to unswitch within the loop. The conditions are known to
; be uniform, so it should be unswitchable. However, unswitch
; currently does not make use of UniformityAnalysis.
define amdgpu_kernel void @test1_uniform(ptr %ptr, i1 %cond1, i1 %cond2) {
; CHECK-LABEL: define amdgpu_kernel void @test1_uniform(
; CHECK-SAME: ptr [[PTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[LOOP_BEGIN:.*]]
; CHECK:       [[LOOP_BEGIN]]:
; CHECK-NEXT:    br i1 [[COND1]], label %[[LOOP_A:.*]], label %[[LOOP_B:.*]]
; CHECK:       [[LOOP_A]]:
; CHECK-NEXT:    [[UNUSED_A:%.*]] = call i32 @a()
; CHECK-NEXT:    br label %[[LATCH:.*]]
; CHECK:       [[LOOP_B]]:
; CHECK-NEXT:    br i1 [[COND2]], label %[[LOOP_B_A:.*]], label %[[LOOP_B_B:.*]]
; CHECK:       [[LOOP_B_A]]:
; CHECK-NEXT:    [[UNUSED_B:%.*]] = call i32 @b()
; CHECK-NEXT:    br label %[[LATCH]]
; CHECK:       [[LOOP_B_B]]:
; CHECK-NEXT:    [[UNUSED_C:%.*]] = call i32 @c()
; CHECK-NEXT:    br label %[[LATCH]]
; CHECK:       [[LATCH]]:
; CHECK-NEXT:    [[V:%.*]] = load i1, ptr [[PTR]], align 1
; CHECK-NEXT:    br i1 [[V]], label %[[LOOP_BEGIN]], label %[[LOOP_EXIT:.*]]
; CHECK:       [[LOOP_EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop_begin

loop_begin:
  br i1 %cond1, label %loop_a, label %loop_b

loop_a:
  %unused.a = call i32 @a()
  br label %latch

loop_b:
  br i1 %cond2, label %loop_b_a, label %loop_b_b

loop_b_a:
  %unused.b = call i32 @b()
  br label %latch

loop_b_b:
  %unused.c = call i32 @c()
  br label %latch

latch:
  %v = load i1, ptr %ptr
  br i1 %v, label %loop_begin, label %loop_exit

loop_exit:
  ret void
}

; Non-trivial loop unswitching where there are two distinct trivial
; conditions to unswitch within the loop. There is no divergence
; because it's assumed it can only execute with a workgroup of size 1.
define void @test1_single_lane_execution(ptr %ptr, i1 %cond1, i1 %cond2) #0 {
; CHECK-LABEL: define void @test1_single_lane_execution(
; CHECK-SAME: ptr [[PTR:%.*]], i1 [[COND1:%.*]], i1 [[COND2:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    br label %[[LOOP_BEGIN:.*]]
; CHECK:       [[LOOP_BEGIN]]:
; CHECK-NEXT:    br i1 [[COND1]], label %[[LOOP_A:.*]], label %[[LOOP_B:.*]]
; CHECK:       [[LOOP_A]]:
; CHECK-NEXT:    [[TMP0:%.*]] = call i32 @a()
; CHECK-NEXT:    br label %[[LATCH:.*]]
; CHECK:       [[LOOP_B]]:
; CHECK-NEXT:    br i1 [[COND2]], label %[[LOOP_B_A:.*]], label %[[LOOP_B_B:.*]]
; CHECK:       [[LOOP_B_A]]:
; CHECK-NEXT:    [[TMP1:%.*]] = call i32 @b()
; CHECK-NEXT:    br label %[[LATCH]]
; CHECK:       [[LOOP_B_B]]:
; CHECK-NEXT:    [[TMP2:%.*]] = call i32 @c()
; CHECK-NEXT:    br label %[[LATCH]]
; CHECK:       [[LATCH]]:
; CHECK-NEXT:    [[V:%.*]] = load i1, ptr [[PTR]], align 1
; CHECK-NEXT:    br i1 [[V]], label %[[LOOP_BEGIN]], label %[[LOOP_EXIT:.*]]
; CHECK:       [[LOOP_EXIT]]:
; CHECK-NEXT:    ret void
;
entry:
  br label %loop_begin

loop_begin:
  br i1 %cond1, label %loop_a, label %loop_b

loop_a:
  call i32 @a()
  br label %latch
; The 'loop_a' unswitched loop.

loop_b:
  br i1 %cond2, label %loop_b_a, label %loop_b_b
; The second unswitched condition.

loop_b_a:
  call i32 @b()
  br label %latch
; The 'loop_b_a' unswitched loop.

loop_b_b:
  call i32 @c()
  br label %latch
; The 'loop_b_b' unswitched loop.

latch:
  %v = load i1, ptr %ptr
  br i1 %v, label %loop_begin, label %loop_exit

loop_exit:
  ret void
}

attributes #0 = { "amdgpu-flat-work-group-size"="1,1" }