# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=amdgcn -mcpu=gfx1250 --timeline --iterations=1 --timeline-max-cycles=0 < %s | FileCheck %s v_permlane16_swap_b32_e32 v255, v13 v_maximum3_f32 v12, v12, v24 /*v792*/, v2 /*v770*/ s_set_vgpr_msb 0x3c03 ; msbs: dst=0 src0=3 src1=0 src2=0 ds_load_tr8_b64 v[162:163], v232 /*v1000*/ offset:43024 s_set_vgpr_msb 0x302 ; msbs: dst=0 src0=2 src1=0 src2=0 v_pk_add_f32 v[10:11], v[18:19] /*v[530:531]*/, v[10:11] s_set_vgpr_msb 0x228 ; msbs: dst=0 src0=0 src1=2 src2=2 v_maximum3_f32 v14, v14, v216 /*v728*/, v218 /*v730*/ v_maximum3_f32 v16, v16, v219 /*v731*/, v221 /*v733*/ s_set_vgpr_msb 0x2838 ; msbs: dst=0 src0=0 src1=2 src2=3 v_maximum3_f32 v17, v70, v255 /*v767*/, v1 /*v769*/ # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 11 # CHECK-NEXT: Total Cycles: 41 # CHECK-NEXT: Total uOps: 11 # CHECK: Dispatch Width: 1 # CHECK-NEXT: uOps Per Cycle: 0.27 # CHECK-NEXT: IPC: 0.27 # CHECK-NEXT: Block RThroughput: 11.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 5 2.00 U v_permlane16_swap_b32_e32 v255, v13 # CHECK-NEXT: 1 5 1.00 U v_maximum3_f32 v12, v12, v24, v2 # CHECK-NEXT: 1 2 1.00 U s_set_vgpr_msb 0x3c03 # CHECK-NEXT: 1 20 1.00 * U ds_load_tr8_b64 v[162:163], v232 offset:43024 # CHECK-NEXT: 1 2 1.00 U s_set_vgpr_msb 0x302 # CHECK-NEXT: 1 5 1.00 U v_pk_add_f32 v[10:11], v[18:19], v[10:11] # CHECK-NEXT: 1 2 1.00 U s_set_vgpr_msb 0x228 # CHECK-NEXT: 1 5 1.00 U v_maximum3_f32 v14, v14, v216, v218 # CHECK-NEXT: 1 5 1.00 U v_maximum3_f32 v16, v16, v219, v221 # CHECK-NEXT: 1 2 1.00 U s_set_vgpr_msb 0x2838 # CHECK-NEXT: 1 5 1.00 U v_maximum3_f32 v17, v70, v255, v1 # CHECK: Resources: # CHECK-NEXT: [0] - HWBranch # CHECK-NEXT: [1] - HWExport # CHECK-NEXT: [2] - HWLGKM # CHECK-NEXT: [3] - HWRC # CHECK-NEXT: [4] - HWSALU # CHECK-NEXT: [5] - HWTransVALU # CHECK-NEXT: [6] - HWVALU # CHECK-NEXT: [7] - HWVMEM # CHECK-NEXT: [8] - HWXDL # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] # CHECK-NEXT: - - 1.00 11.00 4.00 - 7.00 - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] [8] Instructions: # CHECK-NEXT: - - - 1.00 - - 2.00 - - v_permlane16_swap_b32_e32 v255, v13 # CHECK-NEXT: - - - 1.00 - - 1.00 - - v_maximum3_f32 v12, v12, v24, v2 # CHECK-NEXT: - - - 1.00 1.00 - - - - s_set_vgpr_msb 0x3c03 # CHECK-NEXT: - - 1.00 1.00 - - - - - ds_load_tr8_b64 v[162:163], v232 offset:43024 # CHECK-NEXT: - - - 1.00 1.00 - - - - s_set_vgpr_msb 0x302 # CHECK-NEXT: - - - 1.00 - - 1.00 - - v_pk_add_f32 v[10:11], v[18:19], v[10:11] # CHECK-NEXT: - - - 1.00 1.00 - - - - s_set_vgpr_msb 0x228 # CHECK-NEXT: - - - 1.00 - - 1.00 - - v_maximum3_f32 v14, v14, v216, v218 # CHECK-NEXT: - - - 1.00 - - 1.00 - - v_maximum3_f32 v16, v16, v219, v221 # CHECK-NEXT: - - - 1.00 1.00 - - - - s_set_vgpr_msb 0x2838 # CHECK-NEXT: - - - 1.00 - - 1.00 - - v_maximum3_f32 v17, v70, v255, v1 # CHECK: Timeline view: # CHECK-NEXT: 0123456789 0123456789 # CHECK-NEXT: Index 0123456789 0123456789 0 # CHECK: [0,0] DeeeeE . . . . . . . v_permlane16_swap_b32_e32 v255, v13 # CHECK-NEXT: [0,1] . DeeeeE . . . . . . . v_maximum3_f32 v12, v12, v24, v2 # CHECK-NEXT: [0,2] . DeE . . . . . . . s_set_vgpr_msb 0x3c03 # CHECK-NEXT: [0,3] . .DeeeeeeeeeeeeeeeeeeeE . . . ds_load_tr8_b64 v[162:163], v232 offset:43024 # CHECK-NEXT: [0,4] . . . . . DeE . . . s_set_vgpr_msb 0x302 # CHECK-NEXT: [0,5] . . . . . .DeeeeE . . v_pk_add_f32 v[10:11], v[18:19], v[10:11] # CHECK-NEXT: [0,6] . . . . . . DeE . . s_set_vgpr_msb 0x228 # CHECK-NEXT: [0,7] . . . . . . DeeeeE . v_maximum3_f32 v14, v14, v216, v218 # CHECK-NEXT: [0,8] . . . . . . .DeeeeE . v_maximum3_f32 v16, v16, v219, v221 # CHECK-NEXT: [0,9] . . . . . . . DeE . s_set_vgpr_msb 0x2838 # CHECK-NEXT: [0,10] . . . . . . . DeeeeE v_maximum3_f32 v17, v70, v255, v1 # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 0.0 0.0 0.0 v_permlane16_swap_b32_e32 v255, v13 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 v_maximum3_f32 v12, v12, v24, v2 # CHECK-NEXT: 2. 1 0.0 0.0 0.0 s_set_vgpr_msb 0x3c03 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 ds_load_tr8_b64 v[162:163], v232 offset:43024 # CHECK-NEXT: 4. 1 0.0 0.0 0.0 s_set_vgpr_msb 0x302 # CHECK-NEXT: 5. 1 0.0 0.0 0.0 v_pk_add_f32 v[10:11], v[18:19], v[10:11] # CHECK-NEXT: 6. 1 0.0 0.0 0.0 s_set_vgpr_msb 0x228 # CHECK-NEXT: 7. 1 0.0 0.0 0.0 v_maximum3_f32 v14, v14, v216, v218 # CHECK-NEXT: 8. 1 0.0 0.0 0.0 v_maximum3_f32 v16, v16, v219, v221 # CHECK-NEXT: 9. 1 0.0 0.0 0.0 s_set_vgpr_msb 0x2838 # CHECK-NEXT: 10. 1 0.0 0.0 0.0 v_maximum3_f32 v17, v70, v255, v1 # CHECK-NEXT: 11 0.0 0.0 0.0