# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-ax45mpv -iterations=1 -instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, ta, ma vle8.v v8, (a0) vsetvli zero, zero, e8, mf4, ta, ma vle8.v v8, (a0) vsetvli zero, zero, e8, mf2, ta, ma vle8.v v8, (a0) vsetvli zero, zero, e8, m1, ta, ma vle8.v v8, (a0) vsetvli zero, zero, e8, m2, ta, ma vle8.v v8, (a0) vsetvli zero, zero, e8, m4, ta, ma vle8.v v8, (a0) vsetvli zero, zero, e8, m8, ta, ma vle8.v v8, (a0) vsetvli zero, zero, e16, mf4, ta, ma vle16.v v8, (a0) vsetvli zero, zero, e16, mf2, ta, ma vle16.v v8, (a0) vsetvli zero, zero, e16, m1, ta, ma vle16.v v8, (a0) vsetvli zero, zero, e16, m2, ta, ma vle16.v v8, (a0) vsetvli zero, zero, e16, m4, ta, ma vle16.v v8, (a0) vsetvli zero, zero, e16, m8, ta, ma vle16.v v8, (a0) vsetvli zero, zero, e32, mf2, ta, ma vle32.v v8, (a0) vsetvli zero, zero, e32, m1, ta, ma vle32.v v8, (a0) vsetvli zero, zero, e32, m2, ta, ma vle32.v v8, (a0) vsetvli zero, zero, e32, m4, ta, ma vle32.v v8, (a0) vsetvli zero, zero, e32, m8, ta, ma vle32.v v8, (a0) vsetvli zero, zero, e64, m1, ta, ma vle64.v v8, (a0) vsetvli zero, zero, e64, m2, ta, ma vle64.v v8, (a0) vsetvli zero, zero, e64, m4, ta, ma vle64.v v8, (a0) vsetvli zero, zero, e64, m8, ta, ma vle64.v v8, (a0) vsetvli zero, zero, e8, mf8, ta, ma vse8.v v8, (a0) vsetvli zero, zero, e8, mf4, ta, ma vse8.v v8, (a0) vsetvli zero, zero, e8, mf2, ta, ma vse8.v v8, (a0) vsetvli zero, zero, e8, m1, ta, ma vse8.v v8, (a0) vsetvli zero, zero, e8, m2, ta, ma vse8.v v8, (a0) vsetvli zero, zero, e8, m4, ta, ma vse8.v v8, (a0) vsetvli zero, zero, e8, m8, ta, ma vse8.v v8, (a0) vsetvli zero, zero, e16, mf4, ta, ma vse16.v v8, (a0) vsetvli zero, zero, e16, mf2, ta, ma vse16.v v8, (a0) vsetvli zero, zero, e16, m1, ta, ma vse16.v v8, (a0) vsetvli zero, zero, e16, m2, ta, ma vse16.v v8, (a0) vsetvli zero, zero, e16, m4, ta, ma vse16.v v8, (a0) vsetvli zero, zero, e16, m8, ta, ma vse16.v v8, (a0) vsetvli zero, zero, e32, mf2, ta, ma vse32.v v8, (a0) vsetvli zero, zero, e32, m1, ta, ma vse32.v v8, (a0) vsetvli zero, zero, e32, m2, ta, ma vse32.v v8, (a0) vsetvli zero, zero, e32, m4, ta, ma vse32.v v8, (a0) vsetvli zero, zero, e32, m8, ta, ma vse32.v v8, (a0) vsetvli zero, zero, e64, m1, ta, ma vse64.v v8, (a0) vsetvli zero, zero, e64, m2, ta, ma vse64.v v8, (a0) vsetvli zero, zero, e64, m4, ta, ma vse64.v v8, (a0) vsetvli zero, zero, e64, m8, ta, ma vse64.v v8, (a0) # Unit-stride mask load/store vsetvli zero, zero, e8, mf8, ta, ma vlm.v v8, (a0) vsetvli zero, zero, e8, mf4, ta, ma vlm.v v8, (a0) vsetvli zero, zero, e8, mf2, ta, ma vlm.v v8, (a0) vsetvli zero, zero, e8, m1, ta, ma vlm.v v8, (a0) vsetvli zero, zero, e8, m2, ta, ma vlm.v v8, (a0) vsetvli zero, zero, e8, m4, ta, ma vlm.v v8, (a0) vsetvli zero, zero, e8, m8, ta, ma vlm.v v8, (a0) vsetvli zero, zero, e8, mf8, ta, ma vsm.v v8, (a0) vsetvli zero, zero, e8, mf4, ta, ma vsm.v v8, (a0) vsetvli zero, zero, e8, mf2, ta, ma vsm.v v8, (a0) vsetvli zero, zero, e8, m1, ta, ma vsm.v v8, (a0) vsetvli zero, zero, e8, m2, ta, ma vsm.v v8, (a0) vsetvli zero, zero, e8, m4, ta, ma vsm.v v8, (a0) vsetvli zero, zero, e8, m8, ta, ma vsm.v v8, (a0) # Fault-only-first vsetvli zero, zero, e8, mf8, ta, ma vle8ff.v v8, (a0) vsetvli zero, zero, e8, mf4, ta, ma vle8ff.v v8, (a0) vsetvli zero, zero, e8, mf2, ta, ma vle8ff.v v8, (a0) vsetvli zero, zero, e8, m1, ta, ma vle8ff.v v8, (a0) vsetvli zero, zero, e8, m2, ta, ma vle8ff.v v8, (a0) vsetvli zero, zero, e8, m4, ta, ma vle8ff.v v8, (a0) vsetvli zero, zero, e8, m8, ta, ma vle8ff.v v8, (a0) vsetvli zero, zero, e16, mf4, ta, ma vle16ff.v v8, (a0) vsetvli zero, zero, e16, mf2, ta, ma vle16ff.v v8, (a0) vsetvli zero, zero, e16, m1, ta, ma vle16ff.v v8, (a0) vsetvli zero, zero, e16, m2, ta, ma vle16ff.v v8, (a0) vsetvli zero, zero, e16, m4, ta, ma vle16ff.v v8, (a0) vsetvli zero, zero, e16, m8, ta, ma vle16ff.v v8, (a0) vsetvli zero, zero, e32, mf2, ta, ma vle32ff.v v8, (a0) vsetvli zero, zero, e32, m1, ta, ma vle32ff.v v8, (a0) vsetvli zero, zero, e32, m2, ta, ma vle32ff.v v8, (a0) vsetvli zero, zero, e32, m4, ta, ma vle32ff.v v8, (a0) vsetvli zero, zero, e32, m8, ta, ma vle32ff.v v8, (a0) vsetvli zero, zero, e64, m1, ta, ma vle64ff.v v8, (a0) vsetvli zero, zero, e64, m2, ta, ma vle64ff.v v8, (a0) vsetvli zero, zero, e64, m4, ta, ma vle64ff.v v8, (a0) vsetvli zero, zero, e64, m8, ta, ma vle64ff.v v8, (a0) # CHECK: Resources: # CHECK-NEXT: [0] - Andes45ALU:2 # CHECK-NEXT: [1] - Andes45CSR:1 # CHECK-NEXT: [2] - Andes45FDIV:1 # CHECK-NEXT: [3] - Andes45FMAC:1 # CHECK-NEXT: [4] - Andes45FMISC:1 # CHECK-NEXT: [5] - Andes45FMV:1 # CHECK-NEXT: [6] - Andes45LSU:1 # CHECK-NEXT: [7] - Andes45MDU:1 # CHECK-NEXT: [8] - Andes45VALU:1 # CHECK-NEXT: [9] - Andes45VDIV:1 # CHECK-NEXT: [10] - Andes45VFDIV:1 # CHECK-NEXT: [11] - Andes45VFMIS:1 # CHECK-NEXT: [12] - Andes45VLSU:1 # CHECK-NEXT: [13] - Andes45VMAC:1 # CHECK-NEXT: [14] - Andes45VMASK:1 # CHECK-NEXT: [15] - Andes45VPERMUT:1 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [7]: Bypass Latency # CHECK-NEXT: [8]: Resources ( | [] | [,