# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=riscv64 -mcpu=andes-nx45 -timeline -iterations=1 < %s | FileCheck %s # zero (x0) as input sb zero, 0x0(a0) lbu a2, -0x1(a1) sb a2, 0x0(a1) # zero (x0) as output add zero, a3, a4 add a5, a3, a4 sb a5, 0x0(a1) # CHECK: Iterations: 1 # CHECK-NEXT: Instructions: 6 # CHECK-NEXT: Total Cycles: 10 # CHECK-NEXT: Total uOps: 6 # CHECK: Dispatch Width: 2 # CHECK-NEXT: uOps Per Cycle: 0.60 # CHECK-NEXT: IPC: 0.60 # CHECK-NEXT: Block RThroughput: 4.0 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK-NEXT: 1 1 1.00 * sb zero, 0(a0) # CHECK-NEXT: 1 5 1.00 * lbu a2, -1(a1) # CHECK-NEXT: 1 1 1.00 * sb a2, 0(a1) # CHECK-NEXT: 1 1 0.50 add zero, a3, a4 # CHECK-NEXT: 1 1 0.50 add a5, a3, a4 # CHECK-NEXT: 1 1 1.00 * sb a5, 0(a1) # CHECK: Resources: # CHECK-NEXT: [0.0] - Andes45ALU # CHECK-NEXT: [0.1] - Andes45ALU # CHECK-NEXT: [1] - Andes45CSR # CHECK-NEXT: [2] - Andes45FDIV # CHECK-NEXT: [3] - Andes45FMAC # CHECK-NEXT: [4] - Andes45FMISC # CHECK-NEXT: [5] - Andes45FMV # CHECK-NEXT: [6] - Andes45LSU # CHECK-NEXT: [7] - Andes45MDU # CHECK-NEXT: [8] - Andes45VALU # CHECK-NEXT: [9] - Andes45VDIV # CHECK-NEXT: [10] - Andes45VFDIV # CHECK-NEXT: [11] - Andes45VFMIS # CHECK-NEXT: [12] - Andes45VLSU # CHECK-NEXT: [13] - Andes45VMAC # CHECK-NEXT: [14] - Andes45VMASK # CHECK-NEXT: [15] - Andes45VPERMUT # CHECK: Resource pressure per iteration: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] # CHECK-NEXT: 1.00 1.00 - - - - - 4.00 - - - - - - - - - # CHECK: Resource pressure by instruction: # CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Instructions: # CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sb zero, 0(a0) # CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - lbu a2, -1(a1) # CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sb a2, 0(a1) # CHECK-NEXT: - 1.00 - - - - - - - - - - - - - - - add zero, a3, a4 # CHECK-NEXT: 1.00 - - - - - - - - - - - - - - - - add a5, a3, a4 # CHECK-NEXT: - - - - - - - 1.00 - - - - - - - - - sb a5, 0(a1) # CHECK: Timeline view: # CHECK-NEXT: Index 0123456789 # CHECK: [0,0] DE . . sb zero, 0(a0) # CHECK-NEXT: [0,1] .DeeeeE . lbu a2, -1(a1) # CHECK-NEXT: [0,2] . .DE . sb a2, 0(a1) # CHECK-NEXT: [0,3] . .DE . add zero, a3, a4 # CHECK-NEXT: [0,4] . . DE. add a5, a3, a4 # CHECK-NEXT: [0,5] . . DE sb a5, 0(a1) # CHECK: Average Wait times (based on the timeline view): # CHECK-NEXT: [0]: Executions # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK: [0] [1] [2] [3] # CHECK-NEXT: 0. 1 0.0 0.0 0.0 sb zero, 0(a0) # CHECK-NEXT: 1. 1 0.0 0.0 0.0 lbu a2, -1(a1) # CHECK-NEXT: 2. 1 0.0 0.0 0.0 sb a2, 0(a1) # CHECK-NEXT: 3. 1 0.0 0.0 0.0 add zero, a3, a4 # CHECK-NEXT: 4. 1 0.0 0.0 0.0 add a5, a3, a4 # CHECK-NEXT: 5. 1 0.0 0.0 0.0 sb a5, 0(a1) # CHECK-NEXT: 6 0.0 0.0 0.0