# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 -instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e32, m1, ta, ma vmslt.vv v0, v4, v20 vmsle.vv v8, v4, v20 vmsgt.vv v8, v20, v4 vmsge.vv v8, v20, v4 vmseq.vv v8, v4, v20 vmsne.vv v8, v4, v20 vmsltu.vv v8, v4, v20 vmsleu.vv v8, v4, v20 vmsgtu.vv v8, v20, v4 vmsgeu.vv v8, v20, v4 vmflt.vv v0, v4, v20 vmfle.vv v8, v4, v20 vmfgt.vv v8, v20, v4 vmfge.vv v8, v20, v4 vmfeq.vv v8, v4, v20 vmfne.vv v8, v4, v20 vmadc.vv v8, v4, v20 vmsbc.vv v8, v4, v20 vfirst.m a2, v4 vpopc.m a2, v4 viota.m v8, v4 vmsbf.m v8, v4 vmsif.m v8, v4 vmsof.m v8, v4 # CHECK: Resources: # CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1 # CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1 # CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1 # CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB # CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1 # CHECK-NEXT: [5] - VLEN512SiFive7VA1:1 # CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1 # CHECK-NEXT: [7] - VLEN512SiFive7VL:1 # CHECK-NEXT: [8] - VLEN512SiFive7VS:1 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [7]: Bypass Latency # CHECK-NEXT: [8]: Resources ( | [] | [,