# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-u74 -timeline -iterations=1 < %s \
# RUN:   | FileCheck %s

# Check that bypasses with SP operand work correctly

c.mv sp, a0
c.addi4spn a1, sp, 12
addi sp, t0, 16
c.addi16sp sp, -80
addi t0, sp, 20

# CHECK:      Iterations:        1
# CHECK-NEXT: Instructions:      5
# CHECK-NEXT: Total Cycles:      7
# CHECK-NEXT: Total uOps:        5

# CHECK:      Dispatch Width:    2
# CHECK-NEXT: uOps Per Cycle:    0.71
# CHECK-NEXT: IPC:               0.71
# CHECK-NEXT: Block RThroughput: 2.5

# CHECK:      Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
# CHECK-NEXT:  1      3     0.50                        mv	sp, a0
# CHECK-NEXT:  1      3     0.50                        addi	a1, sp, 12
# CHECK-NEXT:  1      3     0.50                        addi	sp, t0, 16
# CHECK-NEXT:  1      3     0.50                        addi	sp, sp, -80
# CHECK-NEXT:  1      3     0.50                        addi	t0, sp, 20

# CHECK:      Resources:
# CHECK-NEXT: [0]   - VLEN512SiFive7FDiv
# CHECK-NEXT: [1]   - VLEN512SiFive7IDiv
# CHECK-NEXT: [2]   - VLEN512SiFive7PipeA
# CHECK-NEXT: [3]   - VLEN512SiFive7PipeB
# CHECK-NEXT: [4]   - VLEN512SiFive7VA1
# CHECK-NEXT: [5]   - VLEN512SiFive7VCQ
# CHECK-NEXT: [6]   - VLEN512SiFive7VL
# CHECK-NEXT: [7]   - VLEN512SiFive7VS

# CHECK:      Resource pressure per iteration:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
# CHECK-NEXT:  -      -     2.00   3.00    -      -      -      -

# CHECK:      Resource pressure by instruction:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     mv	sp, a0
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     addi	a1, sp, 12
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     addi	sp, t0, 16
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     addi	sp, sp, -80
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     addi	t0, sp, 20

# CHECK:      Timeline view:
# CHECK-NEXT: Index     0123456

# CHECK:      [0,0]     DeeE ..   mv	sp, a0
# CHECK-NEXT: [0,1]     .DeeE..   addi	a1, sp, 12
# CHECK-NEXT: [0,2]     .DeeE..   addi	sp, t0, 16
# CHECK-NEXT: [0,3]     . DeeE.   addi	sp, sp, -80
# CHECK-NEXT: [0,4]     .  DeeE   addi	t0, sp, 20

# CHECK:      Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage

# CHECK:            [0]    [1]    [2]    [3]
# CHECK-NEXT: 0.     1     0.0    0.0    0.0       mv	sp, a0
# CHECK-NEXT: 1.     1     0.0    0.0    0.0       addi	a1, sp, 12
# CHECK-NEXT: 2.     1     0.0    0.0    0.0       addi	sp, t0, 16
# CHECK-NEXT: 3.     1     0.0    0.0    0.0       addi	sp, sp, -80
# CHECK-NEXT: 4.     1     0.0    0.0    0.0       addi	t0, sp, 20
# CHECK-NEXT:        5     0.0    0.0    0.0       <total>