# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p550 -iterations=1 -instruction-tables=full  %p/../Inputs/integer.s | FileCheck  %s

# CHECK:      Resources:
# CHECK-NEXT: [0]   - SiFiveP500Div:1
# CHECK-NEXT: [1]   - SiFiveP500FEXQ0:1
# CHECK-NEXT: [2]   - SiFiveP500FEXQ1:1
# CHECK-NEXT: [3]   - SiFiveP500FloatArith:2 SiFiveP500FEXQ0, SiFiveP500FEXQ1
# CHECK-NEXT: [4]   - SiFiveP500FloatDiv:1
# CHECK-NEXT: [5]   - SiFiveP500IEXQ0:1
# CHECK-NEXT: [6]   - SiFiveP500IEXQ1:1
# CHECK-NEXT: [7]   - SiFiveP500IEXQ2:1
# CHECK-NEXT: [8]   - SiFiveP500IntArith:3 SiFiveP500IEXQ0, SiFiveP500IEXQ1, SiFiveP500IEXQ2
# CHECK-NEXT: [9]   - SiFiveP500Load:1
# CHECK-NEXT: [10]  - SiFiveP500Store:1

# CHECK:      Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK-NEXT: [7]: Bypass Latency
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
# CHECK-NEXT: [9]: LLVM Opcode Name

# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_ADDI                     addi	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_ADDIW                    addiw	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SLTI                       slti	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SLTIU                      seqz	a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_ANDI                     andi	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         ORI                        ori	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         XORI                       xori	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_SLLI                     slli	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_SRLI                     srli	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_SRAI                     srai	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SLLIW                      slliw	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SRLIW                      srliw	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SRAIW                      sraiw	a0, a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_LUI                      lui	a0, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         AUIPC                      auipc	a1, 1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_ADD                      add	a0, a0, a1
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_ADDW                     addw	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SLT                        slt	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SLTU                       sltu	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_AND                      and	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_OR                       or	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_XOR                      xor	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SLL                        sll	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SRL                        srl	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SRA                        sra	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SLLW                       sllw	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SRLW                       srlw	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         SRAW                       sraw	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_SUB                      sub	a0, a0, a0
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_SUBW                     subw	a0, a0, a0
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         JAL                        jal	a0, .Ltmp0
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         C_JALR                     jalr	a0
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         BEQ                        beq	a0, a0, .Ltmp1
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         BNE                        bne	a0, a0, .Ltmp2
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         BLT                        blt	a0, a0, .Ltmp3
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         BLTU                       bltu	a0, a0, .Ltmp4
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         BGE                        bge	a0, a0, .Ltmp5
# CHECK-NEXT:  1      1     1.00                         1     SiFiveP500IEXQ0,SiFiveP500IntArith         BGEU                       bgeu	a0, a0, .Ltmp6
# CHECK-NEXT:  1      1     0.33                         1     SiFiveP500IntArith                         C_ADD                      add	a0, a0, a0
# CHECK-NEXT:  1      4     1.00    *                    4     SiFiveP500Load                             LB                         lb	t0, 0(a0)
# CHECK-NEXT:  1      4     1.00    *                    4     SiFiveP500Load                             LBU                        lbu	t0, 0(a0)
# CHECK-NEXT:  1      4     1.00    *                    4     SiFiveP500Load                             LH                         lh	t0, 0(a0)
# CHECK-NEXT:  1      4     1.00    *                    4     SiFiveP500Load                             LHU                        lhu	t0, 0(a0)
# CHECK-NEXT:  1      4     1.00    *                    4     SiFiveP500Load                             LW                         lw	t0, 0(a0)
# CHECK-NEXT:  1      4     1.00    *                    4     SiFiveP500Load                             LWU                        lwu	t0, 0(a0)
# CHECK-NEXT:  1      4     1.00    *                    4     SiFiveP500Load                             LD                         ld	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     SiFiveP500Store                            SB                         sb	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     SiFiveP500Store                            SH                         sh	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     SiFiveP500Store                            SW                         sw	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     SiFiveP500Store                            SD                         sd	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00                  U      1     SiFiveP500IEXQ1,SiFiveP500IntArith         CSRRW                      csrrw	t0, 4095, t1
# CHECK-NEXT:  1      1     1.00                  U      1     SiFiveP500IEXQ1,SiFiveP500IntArith         CSRRS                      csrrs	s3, fflags, s5
# CHECK-NEXT:  1      1     1.00                  U      1     SiFiveP500IEXQ1,SiFiveP500IntArith         CSRRC                      csrrc	sp, 0, ra
# CHECK-NEXT:  1      1     1.00                  U      1     SiFiveP500IEXQ1,SiFiveP500IntArith         CSRRWI                     csrrwi	a5, 0, 0
# CHECK-NEXT:  1      1     1.00                  U      1     SiFiveP500IEXQ1,SiFiveP500IntArith         CSRRSI                     csrrsi	t2, 4095, 31
# CHECK-NEXT:  1      1     1.00                  U      1     SiFiveP500IEXQ1,SiFiveP500IntArith         CSRRCI                     csrrci	t1, sscratch, 5

# CHECK:      Resources:
# CHECK-NEXT: [0]   - SiFiveP500Div
# CHECK-NEXT: [1]   - SiFiveP500FEXQ0
# CHECK-NEXT: [2]   - SiFiveP500FEXQ1
# CHECK-NEXT: [3]   - SiFiveP500FloatDiv
# CHECK-NEXT: [4]   - SiFiveP500IEXQ0
# CHECK-NEXT: [5]   - SiFiveP500IEXQ1
# CHECK-NEXT: [6]   - SiFiveP500IEXQ2
# CHECK-NEXT: [7]   - SiFiveP500Load
# CHECK-NEXT: [8]   - SiFiveP500Store

# CHECK:      Resource pressure per iteration:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]
# CHECK-NEXT:  -      -      -      -     18.33  16.33  10.33  7.00   4.00

# CHECK:      Resource pressure by instruction:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    Instructions:
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     addi	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     addiw	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     slti	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     seqz	a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     andi	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     ori	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     xori	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     slli	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     srli	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     srai	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     slliw	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     srliw	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     sraiw	a0, a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     lui	a0, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     auipc	a1, 1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     add	a0, a0, a1
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     addw	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     slt	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     sltu	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     and	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     or	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     xor	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     sll	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     srl	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     sra	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     sllw	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     srlw	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     sraw	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     sub	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     subw	a0, a0, a0
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     jal	a0, .Ltmp0
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     jalr	a0
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     beq	a0, a0, .Ltmp1
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     bne	a0, a0, .Ltmp2
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     blt	a0, a0, .Ltmp3
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     bltu	a0, a0, .Ltmp4
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     bge	a0, a0, .Ltmp5
# CHECK-NEXT:  -      -      -      -     1.00    -      -      -      -     bgeu	a0, a0, .Ltmp6
# CHECK-NEXT:  -      -      -      -     0.33   0.33   0.33    -      -     add	a0, a0, a0
# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -     lb	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -     lbu	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -     lh	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -     lhu	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -     lw	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -     lwu	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -     1.00    -     ld	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   sb	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   sh	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   sw	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -      -      -      -     1.00   sd	t0, 0(a0)
# CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -     csrrw	t0, 4095, t1
# CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -     csrrs	s3, fflags, s5
# CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -     csrrc	sp, 0, ra
# CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -     csrrwi	a5, 0, 0
# CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -     csrrsi	t2, 4095, 31
# CHECK-NEXT:  -      -      -      -      -     1.00    -      -      -     csrrci	t1, sscratch, 5