# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x180 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s

# CHECK:      Resources:
# CHECK-NEXT: [0]   - VLEN128X100SiFive7FDiv:1
# CHECK-NEXT: [1]   - VLEN128X100SiFive7IDiv:1
# CHECK-NEXT: [2]   - VLEN128X100SiFive7PipeA:1
# CHECK-NEXT: [3]   - VLEN128X100SiFive7PipeAB:2 VLEN128X100SiFive7PipeA, VLEN128X100SiFive7PipeB
# CHECK-NEXT: [4]   - VLEN128X100SiFive7PipeB:1
# CHECK-NEXT: [5]   - VLEN128X100SiFive7VA1:1
# CHECK-NEXT: [6]   - VLEN128X100SiFive7VCQ:1
# CHECK-NEXT: [7]   - VLEN128X100SiFive7VL:1
# CHECK-NEXT: [8]   - VLEN128X100SiFive7VS:1

# CHECK:      Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK-NEXT: [7]: Bypass Latency
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
# CHECK-NEXT: [9]: LLVM Opcode Name

# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_ADDI                     addi	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_ADDIW                    addiw	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SLTI                       slti	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SLTIU                      seqz	a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_ANDI                     andi	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   ORI                        ori	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   XORI                       xori	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_SLLI                     slli	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_SRLI                     srli	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_SRAI                     srai	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SLLIW                      slliw	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SRLIW                      srliw	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SRAIW                      sraiw	a0, a0, 1
# CHECK-NEXT:  1      3     0.50                         3     VLEN128X100SiFive7PipeAB                   C_LUI                      lui	a0, 1
# CHECK-NEXT:  1      3     0.50                         3     VLEN128X100SiFive7PipeAB                   AUIPC                      auipc	a1, 1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_ADD                      add	a0, a0, a1
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_ADDW                     addw	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SLT                        slt	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SLTU                       sltu	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_AND                      and	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_OR                       or	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_XOR                      xor	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SLL                        sll	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SRL                        srl	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SRA                        sra	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SLLW                       sllw	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SRLW                       srlw	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   SRAW                       sraw	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_SUB                      sub	a0, a0, a0
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_SUBW                     subw	a0, a0, a0
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB JAL                  jal	a0, .Ltmp0
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB C_JALR               jalr	a0
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB BEQ                  beq	a0, a0, .Ltmp1
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB BNE                  bne	a0, a0, .Ltmp2
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB BLT                  blt	a0, a0, .Ltmp3
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB BLTU                 bltu	a0, a0, .Ltmp4
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB BGE                  bge	a0, a0, .Ltmp5
# CHECK-NEXT:  1      3     1.00                         3     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB BGEU                 bgeu	a0, a0, .Ltmp6
# CHECK-NEXT:  1      3     0.50                         1     VLEN128X100SiFive7PipeAB                   C_ADD                      add	a0, a0, a0
# CHECK-NEXT:  1      3     1.00    *                    3     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB LB                   lb	t0, 0(a0)
# CHECK-NEXT:  1      3     1.00    *                    3     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB LBU                  lbu	t0, 0(a0)
# CHECK-NEXT:  1      3     1.00    *                    3     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB LH                   lh	t0, 0(a0)
# CHECK-NEXT:  1      3     1.00    *                    3     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB LHU                  lhu	t0, 0(a0)
# CHECK-NEXT:  1      3     1.00    *                    3     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB LW                   lw	t0, 0(a0)
# CHECK-NEXT:  1      3     1.00    *                    3     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB LWU                  lwu	t0, 0(a0)
# CHECK-NEXT:  1      3     1.00    *                    3     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB LD                   ld	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB SB                   sb	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB SH                   sh	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB SW                   sw	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00           *             1     VLEN128X100SiFive7PipeA,VLEN128X100SiFive7PipeAB SD                   sd	t0, 0(a0)
# CHECK-NEXT:  1      1     1.00                  U      1     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CSRRW                csrrw	t0, 4095, t1
# CHECK-NEXT:  1      1     1.00                  U      1     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CSRRS                csrrs	s3, fflags, s5
# CHECK-NEXT:  1      1     1.00                  U      1     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CSRRC                csrrc	sp, 0, ra
# CHECK-NEXT:  1      1     1.00                  U      1     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CSRRWI               csrrwi	a5, 0, 0
# CHECK-NEXT:  1      1     1.00                  U      1     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CSRRSI               csrrsi	t2, 4095, 31
# CHECK-NEXT:  1      1     1.00                  U      1     VLEN128X100SiFive7PipeAB,VLEN128X100SiFive7PipeB CSRRCI               csrrci	t1, sscratch, 5

# CHECK:      Resources:
# CHECK-NEXT: [0]   - VLEN128X100SiFive7FDiv
# CHECK-NEXT: [1]   - VLEN128X100SiFive7IDiv
# CHECK-NEXT: [2]   - VLEN128X100SiFive7PipeA
# CHECK-NEXT: [3]   - VLEN128X100SiFive7PipeB
# CHECK-NEXT: [4]   - VLEN128X100SiFive7VA1
# CHECK-NEXT: [5]   - VLEN128X100SiFive7VCQ
# CHECK-NEXT: [6]   - VLEN128X100SiFive7VL
# CHECK-NEXT: [7]   - VLEN128X100SiFive7VS

# CHECK:      Resource pressure per iteration:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
# CHECK-NEXT:  -      -     26.50  29.50   -      -      -      -

# CHECK:      Resource pressure by instruction:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     addi	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     addiw	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     slti	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     seqz	a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     andi	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     ori	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     xori	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     slli	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     srli	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     srai	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     slliw	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     srliw	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     sraiw	a0, a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     lui	a0, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     auipc	a1, 1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     add	a0, a0, a1
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     addw	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     slt	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     sltu	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     and	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     or	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     xor	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     sll	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     srl	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     sra	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     sllw	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     srlw	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     sraw	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     sub	a0, a0, a0
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     subw	a0, a0, a0
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     jal	a0, .Ltmp0
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     jalr	a0
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     beq	a0, a0, .Ltmp1
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     bne	a0, a0, .Ltmp2
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     blt	a0, a0, .Ltmp3
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     bltu	a0, a0, .Ltmp4
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     bge	a0, a0, .Ltmp5
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     bgeu	a0, a0, .Ltmp6
# CHECK-NEXT:  -      -     0.50   0.50    -      -      -      -     add	a0, a0, a0
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     lb	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     lbu	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     lh	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     lhu	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     lw	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     lwu	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     ld	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     sb	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     sh	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     sw	t0, 0(a0)
# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     sd	t0, 0(a0)
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     csrrw	t0, 4095, t1
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     csrrs	s3, fflags, s5
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     csrrc	sp, 0, ra
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     csrrwi	a5, 0, 0
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     csrrsi	t2, 4095, 31
# CHECK-NEXT:  -      -      -     1.00    -      -      -      -     csrrci	t1, sscratch, 5