# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s # Simple integer reductions: varies by LMUL vsetvli zero, zero, e32, m1, tu, mu vredsum.vs v5, v7, v8 vsetvli zero, zero, e32, m2, tu, mu vredsum.vs v5, v7, v8 vsetvli zero, zero, e32, m4, tu, mu vredsum.vs v5, v7, v8 vsetvli zero, zero, e32, m8, tu, mu vredsum.vs v5, v7, v8 # Advanced integer reductions: varies by LMUL and SEW vsetvli zero, zero, e16, m1, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e16, m2, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e16, m4, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e16, m8, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m1, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m2, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m4, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m8, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m1, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m2, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m4, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m8, tu, mu vredmin.vs v5, v7, v8 vredmax.vs v5, v7, v8 # Simple floating point reductions: varies by LMUL and SEW vsetvli zero, zero, e16, m1, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e16, m2, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e16, m4, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e16, m8, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e32, m1, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e32, m2, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e32, m4, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e32, m8, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e64, m1, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e64, m2, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e64, m4, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 vsetvli zero, zero, e64, m8, tu, mu vfredusum.vs v5, v7, v8 vfredosum.vs v5, v7, v8 # Advanced floating point reductions: varies by LMUL and SEW vsetvli zero, zero, e16, m1, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e16, m2, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e16, m4, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e16, m8, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m1, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m2, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m4, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e32, m8, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m1, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m2, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m4, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 vsetvli zero, zero, e64, m8, tu, mu vfredmin.vs v5, v7, v8 vfredmax.vs v5, v7, v8 # CHECK: Resources: # CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB # CHECK-NEXT: [1] - AscalonFPA:1 # CHECK-NEXT: [2] - AscalonFPB:1 # CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD # CHECK-NEXT: [4] - AscalonFXA:1 # CHECK-NEXT: [5] - AscalonFXB:1 # CHECK-NEXT: [6] - AscalonFXC:2 # CHECK-NEXT: [7] - AscalonFXD:2 # CHECK-NEXT: [8] - AscalonLS:3 # CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB # CHECK-NEXT: [10] - AscalonVA:1 # CHECK-NEXT: [11] - AscalonVB:1 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [7]: Bypass Latency # CHECK-NEXT: [8]: Resources ( | [] | [,