# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-x -instruction-tables=full -iterations=1 < %s | FileCheck %s

vsetvli zero, zero, e32, m1, ta, ma

vsll.vv v1, v2, v5
vsll.vx v1, v2, t0
vsll.vi v1, v2, 7

vsrl.vv v1, v2, v5
vsrl.vx v1, v2, t0
vsrl.vi v1, v2, 7

vsra.vv v1, v2, v5
vsra.vx v1, v2, t0
vsra.vi v1, v2, 7

vsetvli zero, zero, e32, mf4, ta, ma

vsll.vv v1, v2, v5
vsll.vx v1, v2, t0
vsll.vi v1, v2, 7

vsrl.vv v1, v2, v5
vsrl.vx v1, v2, t0
vsrl.vi v1, v2, 7

vsra.vv v1, v2, v5
vsra.vx v1, v2, t0
vsra.vi v1, v2, 7

vsetvli zero, zero, e32, m8, ta, ma

vmul.vv v1, v2, v5
vmul.vx v1, v2, t1

vmadd.vv v1, v2, v5
vmadd.vx v1, t1, v2

# CHECK:      Resources:
# CHECK-NEXT: [0]   - AscalonFP:2 AscalonFPA, AscalonFPB
# CHECK-NEXT: [1]   - AscalonFPA:1
# CHECK-NEXT: [2]   - AscalonFPB:1
# CHECK-NEXT: [3]   - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
# CHECK-NEXT: [4]   - AscalonFXA:1
# CHECK-NEXT: [5]   - AscalonFXB:1
# CHECK-NEXT: [6]   - AscalonFXC:2
# CHECK-NEXT: [7]   - AscalonFXD:2
# CHECK-NEXT: [8]   - AscalonLS:3
# CHECK-NEXT: [9]   - AscalonV:2  AscalonVA, AscalonVB
# CHECK-NEXT: [10]  - AscalonVA:1
# CHECK-NEXT: [11]  - AscalonVB:1

# CHECK:      Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK-NEXT: [7]: Bypass Latency
# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
# CHECK-NEXT: [9]: LLVM Opcode Name

# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]                                        [9]                        Instructions:
# CHECK-NEXT:  1      1     0.50                  U      0     AscalonV                                   VSETVLI                    vsetvli	zero, zero, e32, m1, ta, ma
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSLL_VV                    vsll.vv	v1, v2, v5
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSLL_VX                    vsll.vx	v1, v2, t0
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSLL_VI                    vsll.vi	v1, v2, 7
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRL_VV                    vsrl.vv	v1, v2, v5
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRL_VX                    vsrl.vx	v1, v2, t0
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRL_VI                    vsrl.vi	v1, v2, 7
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRA_VV                    vsra.vv	v1, v2, v5
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRA_VX                    vsra.vx	v1, v2, t0
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRA_VI                    vsra.vi	v1, v2, 7
# CHECK-NEXT:  1      1     0.50                  U      0     AscalonV                                   VSETVLI                    vsetvli	zero, zero, e32, mf4, ta, ma
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSLL_VV                    vsll.vv	v1, v2, v5
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSLL_VX                    vsll.vx	v1, v2, t0
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSLL_VI                    vsll.vi	v1, v2, 7
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRL_VV                    vsrl.vv	v1, v2, v5
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRL_VX                    vsrl.vx	v1, v2, t0
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRL_VI                    vsrl.vi	v1, v2, 7
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRA_VV                    vsra.vv	v1, v2, v5
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRA_VX                    vsra.vx	v1, v2, t0
# CHECK-NEXT:  1      1     0.50                         1     AscalonFX,AscalonV                         VSRA_VI                    vsra.vi	v1, v2, 7
# CHECK-NEXT:  1      1     0.50                  U      0     AscalonV                                   VSETVLI                    vsetvli	zero, zero, e32, m8, ta, ma
# CHECK-NEXT:  1      8     4.00                         8     AscalonFX,AscalonV[8]                      VMUL_VV                    vmul.vv	v1, v2, v5
# CHECK-NEXT:  1      8     4.00                         8     AscalonFX,AscalonV[8]                      VMUL_VX                    vmul.vx	v1, v2, t1
# CHECK-NEXT:  1      8     4.00                         8     AscalonFX,AscalonV[8]                      VMADD_VV                   vmadd.vv	v1, v2, v5
# CHECK-NEXT:  1      8     4.00                         8     AscalonFX,AscalonV[8]                      VMADD_VX                   vmadd.vx	v1, t1, v2

# CHECK:      Resources:
# CHECK-NEXT: [0]   - AscalonFPA
# CHECK-NEXT: [1]   - AscalonFPB
# CHECK-NEXT: [2]   - AscalonFXA
# CHECK-NEXT: [3]   - AscalonFXB
# CHECK-NEXT: [4.0] - AscalonFXC
# CHECK-NEXT: [4.1] - AscalonFXC
# CHECK-NEXT: [5.0] - AscalonFXD
# CHECK-NEXT: [5.1] - AscalonFXD
# CHECK-NEXT: [6.0] - AscalonLS
# CHECK-NEXT: [6.1] - AscalonLS
# CHECK-NEXT: [6.2] - AscalonLS
# CHECK-NEXT: [7]   - AscalonVA
# CHECK-NEXT: [8]   - AscalonVB

# CHECK:      Resource pressure per iteration:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4.0]  [4.1]  [5.0]  [5.1]  [6.0]  [6.1]  [6.2]  [7]    [8]
# CHECK-NEXT:  -      -     3.67   3.67   3.67   3.67   3.67   3.67    -      -      -     26.50  26.50

# CHECK:      Resource pressure by instruction:
# CHECK-NEXT: [0]    [1]    [2]    [3]    [4.0]  [4.1]  [5.0]  [5.1]  [6.0]  [6.1]  [6.2]  [7]    [8]    Instructions:
# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     0.50   0.50   vsetvli	zero, zero, e32, m1, ta, ma
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsll.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsll.vx	v1, v2, t0
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsll.vi	v1, v2, 7
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsrl.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsrl.vx	v1, v2, t0
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsrl.vi	v1, v2, 7
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsra.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsra.vx	v1, v2, t0
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsra.vi	v1, v2, 7
# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     0.50   0.50   vsetvli	zero, zero, e32, mf4, ta, ma
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsll.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsll.vx	v1, v2, t0
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsll.vi	v1, v2, 7
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsrl.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsrl.vx	v1, v2, t0
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsrl.vi	v1, v2, 7
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsra.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsra.vx	v1, v2, t0
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     0.50   0.50   vsra.vi	v1, v2, 7
# CHECK-NEXT:  -      -      -      -      -      -      -      -      -      -      -     0.50   0.50   vsetvli	zero, zero, e32, m8, ta, ma
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     4.00   4.00   vmul.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     4.00   4.00   vmul.vx	v1, v2, t1
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     4.00   4.00   vmadd.vv	v1, v2, v5
# CHECK-NEXT:  -      -     0.17   0.17   0.17   0.17   0.17   0.17    -      -      -     4.00   4.00   vmadd.vx	v1, t1, v2