# ######################################################################## # Copyright (C) 2025-2026 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: hipsparse_common.yaml Tests: - name: spmv_csr_bad_arg category: pre_checkin function: spmv_csr_bad_arg indextype: *i32_i64 precision: *single_double_precisions_complex_real - name: spmv_csr category: quick function: spmv_csr indextype: *i32_i64 precision: *single_double_precisions_complex_real M: [50] N: [84] alpha: [2.0] alphai: [0.5] beta: [1.0] betai: [0.5] transA: [HIPSPARSE_OPERATION_NON_TRANSPOSE] baseA: [HIPSPARSE_INDEX_BASE_ZERO, HIPSPARSE_INDEX_BASE_ONE] spmv_alg: [HIPSPARSE_SPMV_ALG_DEFAULT, HIPSPARSE_SPMV_CSR_ALG1, HIPSPARSE_SPMV_CSR_ALG2, HIPSPARSE_SPMV_CSR_ALG3] call_preprocess: [true, false] # Test transpose operations with default algorithm (tests fix for rocsparse fallback) - name: spmv_csr_transpose category: quick function: spmv_csr indextype: *i32_i64 precision: *single_double_precisions_complex_real M: [50] N: [84] alpha: [2.0] alphai: [1.0] beta: [1.0] betai: [1.0] transA: [HIPSPARSE_OPERATION_TRANSPOSE, HIPSPARSE_OPERATION_CONJUGATE_TRANSPOSE] baseA: [HIPSPARSE_INDEX_BASE_ZERO, HIPSPARSE_INDEX_BASE_ONE] spmv_alg: [HIPSPARSE_SPMV_ALG_DEFAULT, HIPSPARSE_SPMV_CSR_ALG3] call_preprocess: [true] - name: spmv_csr_mixed category: quick function: spmv_csr indextype: *i32_i64 precision: *spmv_mixed_precisions M: [50] N: [84] alpha: [2.0] alphai: [-0.5] beta: [1.0] betai: [0.75] transA: [HIPSPARSE_OPERATION_NON_TRANSPOSE] baseA: [HIPSPARSE_INDEX_BASE_ZERO, HIPSPARSE_INDEX_BASE_ONE] spmv_alg: [HIPSPARSE_SPMV_ALG_DEFAULT, HIPSPARSE_SPMV_CSR_ALG1, HIPSPARSE_SPMV_CSR_ALG2, HIPSPARSE_SPMV_CSR_ALG3] call_preprocess: [true] - name: spmv_csr category: pre_checkin function: spmv_csr indextype: *i32_i64 precision: *single_double_precisions_complex_real M: 1 N: 1 alpha: [2.0] alphai: [-0.5] beta: [1.0] betai: [-0.5] transA: [HIPSPARSE_OPERATION_NON_TRANSPOSE] baseA: [HIPSPARSE_INDEX_BASE_ZERO, HIPSPARSE_INDEX_BASE_ONE] spmv_alg: [HIPSPARSE_SPMV_ALG_DEFAULT, HIPSPARSE_SPMV_CSR_ALG1, HIPSPARSE_SPMV_CSR_ALG2, HIPSPARSE_SPMV_CSR_ALG3] filename: [nos1, nos2, nos3, nos4, nos5, nos6, nos7] call_preprocess: [true] - name: spmv_csr category: pre_checkin function: spmv_csr indextype: *i32 precision: *double_only_precisions M: 1 N: 1 alpha: [2.0] alphai: [0.0] beta: [1.0] betai: [0.0] transA: [HIPSPARSE_OPERATION_NON_TRANSPOSE] baseA: [HIPSPARSE_INDEX_BASE_ZERO] spmv_alg: [HIPSPARSE_SPMV_ALG_DEFAULT, HIPSPARSE_SPMV_CSR_ALG1, HIPSPARSE_SPMV_CSR_ALG2, HIPSPARSE_SPMV_CSR_ALG3] filename: [Chebyshev4, shipsec1, bibd_22_8, scircuit, rma10, sme3Dc, bmwcra_1, webbase-1M, ASIC_320k, mac_econ_fwd500, mc2depi] call_preprocess: [true]