# ######################################################################## # Copyright (C) 2021-2026 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: rocsparse_common.yaml Definitions: - &alpha_beta_range_quick - { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 } - { alpha: -0.5, beta: 0.5, alphai: -0.5, betai: 1.0 } - &alpha_beta_range_checkin - { alpha: 2.0, beta: 0.0, alphai: 1.5, betai: 0.5 } - { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 } - { alpha: 0.0, beta: 1.0, alphai: 0.0, betai: 0.0 } - &alpha_beta_range_1 - { alpha: 1.0, beta: 1.0, alphai: 1.0, betai: 1.0 } - &alpha_beta_range_nightly - { alpha: 2.0, beta: 0.67, alphai: 0.0, betai: 1.5 } - { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 } Tests: - name: bsrxmv_bad_arg category: pre_checkin function: bsrxmv_bad_arg precision: *single_double_precisions_complex_real - name: bsrxmv category: pre_checkin function: bsrxmv precision: *single_double_precisions_complex_real M: [8, 16] N: [8, 16] block_dim: [2, 5, 81] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row, rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: bsrxmv category: pre_checkin function: bsrxmv precision: *single_double_precisions M: [2, 16] N: [2, 16] block_dim: [2, 3, 4, 5, 8, 14, 16, 23, 81] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row, rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] # # For testing float specializations. # - name: bsrxmv category: pre_checkin function: bsrxmv precision: *single_precision M: [512] N: [512, 1024] block_dim: [5, 8] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row, rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: bsrxmv_file category: pre_checkin function: bsrxmv precision: *single_precision M: 1 N: 1 block_dim: [5, 8] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [scircuit, nos3, nos5, nos7] # # For code coverage # - name: bsrxmv category: pre_checkin function: bsrxmv precision: *single_double_precisions M: [512] N: [512, 1024] block_dim: [2, 3, 4] matrix_init_kind: [rocsparse_matrix_init_kind_tunedavg] alpha_beta: *alpha_beta_range_1 direction: [rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: bsrxmv category: pre_checkin function: bsrxmv precision: *single_double_precisions_complex_real M: [64] N: [64] block_dim: [17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32] alpha_beta: *alpha_beta_range_1 direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: bsrxmv_file category: pre_checkin function: bsrxmv precision: *single_double_precisions M: 1 N: 1 block_dim: [2, 15] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [scircuit, nos3, nos5, nos7] - name: bsrxmv_file category: pre_checkin function: bsrxmv precision: *single_double_precisions_complex M: 1 N: 1 block_dim: [7, 18] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [Chevron2] - name: bsrxmv category: quick function: bsrxmv precision: *single_double_precisions M: [10, 300] N: [33, 300] block_dim: [8, 28] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: bsrxmv category: quick function: bsrxmv precision: *single_double_precisions M: [10] N: [33] block_dim: [8] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_zero] - name: bsrxmv_file category: quick function: bsrxmv precision: *single_double_precisions M: 1 N: 1 block_dim: [9, 26] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [nos1, nos2] - name: bsrxmv_file category: quick function: bsrxmv precision: *single_only_precisions_complex M: 1 N: 1 block_dim: [19, 57] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [qc2534] - name: bsrxmv category: nightly function: bsrxmv precision: *single_double_precisions_complex_real M: [39385, 193482] N: [29348, 340123] block_dim: [4, 11, 20] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: bsrxmv_file category: nightly function: bsrxmv precision: *single_double_precisions M: 1 N: 1 block_dim: [2, 12] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [amazon0312, Chebyshev4, sme3Dc, shipsec1, webbase-1M] - name: bsrxmv_file category: nightly function: bsrxmv precision: *single_double_precisions_complex M: 1 N: 1 block_dim: [2, 13] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_column] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [Chevron3] - name: bsrxmv_graph_test category: pre_checkin function: bsrxmv precision: *single_double_precisions_complex_real M: [10, 500] N: [33, 842] block_dim: [2, 8, 28, 174] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_row] transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] graph_test: true