# ######################################################################## # Copyright (C) 2019-2025 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: rocsparse_common.yaml Definitions: - &alpha_beta_range_quick - { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 } - { alpha: -0.5, beta: 0.5, alphai: -0.5, betai: 1.0 } - &alpha_beta_range_checkin - { alpha: 2.0, beta: 0.0, alphai: 1.5, betai: 0.5 } - { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 } - { alpha: 3.0, beta: 1.0, alphai: 2.0, betai: -0.5 } - &alpha_beta_range_nightly - { alpha: 0.0, beta: 0.0, alphai: 1.5, betai: 0.5 } - { alpha: 2.0, beta: 0.67, alphai: 0.0, betai: 1.5 } - { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 } - { alpha: -1.0, beta: -0.5, alphai: 0.0, betai: 0.0 } Tests: - name: csrmv_managed_bad_arg category: pre_checkin function: csrmv_managed_bad_arg precision: *single_double_precisions_complex_real - name: csrmv_managed category: quick function: csrmv_managed precision: *single_double_precisions M: [10, 300] N: [33, 300] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] - name: csrmv_managed category: pre_checkin function: csrmv_managed precision: *single_double_precisions_complex_real M: [8, 2000] N: [8, 2000] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] - name: csrmv_managed category: nightly function: csrmv_managed precision: *single_double_precisions_complex_real M: [5000] N: [5000] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] - name: csrmv_managed_file category: quick function: csrmv_managed precision: *single_double_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] filename: [mac_econ_fwd500, nos2, nos4, nos6, scircuit] - name: csrmv_managed_file category: pre_checkin function: csrmv_managed precision: *single_double_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] filename: [nos1, nos3, nos5, nos7] - name: csrmv_managed_file category: nightly function: csrmv_managed precision: *single_double_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] filename: [bibd_22_8, bmwcra_1, amazon0312, ASIC_320k, sme3Dc, shipsec1] - name: csrmv_managed_file category: quick function: csrmv_managed precision: *single_only_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] filename: [mplate, qc2534] - name: csrmv_managed_file category: pre_checkin function: csrmv_managed precision: *single_double_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] filename: [Chevron2] - name: csrmv_managed_file category: nightly function: csrmv_managed precision: *single_double_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] filename: [Chevron3] - name: csrmv_managed_graph_test category: pre_checkin function: csrmv_managed precision: *single_double_precisions_complex_real M: [10, 500] N: [33, 842] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_rowsplit] graph_test: true # Regression: csr_adaptive on managed (unified) memory over-read csr_row_ptr # past its m+1-length end for the last, partially-filled row block. Benign on # discrete GPUs but faults on unified-memory APUs (gfx1151); caught here on any # arch under ASAN. Row counts are chosen so the final adaptive row block holds # a non-power-of-two number of short rows. - name: csrmv_managed_adaptive_last_rowblock category: quick function: csrmv_managed precision: *single_double_precisions M: [3, 7, 15, 33, 300] N: [3, 7, 15, 33, 300] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero, rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmv_alg: [rocsparse_spmv_alg_csr_adaptive]