# ######################################################################## # Copyright (C) 2020-2026 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: rocsparse_common.yaml Definitions: - &alpha_beta_range_quick - { alpha: 1.0, beta: 1.0, alphai: 1.0, betai: 0.5 } - &alpha_beta_range_checkin - { alpha: 3.0, beta: 1.7, alphai: -0.5, betai: 0.8 } - &alpha_beta_range_nightly - { alpha: -0.5, beta: -0.2, alphai: 1.0, betai: 1.9 } Tests: - name: spgemm_csr_bad_arg category: pre_checkin function: spgemm_csr_bad_arg indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real # C = alpha * A * B - name: spgemm_mult_csr category: quick function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [300] N: [300] K: [254] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spgemm_alg: [rocsparse_spgemm_alg_default] - name: spgemm_mult_csr category: quick function: spgemm_csr indextype: *i32 precision: [*float16_float16_float32_float32_abct_precision, *bfloat16_bfloat16_float32_float32_abct_precision] M: [300] N: [300] K: [512] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spgemm_alg: [rocsparse_spgemm_alg_default] - name: spgemm_mult_csr category: pre_checkin function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [1799] N: [2000] K: [1942] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spgemm_alg: [rocsparse_spgemm_alg_default] - name: spgemm_mult_csr category: pre_checkin function: spgemm_csr indextype: *i32 precision: [*float16_float16_float32_float32_abct_precision, *bfloat16_bfloat16_float32_float32_abct_precision] M: [1024] N: [512, 1024] K: [1024] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spgemm_alg: [rocsparse_spgemm_alg_default] - name: spgemm_mult_csr category: nightly function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [73923, 842323] N: [5239, 1492312] K: [442, 743434] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spgemm_alg: [rocsparse_spgemm_alg_default] - name: spgemm_mult_csr_file category: quick function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions M: 1 N: [13, 300] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spgemm_alg: [rocsparse_spgemm_alg_default] filename: [mac_econ_fwd500, nos2, nos6, scircuit] - name: spgemm_mult_csr_file category: pre_checkin function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions M: 1 N: [8, 2000] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] baseB: [rocsparse_index_base_one] baseC: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spgemm_alg: [rocsparse_spgemm_alg_default] filename: [rma10, mc2depi, ASIC_320k, nos1, nos7] - name: spgemm_mult_csr_file category: nightly function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions M: 1 N: [5239, 1492312] K: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spgemm_alg: [rocsparse_spgemm_alg_default] filename: [bibd_22_8, bmwcra_1, amazon0312, Chebyshev4, sme3Dc, webbase-1M, shipsec1] - name: spgemm_mult_csr_file category: quick function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex M: 1 N: [21, 300] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] baseB: [rocsparse_index_base_one] baseC: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spgemm_alg: [rocsparse_spgemm_alg_default] filename: [qc2534, Chevron2] - name: spgemm_mult_csr_file category: pre_checkin function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex M: 1 N: [8, 2000] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spgemm_alg: [rocsparse_spgemm_alg_default] filename: [mplate, Chevron3] - name: spgemm_mult_csr_file category: nightly function: spgemm_csr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex M: 1 N: [4823, 901923] K: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] baseB: [rocsparse_index_base_zero] baseC: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spgemm_alg: [rocsparse_spgemm_alg_default] filename: [Chevron4]