# ######################################################################## # Copyright (C) 2020-2026 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: rocsparse_common.yaml Definitions: - &alpha_beta_range_quick - { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 } - &alpha_beta_range_checkin - { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 } - &alpha_beta_range_nightly - { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 } - { alpha: -1.0, beta: -0.5, alphai: 0.0, betai: 0.0 } - &alpha_beta_range_stress - { alpha: 1.0, beta: 0.0, alphai: 0.0, betai: 0.0 } Tests: - name: spmm_csr_bad_arg category: pre_checkin function: spmm_csr_bad_arg indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real # Default-algorithm auto-selection. Drives the full buffer_size -> preprocess -> # compute pipeline on an extremely row-skewed and an extremely uniform matrix and # checks the default result against the analytic product and both explicit # load-balanced kernels. The test builds its own matrices, so it ignores the # index/precision below. - name: spmm_csr_extra category: quick function: spmm_csr_extra indextype: *i32 precision: *double_only_precisions ############################## # Quick ############################## - name: spmm_csr category: quick function: spmm_csr indextype: *i32 precision: *double_only_precisions M: [300] N: [72] K: [2345] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_row] - name: spmm_csr category: quick function: spmm_csr indextype: *i64 precision: *single_double_precisions_complex_real M: [300] N: [300] K: [223] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_transpose] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_row] - name: spmm_csr_file category: quick function: spmm_csr indextype: *i64i32 precision: *double_only_precisions M: 1 N: [64] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_transpose] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_column] orderC: [rocsparse_order_row] filename: [nos3] - name: spmm_csr_file category: quick function: spmm_csr indextype: *i32 precision: *single_double_precisions M: 1 N: [256] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] filename: [nos1, nos7] - name: spmm_csr_file category: quick function: spmm_csr indextype: *i64 precision: *single_double_precisions M: 1 N: [128] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] filename: [nos3] - name: spmm_csr_file category: quick function: spmm_csr indextype: *i32_i64 precision: *double_only_precisions M: 1 N: [42] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] filename: [nos2, nos6] - name: spmm_csr_file category: quick function: spmm_csr indextype: *i64i32 precision: *single_double_precisions_complex M: 1 N: [19] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_row] filename: [mplate] - name: spmm_csr category: quick function: spmm_csr indextype: *i32_i64 precision: *int8_int8_int32_int32_abct_precision M: [300] N: [214] K: [573] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] rand_gen_min: -128.0 rand_gen_max: 127.0 convert_to_int: true - name: spmm_csr category: quick function: spmm_csr indextype: *i32 precision: *int8_int8_float32_float32_abct_precision M: [300] N: [210] K: [457] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none, rocsparse_operation_transpose] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] rand_gen_min: -128.0 rand_gen_max: 127.0 convert_to_int: true - name: spmm_csr category: quick function: spmm_csr indextype: *i64 precision: *float16_float16_float32_float32_abct_precision M: [300] N: [23, 24] K: [4860] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] - name: spmm_csr category: quick function: spmm_csr indextype: *i32 precision: [*float16_float16_float32_float32_abct_precision, *bfloat16_bfloat16_float32_float32_abct_precision] M: [300] N: [16, 32] K: [512] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split, rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] # Float16 input/output precision tests (A=f16, B=f16, C=f16, compute=f32) - name: spmm_csr category: quick function: spmm_csr indextype: *i32 precision: [*float16_float16_float16_float32_abct_precision, *bfloat16_bfloat16_bfloat16_float32_abct_precision] M: [300] N: [16, 32] K: [512] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split, rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] ############################## # Precheckin ############################## - name: spmm_csr category: pre_checkin function: spmm_csr indextype: *i64 precision: *single_double_precisions M: [2000] N: [1, 2] K: [14293] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] - name: spmm_csr category: pre_checkin function: spmm_csr indextype: *i64i32 precision: *single_double_precisions M: [2000] N: [1, 2] K: [8475] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] - name: spmm_csr category: pre_checkin function: spmm_csr indextype: *i32 precision: *single_double_precisions M: [311] N: [60, 441] K: [82] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split, rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_row, rocsparse_order_column] orderC: [rocsparse_order_column] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i32_i64 precision: *double_only_precisions_complex M: 1 N: [16] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_transpose] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] filename: [mplate] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i64 precision: *double_only_precisions M: 1 N: [26, 27] K: 1 tolm: 4.0 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] filename: [bmwcra_1] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i64i32 precision: *single_double_precisions_complex M: 1 N: [29, 30] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] filename: [qc2534] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i64i32 precision: *single_double_precisions M: 1 N: [9] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_row_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] filename: [amazon0312] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i64i32 precision: *double_only_precisions M: 1 N: [47, 58] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] filename: [mac_econ_fwd500] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i64i32 precision: *single_double_precisions_complex M: 1 N: [4, 60] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] filename: [Chevron2] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i32_i64 precision: *double_only_precisions M: 1 N: [6] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] filename: [scircuit] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i64i32 precision: *double_only_precisions M: 1 N: [21] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] filename: [bibd_22_8] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i64i32 precision: *double_only_precisions_complex M: 1 N: [17] K: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] filename: [Chebyshev4] - name: spmm_csr_file category: pre_checkin function: spmm_csr indextype: *i32_i64 precision: *int8_int8_int32_int32_abct_precision M: 1 N: [64] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none, rocsparse_operation_transpose] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_row] filename: [nos3, nos4, nos5] rand_gen_min: -128.0 rand_gen_max: 127.0 convert_to_int: true - name: spmm_csr category: pre_checkin function: spmm_csr indextype: *i32 precision: *float16_float16_float32_float32_abct_precision M: [2000] N: [25, 56] K: [47586] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] - name: spmm_csr category: pre_checkin function: spmm_csr indextype: *i32 precision: *bfloat16_bfloat16_float32_float32_abct_precision M: [2000] N: [75] K: [23458] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] - name: spmm_csr category: pre_checkin function: spmm_csr indextype: *i32 precision: [*float16_float16_float32_float32_abct_precision, *bfloat16_bfloat16_float32_float32_abct_precision] M: [1024] N: [32, 64] K: [1024] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split, rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] - name: spmm_csr_graph_test category: pre_checkin function: spmm_csr indextype: *i32_i64 precision: *double_only_precisions M: [223, 485] N: [53, 54] K: [223, 485, 647] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none, rocsparse_operation_transpose] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_column] orderC: [rocsparse_order_row] graph_test: true ############################## # Nightly ############################## - name: spmm_csr category: nightly function: spmm_csr indextype: *i32_i64 precision: *single_double_precisions_complex_real M: [431] N: [48, 49] K: [97] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] - name: spmm_csr_file category: nightly function: spmm_csr indextype: *i64i32 precision: *double_only_precisions M: 1 N: [14] K: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_column, rocsparse_order_row] orderC: [rocsparse_order_row] filename: [sme3Dc] # Fails from rounding. Need to investigate better ways to quantify rounding errors and hoipefully add back later # - name: spmm_csr_file # category: nightly # function: spmm_csr # indextype: *i32_i64 # precision: *double_only_precisions # M: 1 # N: [48] # K: 1 # alpha_beta: *alpha_beta_range_nightly # transA: [rocsparse_operation_none] # transB: [rocsparse_operation_none] # baseA: [rocsparse_index_base_one] # matrix: [rocsparse_matrix_file_rocalution] # spmm_alg: [rocsparse_spmm_alg_csr] # orderB: [rocsparse_order_row] # orderC: [rocsparse_order_column] # filename: [shipsec1] - name: spmm_csr_file category: nightly function: spmm_csr indextype: *i32_i64 precision: *double_only_precisions M: 1 N: [45, 46] K: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] filename: [webbase-1M] - name: spmm_csr_file category: nightly function: spmm_csr indextype: *i32_i64 precision: *double_only_precisions M: 1 N: [21] K: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_nnz_split, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_row] orderC: [rocsparse_order_column] filename: [ASIC_320k] - name: spmm_csr_file category: nightly function: spmm_csr indextype: *i32_i64 precision: *single_double_precisions_complex M: 1 N: [12] K: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_column] filename: [Chevron3, Chevron4] - name: spmm_csr_file category: nightly function: spmm_csr indextype: *i32_i64 precision: *single_double_precisions_complex M: 1 N: [5] K: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr, rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_column] orderC: [rocsparse_order_row] filename: [Chevron4] - name: spmm_csr_file category: nightly function: spmm_csr indextype: *i32_i64 precision: *double_only_precisions M: 1 N: [40, 41] K: 1 tolm: 5.0 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] filename: [mc2depi] - name: spmm_csr_file category: nightly function: spmm_csr indextype: *i64i32 precision: *int8_int8_float32_float32_abct_precision M: 1 N: [77] K: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none, rocsparse_operation_transpose] transB: [rocsparse_operation_none, rocsparse_operation_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] filename: [Chevron2] rand_gen_min: -128.0 rand_gen_max: 127.0 convert_to_int: true - name: spmm_csr category: nightly function: spmm_csr indextype: *i32 precision: *float16_float16_float32_float32_abct_precision M: [8538] N: [19, 49] K: [54678] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] spmm_alg: [rocsparse_spmm_alg_csr_merge_path] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] ############################## # STRESS ############################## - name: spmm_csr category: stress hardware: [gfx90a] function: spmm_csr indextype: *i32 precision: *single_only_precisions M: [30000000] N: [2] K: [300000000] alpha_beta: *alpha_beta_range_stress transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_tridiagonal] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row] host_memory_gb: 16 device_memory_gb: 16 - name: spmm_csr_file category: stress hardware: [gfx90a] function: spmm_csr indextype: *i32 precision: *double_only_precisions M: 1 N: [2] K: 1 ld_multiplier_B: [9354] ld_multiplier_C: [7523] alpha_beta: *alpha_beta_range_stress transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_row, rocsparse_order_column] orderC: [rocsparse_order_row, rocsparse_order_column] filename: [sme3Dc, bmwcra_1] host_memory_gb: 32 device_memory_gb: 16 - name: spmm_csr_file category: stress hardware: [gfx90a] function: spmm_csr indextype: *i32 precision: *double_only_precisions M: 1 N: [2] K: 1 ld_multiplier_B: [9354] ld_multiplier_C: [7523] alpha_beta: *alpha_beta_range_stress transA: [rocsparse_operation_none] transB: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] spmm_alg: [rocsparse_spmm_alg_csr_row_split] orderB: [rocsparse_order_row] orderC: [rocsparse_order_row, rocsparse_order_column] filename: [shipsec1] host_memory_gb: 32 device_memory_gb: 16