# ######################################################################## # Copyright (C) 2022-2026 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: rocsparse_common.yaml Definitions: - &alpha_beta_range_quick - { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 } - &alpha_beta_range_checkin - { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 } - &alpha_beta_range_nightly - { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 } - { alpha: -1.0, beta: -0.5, alphai: 0.0, betai: 0.0 } Tests: # Quick - name: spmv_bsr category: quick function: spmv_bsr indextype: *i32 precision: *single_double_precisions M: [50] N: [50] block_dim: [2, 4] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: spmv_bsr_file category: quick function: spmv_bsr indextype: *i32 precision: *single_double_precisions block_dim: [5, 8] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [mac_econ_fwd500, nos2, nos4, nos6] - name: spmv_bsr_file category: quick function: spmv_bsr indextype: *i32 precision: *single_only_precisions_complex M: 1 N: 1 block_dim: [3, 5] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [Chevron2, qc2534] - name: spmv_bsr category: quick function: spmv_bsr indextype: *i32 precision: *float32_float64_float64_float64 M: [50] N: [50] block_dim: [6, 12] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: spmv_bsr category: quick function: spmv_bsr indextype: *i32 precision: *int8_int8_int32_int32_axyt_precision M: [50] N: [50] block_dim: [7, 9] alpha_beta: *alpha_beta_range_quick direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] # Pre-checkin - name: spmv_bsr_bad_arg category: pre_checkin function: spmv_bsr_bad_arg indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real - name: spmv_bsr category: pre_checkin function: spmv_bsr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [100] N: [100] block_dim: [3] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] call_stage_analysis: [false] - name: spmv_bsr_file category: pre_checkin function: spmv_bsr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions block_dim: [6] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [nos1, nos2, nos3, nos4, nos5, nos6, nos7] - name: spmv_bsr_file category: pre_checkin function: spmv_bsr indextype: *i32 precision: *single_double_precisions block_dim: [4] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [rma10, mc2depi, mac_econ_fwd500] - name: spmv_bsr_file category: pre_checkin function: spmv_bsr indextype: *i64 precision: *single_double_precisions block_dim: [5] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [ASIC_320k, bibd_22_8, Chebyshev4] - name: spmv_bsr_file category: pre_checkin function: spmv_bsr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex block_dim: [2] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [mplate, Chevron3] - name: spmv_bsr_graph_test category: pre_checkin function: spmv_bsr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [500] N: [842] block_dim: [8] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] graph_test: true call_stage_analysis: [false] - name: spmv_bsr category: pre_checkin function: spmv_bsr indextype: *i32_i64 precision: *float32_float64_float64_float64 M: [200] N: [578, 2000] block_dim: [16] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: spmv_bsr category: pre_checkin function: spmv_bsr indextype: *i32_i64 precision: *int8_int8_float32_float32_axyt_precision M: [200] N: [578, 2000] block_dim: [16] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: spmv_bsr category: pre_checkin function: spmv_bsr indextype: *i32_i64 precision: *float16_float16_float32_float32_axyt_precision M: [2000] N: [2000] block_dim: [8] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: spmv_bsr category: pre_checkin function: spmv_bsr indextype: *i32_i64 precision: [*float16_float16_float16_float32_axyt_precision, *bfloat16_bfloat16_bfloat16_float32_axyt_precision] M: [2000] N: [2000] block_dim: [4, 8, 16] alpha_beta: *alpha_beta_range_checkin direction: *all_rocsparse_direction baseA: *all_rocsparse_index_base matrix: [rocsparse_matrix_random] - name: spmv_bsr category: pre_checkin function: spmv_bsr indextype: *i32_i64 precision: *bfloat16_bfloat16_float32_float32_axyt_precision M: [2000] N: [2000] block_dim: [9] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: spmv_bsr_file category: pre_checkin function: spmv_bsr indextype: *i32_i64 precision: *float32_cmplx32_cmplx32_cmplx32_axyt_precision M: [2000] N: [2000] block_dim: [4] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: spmv_bsr_file category: pre_checkin function: spmv_bsr indextype: *i32_i64 precision: *cmplx32_cmplx64_cmplx64_cmplx64 M: [2000] N: [2000] block_dim: [4] alpha_beta: *alpha_beta_range_checkin direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] # Nightly - name: spmv_bsr category: nightly function: spmv_bsr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [39385, 639102] N: [29348, 710341] block_dim: [4] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: spmv_bsr_file category: nightly function: spmv_bsr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions block_dim: [5] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [bibd_22_8, bmwcra_1, amazon0312, Chebyshev4, sme3Dc, shipsec1, scircuit] - name: spmv_bsr_file category: nightly function: spmv_bsr indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex block_dim: [7] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_row] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [Chevron4] skip_hardware: gfx1151 - name: spmv_bsr_file category: nightly function: spmv_bsr indextype: *i32_i64 precision: *float64_cmplx64_cmplx64_cmplx64_axyt_precision M: 1 N: 1 block_dim: [7] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [Chevron3, bmwcra_1] - name: spmv_bsr_file category: nightly function: spmv_bsr indextype: *i32_i64 precision: *cmplx32_cmplx64_cmplx64_cmplx64 M: 1 N: 1 block_dim: [7] alpha_beta: *alpha_beta_range_nightly direction: [rocsparse_direction_column] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [Chevron3, bmwcra_1]