# ######################################################################## # Copyright (C) 2022-2025 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: rocsparse_common.yaml Definitions: - &alpha_beta_range_quick - { alpha: 1.0, beta: -1.0, alphai: 1.0, betai: -0.5 } - &alpha_beta_range_checkin - { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 } - &alpha_beta_range_half_checkin - { alpha: 0.0, beta: 1.0, alphai: 1.5, betai: 0.5 } - { alpha: 1.0, beta: 1.0, alphai: 2.0, betai: -0.5 } - &alpha_beta_range_nightly - { alpha: -0.5, beta: 0.5, alphai: 1.0, betai: -0.5 } - { alpha: -1.0, beta: -0.5, alphai: 0.0, betai: 0.0 } - &M_N_range_quick - { M: 12, N: 12 } - &M_N_range_checkin - { M: 0, N: 0 } - &M_N_range_nightly - { M: 10354, N: 10354 } - { M: 31057, N: 31057 } - { M: 38564, N: 38564 } - { M: 56748, N: 56748 } - { M: 237462, N: 237462 } - { M: 457294, N: 457294 } - { M: 692846, N: 692846 } - { M: 791842, N: 791842 } - { M: 823710, N: 823710 } - { M: 910387, N: 910387 } - { M: 1029843, N: 1029843 } Tests: - name: spmv_csc_bad_arg category: pre_checkin function: spmv_csc_bad_arg indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real # # Test rocsparse_spmv_alg_default dispatch: # - CSC format + default algo + none should use rowsplit internally # - CSC format + default algo + transpose/conjugate_transpose should use adaptive internally # - name: spmv_csc_default_alg category: quick function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [10, 500] N: [33, 842] alpha_beta: *alpha_beta_range_quick transA: *all_rocsparse_operation baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_default] - name: spmv_csc_default_alg category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [0, 7111] N: [0, 4441] alpha_beta: *alpha_beta_range_checkin transA: *all_rocsparse_operation baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_default] call_stage_analysis: [false, true] # # general matrix type # - name: spmv_csc category: quick function: spmv_csc indextype: *i32 precision: *single_double_precisions M: [10, 300] N: [33, 300] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [8, 2000] N: [8, 2000] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] call_stage_analysis: [false] - name: spmv_csc category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [39385, 639102] N: [29348, 710341] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc_file category: quick function: spmv_csc indextype: *i32 precision: *double_only_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [mac_econ_fwd500, nos2] - name: spmv_csc_file category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [rma10, mc2depi, ASIC_320k, nos1, nos3, nos5, nos7, bibd_22_8, Chebyshev4, mac_econ_fwd500] - name: spmv_csc_file category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] filename: [bibd_22_8, bmwcra_1, amazon0312, Chebyshev4, sme3Dc, shipsec1, scircuit] - name: spmv_csc_file category: quick function: spmv_csc indextype: *i32 precision: *single_only_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [Chevron2, qc2534] - name: spmv_csc_file category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_conjugate_transpose] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] filename: [mplate, Chevron3] - name: spmv_csc_file category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [Chevron4] - name: spmv_csc_graph_test category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M: [500] N: [842] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] graph_test: true # # symmetric and triangular matrix type # - name: spmv_csc category: quick hardware: [gfx900, gfx906, gfx908, gfx90a, gfx1030] function: spmv_csc indextype: *i32 precision: *single_double_precisions M_N: *M_N_range_quick alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_lower] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc category: quick hardware: [gfx940] function: spmv_csc indextype: *i32 precision: *single_double_precisions M_N: *M_N_range_quick alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_lower] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M_N: *M_N_range_checkin alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_upper] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] call_stage_analysis: [false] - name: spmv_csc category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex_real M_N: *M_N_range_nightly alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_upper] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc_file category: quick function: spmv_csc indextype: *i32 precision: *double_only_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_lower] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [mac_econ_fwd500, nos2, nos4, nos6] - name: spmv_csc_file category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *double_only_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_lower] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [rma10, mc2depi, nos1, nos3, nos5, nos7] - name: spmv_csc_file category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *double_only_precisions M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_transpose] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_lower] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] filename: [bmwcra_1, amazon0312, Chebyshev4, sme3Dc, shipsec1, scircuit] - name: spmv_csc_file category: quick function: spmv_csc indextype: *i32 precision: *single_only_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_lower] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [Chevron2, qc2534] - name: spmv_csc_file category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *double_only_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_upper] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] filename: [mplate, Chevron3] - name: spmv_csc_file category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *single_double_precisions_complex M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_symmetric] uplo: [rocsparse_fill_mode_lower] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [Chevron4] # # mixed precision # - name: spmv_csc_file category: quick function: spmv_csc indextype: *i32 precision: *float32_float64_float64_float64 M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] filename: [bmwcra_1, amazon0312, sme3Dc] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *float32_float64_float64_float64 M: [34, 104] N: [57, 109] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc_file category: quick function: spmv_csc indextype: *i32 precision: *int8_int8_int32_int32_axyt_precision M: 1 N: 1 alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] filename: [bmwcra_1, amazon0312, sme3Dc] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *int8_int8_float32_float32_axyt_precision M: [34, 104] N: [57, 109] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *float16_float16_float32_float32_axyt_precision M: [22, 196] N: [45, 425] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: [*float16_float16_float16_float32_axyt_precision, *bfloat16_bfloat16_bfloat16_float32_axyt_precision] M: [22, 100] N: [45, 100] alpha_beta: *alpha_beta_range_half_checkin transA: [rocsparse_operation_none] baseA: *all_rocsparse_index_base matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_lrb, rocsparse_spmv_alg_csr_rowsplit] - name: spmv_csc category: quick function: spmv_csc indextype: *i32 precision: *bfloat16_bfloat16_float32_float32_axyt_precision M: [33, 178] N: [31, 235] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit, rocsparse_spmv_alg_csr_adaptive, rocsparse_spmv_alg_csr_lrb] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *cmplx32_cmplx64_cmplx64_cmplx64 M: [16, 78] N: [16, 93] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] - name: spmv_csc_file category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *cmplx32_cmplx64_cmplx64_cmplx64 M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [Chebyshev4, shipsec1] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *float32_cmplx32_cmplx32_cmplx32_axyt_precision M: [16, 78] N: [16, 93] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] - name: spmv_csc category: pre_checkin function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *float64_cmplx64_cmplx64_cmplx64_axyt_precision M: [2000] N: [2000] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_rowsplit] - name: spmv_csc_file category: nightly function: spmv_csc indextype: *i32i32_i64i32_i64i64 precision: *float64_cmplx64_cmplx64_cmplx64_axyt_precision M: 1 N: 1 alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] matrix_type: [rocsparse_matrix_type_general] spmv_alg: [rocsparse_spmv_alg_csr_adaptive] filename: [Chebyshev4, shipsec1]