# ######################################################################## # Copyright (C) 2025 Advanced Micro Devices, Inc. All rights Reserved. # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to deal # in the Software without restriction, including without limitation the rights # to use, copy, modify, merge, publish, distribute, sublicense, and/or sell # copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER # LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN # THE SOFTWARE. # # ######################################################################## --- include: rocsparse_common.yaml Definitions: - &alpha_beta_range_quick - { alpha: 1.1, beta: -1.5, alphai: 0.87, betai: -0.75 } - &alpha_beta_range_checkin - { alpha: 0.0, beta: -2.0, alphai: 0.0, betai: 0.65 } - &alpha_beta_range_nightly - { alpha: 0.5, beta: 0.7, alphai: -1.5, betai: 0.0 } - { alpha: 1.0, beta: 0.0, alphai: 1.0, betai: 1.0 } Tests: - name: v2_spmv_sell_bad_arg category: pre_checkin function: v2_spmv_sell_bad_arg indextype: *i32_i64 precision: *single_double_precisions_complex_real - name: v2_spmv_sell category: quick function: v2_spmv_sell indextype: *i32 precision: *single_double_precisions_complex_real M: [300] N: [300] sell_slice_size: [7] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_zero] - name: v2_spmv_sell category: quick function: v2_spmv_sell indextype: *i32_i64 precision: *single_double_precisions_complex_real M: [87, 243] N: [143, 257] sell_slice_size: [5] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: v2_spmv_sell_file category: quick function: v2_spmv_sell indextype: *i32_i64 precision: *double_only_precisions M: 1 N: 1 sell_slice_size: [2] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] filename: [qc2534, nos2] - name: v2_spmv_sell category: pre_checkin function: v2_spmv_sell indextype: *i32_i64 precision: *single_double_precisions_complex_real M: [2000] N: [2000] sell_slice_size: [8] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_random] - name: v2_spmv_sell_file category: pre_checkin function: v2_spmv_sell indextype: *i32_i64 precision: *double_only_precisions_complex M: 1 N: 1 sell_slice_size: [12] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [Chevron2, Chevron3, Chevron4, Chebyshev4, mplate] - name: v2_spmv_sell category: nightly function: v2_spmv_sell indextype: *i32_i64 precision: *single_double_precisions_complex_real M: [5467] N: [6514] sell_slice_size: [9, 10, 11] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: v2_spmv_sell_file category: nightly function: v2_spmv_sell indextype: *i32_i64 precision: *double_only_precisions M: 1 N: 1 sell_slice_size: [2, 5, 7] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_one] matrix: [rocsparse_matrix_file_rocalution] rand_gen_min: 0.0 rand_gen_max: 100.0 convert_to_int: true filename: [mac_econ_fwd500, bmwcra_1, scircuit, amazon0312, sme3Dc, shipsec1, webbase-1M, Chebyshev4, ASIC_320k, bibd_22_8, rma10] # Coverage gap tests: transpose with large slice sizes (develop vs reduced_ci) - name: v2_spmv_sell_transpose category: pre_checkin function: v2_spmv_sell indextype: *i32 precision: *single_double_precisions_complex_real M: [500] N: [500] sell_slice_size: [64, 256] alpha_beta: *alpha_beta_range_checkin transA: [rocsparse_operation_transpose, rocsparse_operation_conjugate_transpose] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] - name: v2_spmv_sell_graph_test category: pre_checkin function: v2_spmv_sell indextype: *i32_i64 precision: *single_double_precisions_complex_real M: [2000] N: [2000] sell_slice_size: [6] alpha_beta: *alpha_beta_range_quick transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_random] graph_test: true call_stage_analysis: [false] - name: v2_spmv_sell_file category: nightly function: v2_spmv_sell indextype: *i32 precision: *double_only_precisions M: 1 N: 1 sell_slice_size: [56, 89, 238, 756] alpha_beta: *alpha_beta_range_nightly transA: [rocsparse_operation_none] baseA: [rocsparse_index_base_zero] matrix: [rocsparse_matrix_file_rocalution] filename: [scircuit, amazon0312, webbase-1M, Chebyshev4]