/* * Copyright (c) Advanced Micro Devices, Inc., or its affiliates. * * SPDX-License-Identifier: MIT */ #include "arithmetic_common.hh" #include "atomicCAS_negative_kernels_rtc.hh" #include /** * @addtogroup atomicCAS atomicCAS * @{ * @ingroup AtomicsTest */ // Helper function to run atomicCAS tests (single kernel) template static void runAtomicCASTest() { int warp_size = 0; HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); const auto cache_line_size = 128u; for (auto current = 0; current < cmd_options.iterations; ++current) { DYNAMIC_SECTION("Same address " << current) { SingleDeviceSingleKernelTest(1, sizeof(TestType)); } DYNAMIC_SECTION("Adjacent addresses " << current) { SingleDeviceSingleKernelTest(warp_size, sizeof(TestType)); } DYNAMIC_SECTION("Scattered addresses " << current) { SingleDeviceSingleKernelTest(warp_size, cache_line_size); } } } // Helper function to run atomicCAS tests (multiple kernels) template static void runAtomicCASMultiKernelTest() { int warp_size = 0; HIP_CHECK(hipDeviceGetAttribute(&warp_size, hipDeviceAttributeWarpSize, 0)); const auto cache_line_size = 128u; for (auto current = 0; current < cmd_options.iterations; ++current) { DYNAMIC_SECTION("Same address " << current) { SingleDeviceMultipleKernelTest(2, 1, sizeof(TestType)); } DYNAMIC_SECTION("Adjacent addresses " << current) { SingleDeviceMultipleKernelTest(2, warp_size, sizeof(TestType)); } DYNAMIC_SECTION("Scattered addresses " << current) { SingleDeviceMultipleKernelTest(2, warp_size, cache_line_size); } } } /** * Test Description * ------------------------ * - Executes a single kernel on a single device wherein all threads will perform an atomic * addition, implemented using an atomic CAS operation, on a target memory location. Each thread * will add the same value to the memory location, storing the return value into a separate output * array slot corresponding to it. Once complete, the output array and target memory is validated to * contain all the expected values. Several memory access patterns are tested: * -# All threads exchange to a single, compile time deducible, memory location * -# Each thread targets an array containing warp_size elements, using tid % warp_size * for indexing * -# Same as the above, but the elements are spread out by L1 cache line size bytes. * * - The test is run for: * - All overloads of atomicCAS * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory * - Shared memory * - Several grid and block dimension combinations (only one block is used for shared memory). * Test source * ------------------------ * - unit/atomics/atomicCAS.cc * Test requirements * ------------------------ * - HIP_VERSION >= 5.2 */ HIP_TEST_CASE(Unit_atomicCAS_Positive) { SECTION("int") { runAtomicCASTest(); } SECTION("unsigned int") { runAtomicCASTest(); } SECTION("unsigned long long") { runAtomicCASTest(); } SECTION("unsigned short int") { runAtomicCASTest(); } #ifndef HT_NVIDIA SECTION("float") { runAtomicCASTest(); } SECTION("double") { runAtomicCASTest(); } #endif } /** * Test Description * ------------------------ * - Executes a kernel two times concurrently on a single device wherein all threads will perform * an atomic addition, implemented using an atomic CAS operation, on a target memory location. Each * thread will add the same value to the memory location, storing the return value into a separate * output array slot corresponding to it. Once complete, the output array and target memory is * validated to contain all the expected values. Several memory access patterns are tested: * -# All threads exchange to a single, compile time deducible, memory location * -# Each thread targets an array containing warp_size elements, using tid % warp_size * for indexing * -# Same as the above, but the elements are spread out by L1 cache line size bytes. * * - The test is run for: * - All overloads of atomicCAS * - hipMalloc, hipMallocManaged, hipHostMalloc and hipHostRegister allocated memory * - Several grid and block dimension combinations. * Test source * ------------------------ * - unit/atomics/atomicCAS.cc * Test requirements * ------------------------ * - HIP_VERSION >= 5.2 */ HIP_TEST_CASE(Unit_atomicCAS_Positive_Multi_Kernel) { SECTION("int") { runAtomicCASMultiKernelTest(); } SECTION("unsigned int") { runAtomicCASMultiKernelTest(); } SECTION("unsigned long long") { runAtomicCASMultiKernelTest(); } SECTION("unsigned short int") { runAtomicCASMultiKernelTest(); } #ifndef HT_NVIDIA SECTION("float") { runAtomicCASMultiKernelTest(); } SECTION("double") { runAtomicCASMultiKernelTest(); } #endif } /** * Test Description * ------------------------ * - RTCs kernels that pass combinations of arguments of invalid types for all overloads of * atomicCAS. * Test source * ------------------------ * - unit/atomics/atomicCAS.cc * Test requirements * ------------------------ * - HIP_VERSION >= 5.2 */ HIP_TEST_CASE(Unit_atomicCAS_Negative_Parameters_RTC) { hiprtcProgram program{}; const auto program_source = GENERATE(kAtomicCAS_int, kAtomicCAS_uint, kAtomicCAS_ulong, kAtomicCAS_ulonglong, kAtomicCAS_float, kAtomicCAS_double); HIPRTC_CHECK( hiprtcCreateProgram(&program, program_source, "atomicCAS_negative.cc", 0, nullptr, nullptr)); hiprtcResult result{hiprtcCompileProgram(program, 0, nullptr)}; // Get the compile log and count compiler error messages size_t log_size{}; HIPRTC_CHECK(hiprtcGetProgramLogSize(program, &log_size)); std::string log(log_size, ' '); HIPRTC_CHECK(hiprtcGetProgramLog(program, log.data())); int error_count{0}; int expected_error_count{8}; std::string error_message{"error:"}; size_t n_pos = log.find(error_message, 0); while (n_pos != std::string::npos) { ++error_count; n_pos = log.find(error_message, n_pos + 1); } HIPRTC_CHECK(hiprtcDestroyProgram(&program)); HIPRTC_CHECK_ERROR(result, HIPRTC_ERROR_COMPILATION); REQUIRE(error_count == expected_error_count); } /** * End doxygen group AtomicsTest. * @} */