Copyright (c) 2024 Advanced Micro Devices, Inc., or its affiliates. AMD Public Use. MIT 2024-05-02 1.0.0 AMD RDNA 1 5 ENC_SOP1 32 11111111100000001111111100000000 10111110100000000000001100000000 10111110100000000000010000000000 10111110100000000000010100000000 10111110100000000000011000000000 10111110100000000000011100000000 10111110100000000000100000000000 10111110100000000000100100000000 10111110100000000000101000000000 10111110100000000000101100000000 10111110100000000000110000000000 10111110100000000000110100000000 10111110100000000000111000000000 10111110100000000000111100000000 10111110100000000001000000000000 10111110100000000001000100000000 10111110100000000001001000000000 10111110100000000001001100000000 10111110100000000001010000000000 10111110100000000001010100000000 10111110100000000001011000000000 10111110100000000001011100000000 10111110100000000001100000000000 10111110100000000001100100000000 10111110100000000001101000000000 10111110100000000001101100000000 10111110100000000001110000000000 10111110100000000001110100000000 10111110100000000001111000000000 10111110100000000001111100000000 10111110100000000010000000000000 10111110100000000010000100000000 10111110100000000010001000000000 10111110100000000010010000000000 10111110100000000010010100000000 10111110100000000010011000000000 10111110100000000010011100000000 10111110100000000010100000000000 10111110100000000010100100000000 10111110100000000010101000000000 10111110100000000010101100000000 10111110100000000010110000000000 10111110100000000010110100000000 10111110100000000010111000000000 10111110100000000010111100000000 10111110100000000011000000000000 10111110100000000011000100000000 10111110100000000011010000000000 10111110100000000011011100000000 10111110100000000011100000000000 10111110100000000011100100000000 10111110100000000011101000000000 10111110100000000011101100000000 10111110100000000011110000000000 10111110100000000011110100000000 10111110100000000011111000000000 10111110100000000011111100000000 10111110100000000100000000000000 10111110100000000100000100000000 10111110100000000100001000000000 10111110100000000100001100000000 10111110100000000100010000000000 10111110100000000100010100000000 10111110100000000100011000000000 10111110100000000100011100000000 10111110100000000100100100000000 default != .fieldderef .fieldderef INST SOP1 SSRC0 I 32 255 I 32 U 1 Scalar ALU operations with one destination and one source. Allowed patterns: SOP1 (32 bits) SOP1 + LITERAL (64 bits) ENCODING Encoding. 9 23 OP Opcode. 8 8 SDST Destination for instruction. 7 16 SSRC0 Operand for instruction. 8 0 ENC_SOPC 32 11111111111111110000000000000000 10111111000000000000000000000000 10111111000000010000000000000000 10111111000000100000000000000000 10111111000000110000000000000000 10111111000001000000000000000000 10111111000001010000000000000000 10111111000001100000000000000000 10111111000001110000000000000000 10111111000010000000000000000000 10111111000010010000000000000000 10111111000010100000000000000000 10111111000010110000000000000000 10111111000011000000000000000000 10111111000011010000000000000000 10111111000011100000000000000000 10111111000011110000000000000000 10111111000100100000000000000000 10111111000100110000000000000000 default && != .fieldderef .fieldderef INST SOPC SSRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST SOPC SSRC1 I 32 255 I 32 U 1 U 1 Scalar ALU comparison operations with two sources. Allowed patterns: SOPC (32 bits) SOPC + LITERAL (64 bits) ENCODING Encoding. 9 23 OP Opcode. 7 16 SSRC0 First operand for instruction. 8 0 SSRC1 Second operand for instruction. 8 8 ENC_SOPP 32 11111111111111110000000000000000 10111111100000000000000000000000 10111111100000010000000000000000 10111111100000100000000000000000 10111111100000110000000000000000 10111111100001000000000000000000 10111111100001010000000000000000 10111111100001100000000000000000 10111111100001110000000000000000 10111111100010000000000000000000 10111111100010010000000000000000 10111111100010100000000000000000 10111111100010110000000000000000 10111111100011000000000000000000 10111111100011010000000000000000 10111111100011100000000000000000 10111111100011110000000000000000 10111111100100000000000000000000 10111111100100010000000000000000 10111111100100100000000000000000 10111111100100110000000000000000 10111111100101000000000000000000 10111111100101010000000000000000 10111111100101100000000000000000 10111111100101110000000000000000 10111111100110000000000000000000 10111111100110010000000000000000 10111111100110100000000000000000 10111111100110110000000000000000 10111111100111100000000000000000 10111111100111110000000000000000 10111111101000000000000000000000 10111111101000010000000000000000 10111111101000100000000000000000 10111111101000110000000000000000 10111111101001000000000000000000 10111111101001010000000000000000 10111111101010000000000000000000 default 1 U 1 Scalar ALU operations for control flow. Allowed patterns: SOPP (32 bits) SOPP + LITERAL (64 bits) ENCODING Encoding. 9 23 OP Opcode. 7 16 SIMM16 16-bit integer input for opcode. Signedness is determined by opcode. 16 0 ENC_SOPK 32 11111111100000000000000000000000 10110000000000000000000000000000 10110000100000000000000000000000 10110001000000000000000000000000 10110001100000000000000000000000 10110010000000000000000000000000 10110010100000000000000000000000 10110011000000000000000000000000 10110011100000000000000000000000 10110100000000000000000000000000 10110100100000000000000000000000 10110101000000000000000000000000 10110101100000000000000000000000 10110110000000000000000000000000 10110110100000000000000000000000 10110111000000000000000000000000 10110111100000000000000000000000 10111000000000000000000000000000 10111001000000000000000000000000 10111001100000000000000000000000 10111011000000000000000000000000 10111011100000000000000000000000 10111100000000000000000000000000 10111100100000000000000000000000 10111101000000000000000000000000 10111101100000000000000000000000 10111110000000000000000000000000 default 1 U 1 Scalar ALU operations with one destination and one 16-bit constant source. Allowed patterns: SOPK (32 bits) SOPK + LITERAL (64 bits) ENCODING Encoding. 4 28 OP Opcode. 5 23 SDST Destination for instruction. 7 16 SIMM16 16-bit integer input for opcode. Signedness is determined by opcode. 16 0 ENC_SOP2 32 11111111100000000000000000000000 10000000000000000000000000000000 10000000100000000000000000000000 10000001000000000000000000000000 10000001100000000000000000000000 10000010000000000000000000000000 10000010100000000000000000000000 10000011000000000000000000000000 10000011100000000000000000000000 10000100000000000000000000000000 10000100100000000000000000000000 10000101000000000000000000000000 10000101100000000000000000000000 10000111000000000000000000000000 10000111100000000000000000000000 10001000000000000000000000000000 10001000100000000000000000000000 10001001000000000000000000000000 10001001100000000000000000000000 10001010000000000000000000000000 10001010100000000000000000000000 10001011000000000000000000000000 10001011100000000000000000000000 10001100000000000000000000000000 10001100100000000000000000000000 10001101000000000000000000000000 10001101100000000000000000000000 10001110000000000000000000000000 10001110100000000000000000000000 10001111000000000000000000000000 10001111100000000000000000000000 10010000000000000000000000000000 10010000100000000000000000000000 10010001000000000000000000000000 10010001100000000000000000000000 10010010000000000000000000000000 10010010100000000000000000000000 10010011000000000000000000000000 10010011100000000000000000000000 10010100000000000000000000000000 10010100100000000000000000000000 10010101000000000000000000000000 10010110000000000000000000000000 10010111000000000000000000000000 10010111100000000000000000000000 10011000000000000000000000000000 10011000100000000000000000000000 10011001000000000000000000000000 10011001100000000000000000000000 10011010000000000000000000000000 10011010100000000000000000000000 10011011000000000000000000000000 default && != .fieldderef .fieldderef INST SOP2 SSRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST SOP2 SSRC1 I 32 255 I 32 U 1 U 1 Scalar ALU operations with one destination and two sources. Allowed patterns: SOP2 (32 bits) SOP2 + LITERAL (64 bits) ENCODING Encoding. 2 30 OP Opcode. 7 23 SDST Destination for instruction. 7 16 SSRC0 First operand for instruction. 8 0 SSRC1 Second operand for instruction. 8 8 ENC_SMEM 64 0000000000000000000000000000000011111111111111000000000000000000 0000000000000000000000000000000011110100000000000000000000000000 0000000000000000000000000000000011110100000001000000000000000000 0000000000000000000000000000000011110100000010000000000000000000 0000000000000000000000000000000011110100000011000000000000000000 0000000000000000000000000000000011110100000100000000000000000000 0000000000000000000000000000000011110100000101000000000000000000 0000000000000000000000000000000011110100000110000000000000000000 0000000000000000000000000000000011110100000111000000000000000000 0000000000000000000000000000000011110100001000000000000000000000 0000000000000000000000000000000011110100001001000000000000000000 0000000000000000000000000000000011110100001010000000000000000000 0000000000000000000000000000000011110100001011000000000000000000 0000000000000000000000000000000011110100001100000000000000000000 0000000000000000000000000000000011110100011111000000000000000000 0000000000000000000000000000000011110100100000000000000000000000 0000000000000000000000000000000011110100100100000000000000000000 0000000000000000000000000000000011110100100101000000000000000000 0000000000000000000000000000000011110100100110000000000000000000 0000000000000000000000000000000011110100100111000000000000000000 0000000000000000000000000000000011110100101010000000000000000000 default 1 U 1 Scalar memory operations. Examples: // Load some resource constants into SGPRs s_load_dwordx4 s[20:23], s[0:1], 0x0 // pos resource buffer s_load_dwordx4 s[24:27], s[0:1], 0x4 // color0 resource buffer s_load_dwordx4 s[28:31], s[0:1], 0x10 // tex0 resource buffer Different ways of writing an offset: s_load_dword s20, s[0:1], null // No offset applied s_load_dword s20, s[0:1], s4 // Register-based offset only s_load_dword s20, s[0:1], s4 offset:0x8 // Apply register and constant offsets To simplify porting older shader programs, instructions accepting a constant offset may either specify the offset as an operand (to match old architectures that did not allow for an SGPR offset) or they may use the offset: modifier. If a constant operand is used then the offset: modifier may not be used, and the instruction is translated to the current binary format as shown below: s_load_dword s20, s[0:1], 0x8 // Constant offset only, in operand s_load_dword s20, s[0:1], null offset:0x8 // Identical to above, using modifier, matches hardware The second example reflects the current binary encoding of the instruction. DLC If set, operation is L1-coherent (synced between WGPs in a shader engine). 1 14 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 16 OFFSET Specifies a 21-bit SIGNED BYTE offset aligned to one DWORD. 21 32 OP Opcode. 8 18 SBASE Bits [6:1] of an aligned pair of SGPRs specifying {size[16], base[48]}, where base and size are in dword units. The low-order bits are in the first SGPR. 6 0 1 0 SDATA Destination for instruction. 7 6 SOFFSET If not set to SQ_NULL: Specifies an SGPR address that supplies an UNSIGNED BYTE offset aligned to one DWORD for the memory operation (see enumeration). If set to SQ_NULL: not used in the address calculation. 7 57 ENC_VOP1 32 11111110000000011111111000000000 01111110000000000000000000000000 01111110000000000000001000000000 01111110000000000000010000000000 01111110000000000000011000000000 01111110000000000000100000000000 01111110000000000000101000000000 01111110000000000000110000000000 01111110000000000000111000000000 01111110000000000001000000000000 01111110000000000001010000000000 01111110000000000001011000000000 01111110000000000001100000000000 01111110000000000001101000000000 01111110000000000001110000000000 01111110000000000001111000000000 01111110000000000010000000000000 01111110000000000010001000000000 01111110000000000010010000000000 01111110000000000010011000000000 01111110000000000010100000000000 01111110000000000010101000000000 01111110000000000010110000000000 01111110000000000010111000000000 01111110000000000011000000000000 01111110000000000011001000000000 01111110000000000011010000000000 01111110000000000011011000000000 01111110000000000100000000000000 01111110000000000100001000000000 01111110000000000100010000000000 01111110000000000100011000000000 01111110000000000100100000000000 01111110000000000100101000000000 01111110000000000100111000000000 01111110000000000101010000000000 01111110000000000101011000000000 01111110000000000101110000000000 01111110000000000101111000000000 01111110000000000110001000000000 01111110000000000110011000000000 01111110000000000110100000000000 01111110000000000110101000000000 01111110000000000110110000000000 01111110000000000110111000000000 01111110000000000111000000000000 01111110000000000111001000000000 01111110000000000111010000000000 01111110000000000111011000000000 01111110000000000111100000000000 01111110000000000111101000000000 01111110000000000111110000000000 01111110000000000111111000000000 01111110000000001000000000000000 01111110000000001000001000000000 01111110000000001000010000000000 01111110000000001000011000000000 01111110000000001000100000000000 01111110000000001001000000000000 01111110000000001010000000000000 01111110000000001010001000000000 01111110000000001010010000000000 01111110000000001010011000000000 01111110000000001010100000000000 01111110000000001010101000000000 01111110000000001010110000000000 01111110000000001010111000000000 01111110000000001011000000000000 01111110000000001011001000000000 01111110000000001011010000000000 01111110000000001011011000000000 01111110000000001011100000000000 01111110000000001011101000000000 01111110000000001011110000000000 01111110000000001011111000000000 01111110000000001100000000000000 01111110000000001100001000000000 01111110000000001100010000000000 01111110000000001100011000000000 01111110000000001100100000000000 01111110000000001100101000000000 01111110000000001101000000000000 default && && && != .fieldderef .fieldderef INST VOP1 SRC0 I 32 250 I 32 U 1 && != .fieldderef .fieldderef INST VOP1 SRC0 I 32 233 I 32 U 1 != .fieldderef .fieldderef INST VOP1 SRC0 I 32 234 I 32 U 1 U 1 U 1 != .fieldderef .fieldderef INST VOP1 SRC0 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP1 SRC0 I 32 249 I 32 U 1 U 1 Vector ALU operations with one destination and one source. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Instructions in this encoding may use SDWA or DPP modes unless otherwise noted. Allowed patterns: VOP1 (32 bits) VOP1 + LITERAL (64 bits) VOP1 + SDWA (64 bits) VOP1 + DPP (64 bits) ENCODING Encoding. 7 25 OP Opcode. 8 9 SRC0 First operand for instruction. 9 0 VDST Destination for instruction. 8 17 ENC_VOPC 32 11111111111111100000000000000000 01111100000000000000000000000000 01111100000000100000000000000000 01111100000001000000000000000000 01111100000001100000000000000000 01111100000010000000000000000000 01111100000010100000000000000000 01111100000011000000000000000000 01111100000011100000000000000000 01111100000100000000000000000000 01111100000100100000000000000000 01111100000101000000000000000000 01111100000101100000000000000000 01111100000110000000000000000000 01111100000110100000000000000000 01111100000111000000000000000000 01111100000111100000000000000000 01111100001000000000000000000000 01111100001000100000000000000000 01111100001001000000000000000000 01111100001001100000000000000000 01111100001010000000000000000000 01111100001010100000000000000000 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01111101101000000000000000000000 01111101101000100000000000000000 01111101101001000000000000000000 01111101101001100000000000000000 01111101101010000000000000000000 01111101101010100000000000000000 01111101101011000000000000000000 01111101101011100000000000000000 01111101101100000000000000000000 01111101101100100000000000000000 01111101101101000000000000000000 01111101101101100000000000000000 01111101101110000000000000000000 01111101101110100000000000000000 01111101101111000000000000000000 01111101101111100000000000000000 01111101110000000000000000000000 01111101110000100000000000000000 01111101110001000000000000000000 01111101110001100000000000000000 01111101110010000000000000000000 01111101110010100000000000000000 01111101110011000000000000000000 01111101110011100000000000000000 01111101110100000000000000000000 01111101110100100000000000000000 01111101110101000000000000000000 01111101110101100000000000000000 01111101110110000000000000000000 01111101110110100000000000000000 01111101110111000000000000000000 01111101110111100000000000000000 01111101111000000000000000000000 01111101111000100000000000000000 01111101111001000000000000000000 01111101111001100000000000000000 01111101111010000000000000000000 01111101111010100000000000000000 01111101111011000000000000000000 01111101111011100000000000000000 01111101111100000000000000000000 01111101111100100000000000000000 01111101111101000000000000000000 01111101111101100000000000000000 01111101111110000000000000000000 01111101111110100000000000000000 01111101111111000000000000000000 01111101111111100000000000000000 default && && && != .fieldderef .fieldderef INST VOPC SRC0 I 32 250 I 32 U 1 && != .fieldderef .fieldderef INST VOPC SRC0 I 32 233 I 32 U 1 != .fieldderef .fieldderef INST VOPC SRC0 I 32 234 I 32 U 1 U 1 U 1 != .fieldderef .fieldderef INST VOPC SRC0 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOPC SRC0 I 32 249 I 32 U 1 U 1 Vector ALU comparison operations with two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Note that vector compare instructions respect the EXEC mask for computing the result in each thread; if EXEC[laneId] is zero, then the comparison for that thread is not performed and the result of VCC[laneId] is zero. SDWA is allowed but DPP is not allowed. Note when using SDWA format, the SDWA_SDST_ENC format must be used; this means the dst_sel, dst_unused, omod and clamp modifiers are unavailable. Allowed patterns: VOPC (32 bits) VOPC + LITERAL (64 bits) VOPC + SDWA (64 bits) ENCODING Encoding. 7 25 OP Opcode. 8 17 SRC0 First operand for instruction. 9 0 VSRC1 Second operand for instruction. 8 9 ENC_VOP2 32 11111110000000000000000000000000 00000010000000000000000000000000 00000100000000000000000000000000 00000110000000000000000000000000 00001000000000000000000000000000 00001010000000000000000000000000 00001100000000000000000000000000 00001110000000000000000000000000 00010000000000000000000000000000 00010010000000000000000000000000 00010100000000000000000000000000 00010110000000000000000000000000 00011000000000000000000000000000 00011010000000000000000000000000 00011110000000000000000000000000 00100000000000000000000000000000 00100010000000000000000000000000 00100100000000000000000000000000 00100110000000000000000000000000 00101000000000000000000000000000 00101100000000000000000000000000 00110000000000000000000000000000 00110100000000000000000000000000 00110110000000000000000000000000 00111000000000000000000000000000 00111010000000000000000000000000 00111100000000000000000000000000 00111110000000000000000000000000 01001010000000000000000000000000 01001100000000000000000000000000 01001110000000000000000000000000 01010000000000000000000000000000 01010010000000000000000000000000 01010100000000000000000000000000 01010110000000000000000000000000 01011110000000000000000000000000 01100100000000000000000000000000 01100110000000000000000000000000 01101000000000000000000000000000 01101010000000000000000000000000 01101100000000000000000000000000 01110010000000000000000000000000 01110100000000000000000000000000 01110110000000000000000000000000 01111000000000000000000000000000 default && && && != .fieldderef .fieldderef INST VOP2 SRC0 I 32 250 I 32 U 1 && != .fieldderef .fieldderef INST VOP2 SRC0 I 32 233 I 32 U 1 != .fieldderef .fieldderef INST VOP2 SRC0 I 32 234 I 32 U 1 U 1 U 1 != .fieldderef .fieldderef INST VOP2 SRC0 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP2 SRC0 I 32 249 I 32 U 1 U 1 Vector ALU operations with one destination and two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. SDWA and DPP modes are allowed unless otherwise noted. Allowed patterns: VOP2 (32 bits) VOP2 + LITERAL (64 bits) VOP2 + SDWA (64 bits) VOP2 + DPP (64 bits) ENCODING Encoding. 1 31 OP Opcode. 6 25 SRC0 First operand for instruction. 9 0 VDST Destination for instruction. 8 17 VSRC1 Second operand for instruction. 8 9 ENC_VINTRP 32 11111100000000110000000000000000 11001000000000000000000000000000 11001000000000010000000000000000 11001000000000100000000000000000 default 1 U 1 Vector ALU interpolation. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. SDWA, DPP or literal constants cannot be used with interpolation instructions. ATTR Attribute to interpolate. 6 10 ATTRCHAN Attribute component to interpolate. 2 8 ENCODING Encoding. 6 26 OP Opcode. 2 16 VDST VGPR to write results to, and optionally to read from when accumulating results. 8 18 VSRC VGPR containing the i/j coordinate to multiply one of the parameter components by. 8 0 ENC_VOP3 64 0000000000000000000000000000000011111111111111110000000000000000 0000000000000000000000000000000011010110000000000000000000000000 0000000000000000000000000000000011010110000000010000000000000000 0000000000000000000000000000000011010110000000100000000000000000 0000000000000000000000000000000011010101100000000000000000000000 0000000000000000000000000000000011010101100000010000000000000000 0000000000000000000000000000000011010101100000100000000000000000 0000000000000000000000000000000011010101100000110000000000000000 0000000000000000000000000000000011010101100001000000000000000000 0000000000000000000000000000000011010101100001010000000000000000 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0000000000000000000000000000000011010100111110100000000000000000 0000000000000000000000000000000011010100111110110000000000000000 0000000000000000000000000000000011010100111111000000000000000000 0000000000000000000000000000000011010100111111010000000000000000 0000000000000000000000000000000011010100111111100000000000000000 0000000000000000000000000000000011010100111111110000000000000000 default && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 Vector ALU operations requiring three sources or modifiers; also some obscure opcodes that cannot be encoded in smaller instructions due to limited OP bits. Almost all VOP1, VOP2, VOPC and VINTRP opcodes can be promoted to VOP3 to use input and output modifiers. Allowed patterns: VOP3 (64 bits) VOP3 + LITERAL (96 bits) ABS If ABS[N] set, take the floating-point absolute value of the N'th input operand. This is applied before negation. 3 8 CLAMP If set, clamp output to [0.0, 1.0]. Applied after output modifier. 1 15 ENCODING Encoding. 6 26 NEG If NEG[N] set, take the floating-point negation of the N'th input operand. This is applied after absolute value. 3 61 OMOD Output modifier for instruction. Applied before clamping. 2 59 OP Opcode. 10 16 OP_SEL OP_SEL [0,1,2] to select src0,src1,src2 lower[0:15] or higher order[16:31] bits. OP_SEL[3] to select destination.If 0 select [0:15] If 1 select [16:31].For destination 0 sets higher order bits to zero and [0:15] is result. If 1 result in higher order bits and bits preserved in [0:15]. 4 11 SRC0 First operand for instruction. 9 32 SRC1 Second operand for instruction. 9 41 SRC2 Third operand for instruction. 9 50 VDST Destination for instruction. 8 0 ENC_VOP3P 64 0000000000000000000000000000000011111100011111110000000000000000 0000000000000000000000000000000011001100000000000000000000000000 0000000000000000000000000000000011001100000000010000000000000000 0000000000000000000000000000000011001100000000100000000000000000 0000000000000000000000000000000011001100000000110000000000000000 0000000000000000000000000000000011001100000001000000000000000000 0000000000000000000000000000000011001100000001010000000000000000 0000000000000000000000000000000011001100000001100000000000000000 0000000000000000000000000000000011001100000001110000000000000000 0000000000000000000000000000000011001100000010000000000000000000 0000000000000000000000000000000011001100000010010000000000000000 0000000000000000000000000000000011001100000010100000000000000000 0000000000000000000000000000000011001100000010110000000000000000 0000000000000000000000000000000011001100000011000000000000000000 0000000000000000000000000000000011001100000011010000000000000000 0000000000000000000000000000000011001100000011100000000000000000 0000000000000000000000000000000011001100000011110000000000000000 0000000000000000000000000000000011001100000100000000000000000000 0000000000000000000000000000000011001100000100010000000000000000 0000000000000000000000000000000011001100000100100000000000000000 0000000000000000000000000000000011001100000100110000000000000000 0000000000000000000000000000000011001100000101000000000000000000 0000000000000000000000000000000011001100000101010000000000000000 0000000000000000000000000000000011001100000101100000000000000000 0000000000000000000000000000000011001100000101110000000000000000 0000000000000000000000000000000011001100000110000000000000000000 0000000000000000000000000000000011001100000110010000000000000000 0000000000000000000000000000000011001100001000000000000000000000 0000000000000000000000000000000011001100001000010000000000000000 0000000000000000000000000000000011001100001000100000000000000000 default && && != .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 Packed math instructions: vector ALU operations requiring two or three sources and performing two 16 bit ops in one instruction. Allowed patterns: VOP3P (64 bits) VOP3P + LITERAL (96 bits) CLAMP If set, clamp output to [0.0, 1.0]. Applied after output modifier. 1 15 ENCODING Encoding. 6 26 NEG If NEG[N] set, take the floating-point negation of the N'th input low opcode. This is applied after absolute value. 3 61 NEG_HI If NEG_HI[N] set, take the floating-point negation of the N'th input high opcode. This is applied after absolute value. 3 8 OP Opcode. 7 16 OP_SEL Input modifier for low opcode src0, src1 and src2. If 0 select src[0:15]. If 1 select src[16:31]. 3 11 OP_SEL_HI Input modifier for high opcode src0 and src1. If 0 select src[0:15]. If 1 select src[16:31]. 2 59 OP_SEL_HI_2 Input modifier for high opcode src2. If 0 select src2[0:15]. If 1 select src2[16:31]. 1 14 SRC0 First operand for instruction. 9 32 SRC1 Second operand for instruction. 9 41 SRC2 Third operand for instruction. 9 50 VDST Destination for instruction. 8 0 ENC_DS 64 0000000000000000000000000000000011111111111111000000000000000000 0000000000000000000000000000000011011000000000000000000000000000 0000000000000000000000000000000011011000000001000000000000000000 0000000000000000000000000000000011011000000010000000000000000000 0000000000000000000000000000000011011000000011000000000000000000 0000000000000000000000000000000011011000000100000000000000000000 0000000000000000000000000000000011011000000101000000000000000000 0000000000000000000000000000000011011000000110000000000000000000 0000000000000000000000000000000011011000000111000000000000000000 0000000000000000000000000000000011011000001000000000000000000000 0000000000000000000000000000000011011000001001000000000000000000 0000000000000000000000000000000011011000001010000000000000000000 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0000000000000000000000000000000011011010110001000000000000000000 0000000000000000000000000000000011011010110010000000000000000000 0000000000000000000000000000000011011010110011000000000000000000 0000000000000000000000000000000011011011011110000000000000000000 0000000000000000000000000000000011011011011111000000000000000000 0000000000000000000000000000000011011011111110000000000000000000 0000000000000000000000000000000011011011111111000000000000000000 default 1 U 1 Local and global data share operations. Examples: // Write 1 dword from v22 into LDS at byte address v12 ds_write_b32 v12, v22 // Read 1 dword from LDS byte address (v3 + 120), write value to v2 ds_read_b32 v2, v3 offset:120 // Write 2 dwords from v[4:5] into GDS at byte address v10 ds_write_b32 v10, v[4:5] gds ADDR source LDS address VGPR 8 32 DATA0 source data 0 8 40 DATA1 source data 1 8 48 ENCODING Encoding. 6 26 GDS 1=GDS, 0=LDS 1 17 OFFSET0 First DS offset. See individual instructions for how this field is used. 8 0 OFFSET1 Second DS offset. See individual instructions for how this field is used. 8 8 OP Opcode. 8 18 VDST destination VGPR 8 56 ENC_MUBUF 64 0000000000000000000000000000000011111101111111000000000000000000 0000000000000000000000000000000011100000000000000000000000000000 0000000000000000000000000000000011100000000001000000000000000000 0000000000000000000000000000000011100000000010000000000000000000 0000000000000000000000000000000011100000000011000000000000000000 0000000000000000000000000000000011100000000100000000000000000000 0000000000000000000000000000000011100000000101000000000000000000 0000000000000000000000000000000011100000000110000000000000000000 0000000000000000000000000000000011100000000111000000000000000000 0000000000000000000000000000000011100000001000000000000000000000 0000000000000000000000000000000011100000001001000000000000000000 0000000000000000000000000000000011100000001010000000000000000000 0000000000000000000000000000000011100000001011000000000000000000 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0000000000000000000000000000000011100010000110000000000000000000 0000000000000000000000000000000011100010000111000000000000000000 default 1 U 1 Untyped vector memory buffer operations. DLC If set, operation is L1-coherent (synced between WGPs in a shader engine). 1 15 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 14 IDXEN If set, send VADDR as an index. If unset, treat the index as zero. 1 13 LDS If set, data is read from/written to LDS memory. If unset, data is read from/written to a VGPR. 1 16 OFFEN If set, send VADDR as an offset. If unset, send the instruction offset stored in OFFSET. Only one of these offsets may be sent. 1 12 OFFSET Unsigned byte offset 12 0 OP Opcode. 7 18 OPM Opcode -- extension for MSBs. 1 25 SLC System Level Coherent. 1 54 SOFFSET Scalar or constant GPR containing the base offset. 8 56 SRSRC Scalar GPR that specifies the resource constant, in units of 4 SGPRs. 5 48 2 00 TFE Texture Fail Enable (for partially resident textures). 1 55 VADDR Address source - may carry an offset or an index. 8 32 VDATA Vector GPR to read/write result to. 8 40 ENC_MTBUF 64 0000000000000000000000000000000011111100000001110000000000000000 0000000000000000000000000000000011101000000000000000000000000000 0000000000000000000000000000000011101000000000010000000000000000 0000000000000000000000000000000011101000000000100000000000000000 0000000000000000000000000000000011101000000000110000000000000000 0000000000000000000000000000000011101000000001000000000000000000 0000000000000000000000000000000011101000000001010000000000000000 0000000000000000000000000000000011101000000001100000000000000000 0000000000000000000000000000000011101000000001110000000000000000 0000000000000000000000000000000011101000000010000000000000000000 0000000000000000000000000000000011101000000010010000000000000000 0000000000000000000000000000000011101000000010100000000000000000 0000000000000000000000000000000011101000000010110000000000000000 0000000000000000000000000000000011101000000011000000000000000000 0000000000000000000000000000000011101000000011010000000000000000 0000000000000000000000000000000011101000000011100000000000000000 0000000000000000000000000000000011101000000011110000000000000000 default 1 U 1 Typed vector memory buffer operations. Example from textri: s_load_dwordx4 s[20:23], s[0:1], 0x0 // pos resource buffer s_load_dwordx4 s[24:27], s[0:1], 0x4 // color0 resource buffer s_load_dwordx4 s[28:31], s[0:1], 0x10 // tex0 resource buffer s_movk_i32 s16, 0x0000 // soffset s_waitcnt lgkmcnt(0) // v4..v7 -> Unadjusted position tbuffer_load_format_xyzw v4, v0, s20, s16 idxen \\ format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] // v8..v11 -> Color tbuffer_load_format_xyzw v8, v0, s24, s16 idxen \\ format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] // v12..v15 -> Texture coordinates tbuffer_load_format_xyzw v12, v0, s28, s16 idxen \\ format:[BUF_DATA_FORMAT_32_32_32_32,BUF_NUM_FORMAT_FLOAT] ... s_waitcnt vmcnt(0) // now safe to access v4..v15. DLC If set, operation is L1-coherent (synced between WGPs in a shader engine). 1 15 ENCODING Encoding. 6 26 FORMAT Format for typed buffer. LEGACY MODE: Bits 3:0 are legacy dfmt, and bits 6:4 are legacy nfmt. 7 19 GLC If set, operation is globally coherent. 1 14 IDXEN If set, send VADDR as an index. If unset, treat the index as zero. 1 13 OFFEN If set, send VADDR as an offset. If unset, send the instruction offset stored in OFFSET. Only one of these offsets may be sent. 1 12 OFFSET Unsigned byte offset. 12 0 OP opcode: read/write and x,xy,xyz,xyzw 3 16 OPM Opcode -- extension for MSBs. 1 53 SLC System Level Coherent. 1 54 SOFFSET Scalar GPR or constant containing the base offset. 8 56 SRSRC Scalar GPR that specifies the resource constant, in units of 4 SGPRs. 5 48 2 00 TFE Texture Fail Enable (for partially resident textures). 1 55 VADDR Address source - may carry an offset or an index. 8 32 VDATA Vector GPR to read/write result to. 8 40 ENC_MIMG 64 0000000000000000000000000000000011111101111111000000000000000000 0000000000000000000000000000000011110000000000000000000000000000 0000000000000000000000000000000011110000000001000000000000000000 0000000000000000000000000000000011110000000010000000000000000000 0000000000000000000000000000000011110000000011000000000000000000 0000000000000000000000000000000011110000000100000000000000000000 0000000000000000000000000000000011110000000101000000000000000000 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0000000000000000000000000000000011110011101110000000000000000000 0000000000000000000000000000000011110011101111000000000000000000 default && && != .fieldderef .fieldderef INST MIMG NSA I 32 1 I 32 U 1 != .fieldderef .fieldderef INST MIMG NSA I 32 2 I 32 U 1 U 1 != .fieldderef .fieldderef INST MIMG NSA I 32 3 I 32 U 1 U 1 Memory image (texture) operations. Example from textri: s_load_dwordx8 s[20:27], s[2:3], 0x0 // load image resource buffer s_load_dwordx4 s[28:31], s[4:5], 0x0 // load image sampler buffer s_waitcnt lgkmcnt(0) // v4..v7 -> incoming texture coordinates // v16..v19 -> the resulting sample from the texture image_sample v16, v4, s20, s28 dmask:0xf ... s_waitcnt vmcnt(0) // now save to access v16..v19 NSA example: image_sample v[0:3], [v9,v4], s[20:27], s[28:31] // address component is NSA A16 Texture coordinates size: 1=16b, 0=32b 1 62 D16 If set, convert 32 bit floating point texture return data to 16 bit. 1 63 DA Declare Array: 1=shader declared this texture to be an array and SH sends array-index (slice#) to TA; 0=shader declared non-array type and does not send out array-index (slice#). TA assumes slice# is zero when it doesn't receive one. DEPRECATED in GFX10 mode. 1 14 DIM Dimensionality of resource constant, used to determine the number of addresses supplied for this instruction. This should be set the same as bits [3:1] of the resource TYPE field. (GFX10+ only). 3 3 DLC If set, operation is L1-coherent (synced between WGPs in a shader engine). 1 7 DMASK Enable mask for image read/write data components. bit0=red, 1=green, 2=blue, 3=alpha. At least 1 bit must be on. Data is assumed to be packed into consecutive VGPRs. 4 8 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 13 LWE LOD Warning Enable (for partially resident textures). 1 17 NSA Non Sequential Address mode: triggers reading additional dwords in the instruction stream to obtain all the address components. Specifies the number of additional DWORDs carrying address registers, 0 means no additional dwords. GFX10+ only. 2 1 OP Opcode. 7 18 OPM Opcode -- extension for MSBs. 1 0 R128 Texture resource size: 1=128b, 0=256b 1 15 SLC System Level Coherent. 1 25 SRSRC Scalar GPR that specifies the resource constant, in units of 4 SGPRs. 5 48 2 00 SSAMP Scalar GPR that specifies the sampler constant, in units of 4 SGPRs. 5 53 2 00 TFE Texture Fail Enable (for partially resident textures). 1 16 UNORM Force address to be un-normalized regardless of texture sampler setting. Must be set to 1 for image store and atomic operations. 1 12 VADDR Address source - may carry an offset or an index. 8 32 VDATA Vector GPR to write result to. 8 40 ENC_EXP 64 0000000000000000000000000000000011111100000000000000000000000000 0000000000000000000000000000000011111000000000000000000000000000 default 1 U 1 Graphics export operations. Example: // Export RGBA color to render target 0, using values in v[0:3] exp mrt0, v0, v1, v2, v3 ... // Need to ensure the export has completed before modifying v0: s_waitcnt expcnt(0) v_mov_b32 v0, ... ... // Export a single colour to render target 1, and export the valid mask // Mark this as the final render target export with the 'done' flag: exp mrt1, v0, off, off, off done vm COMPR Boolean. If true, data is exported in float16 format;If false, data is 32 bit. 1 10 DONE If set, this is the last export of a given type. If this is set for a colour export (PS only), then the valid mask must be present in the EXEC register. 1 11 EN En[0] is red or x, en[3] is alpha or w. Compressed export: enables for half-dword export; EN[0] for low 16 bits of VSRC0, EN[1] for high 16 bits of VSRC0, EN[2] for low 16 bits of VSRC1, EN[3] for high 16 bits of VSRC1. Non-float16: enables for VSRCs, EN[N] for VSRC[N]. 4 0 ENCODING Encoding. 6 26 TGT Export target based on the enumeration below. 6 4 VM Mask contains valid-mask when set; otherwise mask is just write-mask. Used only for pixel(MRT) exports. 1 12 VSRC0 VGPR of the first data to export. 8 32 VSRC1 VGPR of the second data to export. 8 40 VSRC2 VGPR of the third data to export. 8 48 VSRC3 VGPR of the fourth data to export. 8 56 ENC_FLAT 64 0000000000000000000000000000000011111101111111001100000000000000 0000000000000000000000000000000011011100001000000000000000000000 0000000000000000000000000000000011011100001001000000000000000000 0000000000000000000000000000000011011100001010000000000000000000 0000000000000000000000000000000011011100001011000000000000000000 0000000000000000000000000000000011011100001100000000000000000000 0000000000000000000000000000000011011100001101000000000000000000 0000000000000000000000000000000011011100001110000000000000000000 0000000000000000000000000000000011011100001111000000000000000000 0000000000000000000000000000000011011100011000000000000000000000 0000000000000000000000000000000011011100011001000000000000000000 0000000000000000000000000000000011011100011010000000000000000000 0000000000000000000000000000000011011100011011000000000000000000 0000000000000000000000000000000011011100011100000000000000000000 0000000000000000000000000000000011011100011101000000000000000000 0000000000000000000000000000000011011100011110000000000000000000 0000000000000000000000000000000011011100011111000000000000000000 0000000000000000000000000000000011011100100000000000000000000000 0000000000000000000000000000000011011100100001000000000000000000 0000000000000000000000000000000011011100100010000000000000000000 0000000000000000000000000000000011011100100011000000000000000000 0000000000000000000000000000000011011100100100000000000000000000 0000000000000000000000000000000011011100100101000000000000000000 0000000000000000000000000000000011011100110000000000000000000000 0000000000000000000000000000000011011100110001000000000000000000 0000000000000000000000000000000011011100110010000000000000000000 0000000000000000000000000000000011011100110011000000000000000000 0000000000000000000000000000000011011100110101000000000000000000 0000000000000000000000000000000011011100110110000000000000000000 0000000000000000000000000000000011011100110111000000000000000000 0000000000000000000000000000000011011100111000000000000000000000 0000000000000000000000000000000011011100111001000000000000000000 0000000000000000000000000000000011011100111010000000000000000000 0000000000000000000000000000000011011100111011000000000000000000 0000000000000000000000000000000011011100111100000000000000000000 0000000000000000000000000000000011011100111101000000000000000000 0000000000000000000000000000000011011100111110000000000000000000 0000000000000000000000000000000011011100111111000000000000000000 0000000000000000000000000000000011011101000000000000000000000000 0000000000000000000000000000000011011101010000000000000000000000 0000000000000000000000000000000011011101010001000000000000000000 0000000000000000000000000000000011011101010010000000000000000000 0000000000000000000000000000000011011101010011000000000000000000 0000000000000000000000000000000011011101010101000000000000000000 0000000000000000000000000000000011011101010110000000000000000000 0000000000000000000000000000000011011101010111000000000000000000 0000000000000000000000000000000011011101011000000000000000000000 0000000000000000000000000000000011011101011001000000000000000000 0000000000000000000000000000000011011101011010000000000000000000 0000000000000000000000000000000011011101011011000000000000000000 0000000000000000000000000000000011011101011100000000000000000000 0000000000000000000000000000000011011101011101000000000000000000 0000000000000000000000000000000011011101011110000000000000000000 0000000000000000000000000000000011011101011111000000000000000000 0000000000000000000000000000000011011101100000000000000000000000 default 1 U 1 Flat (DUA) addressing instructions. For basic flat instructions note that a VGPR address must be specified. SGPR addresses are not allowed. ADDR source flat address VGPR 8 32 DATA source data 8 40 DLC Something about GL2 cache control; also known as the Fowler bit. 1 12 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 16 LDS Write Data to LDS. Must be zero for FLAT instructions, as well as all stores and atomics. 1 13 OFFSET 12-bit unsigned offset 12 0 OP Opcode. 7 18 SADDR addr/offset SGPR 7 48 SEG FLAT=00 2 14 SLC System Level Coherent. 1 17 VDST destination VGPR 8 56 ENC_FLAT_GLBL 64 0000000000000000000000000000000011111101111111001100000000000000 0000000000000000000000000000000011011100001000001000000000000000 0000000000000000000000000000000011011100001001001000000000000000 0000000000000000000000000000000011011100001010001000000000000000 0000000000000000000000000000000011011100001011001000000000000000 0000000000000000000000000000000011011100001100001000000000000000 0000000000000000000000000000000011011100001101001000000000000000 0000000000000000000000000000000011011100001110001000000000000000 0000000000000000000000000000000011011100001111001000000000000000 0000000000000000000000000000000011011100011000001000000000000000 0000000000000000000000000000000011011100011001001000000000000000 0000000000000000000000000000000011011100011010001000000000000000 0000000000000000000000000000000011011100011011001000000000000000 0000000000000000000000000000000011011100011100001000000000000000 0000000000000000000000000000000011011100011101001000000000000000 0000000000000000000000000000000011011100011110001000000000000000 0000000000000000000000000000000011011100011111001000000000000000 0000000000000000000000000000000011011100100000001000000000000000 0000000000000000000000000000000011011100100001001000000000000000 0000000000000000000000000000000011011100100010001000000000000000 0000000000000000000000000000000011011100100011001000000000000000 0000000000000000000000000000000011011100100100001000000000000000 0000000000000000000000000000000011011100100101001000000000000000 0000000000000000000000000000000011011100110000001000000000000000 0000000000000000000000000000000011011100110001001000000000000000 0000000000000000000000000000000011011100110010001000000000000000 0000000000000000000000000000000011011100110011001000000000000000 0000000000000000000000000000000011011100110101001000000000000000 0000000000000000000000000000000011011100110110001000000000000000 0000000000000000000000000000000011011100110111001000000000000000 0000000000000000000000000000000011011100111000001000000000000000 0000000000000000000000000000000011011100111001001000000000000000 0000000000000000000000000000000011011100111010001000000000000000 0000000000000000000000000000000011011100111011001000000000000000 0000000000000000000000000000000011011100111100001000000000000000 0000000000000000000000000000000011011100111101001000000000000000 0000000000000000000000000000000011011100111110001000000000000000 0000000000000000000000000000000011011100111111001000000000000000 0000000000000000000000000000000011011101000000001000000000000000 0000000000000000000000000000000011011101010000001000000000000000 0000000000000000000000000000000011011101010001001000000000000000 0000000000000000000000000000000011011101010010001000000000000000 0000000000000000000000000000000011011101010011001000000000000000 0000000000000000000000000000000011011101010101001000000000000000 0000000000000000000000000000000011011101010110001000000000000000 0000000000000000000000000000000011011101010111001000000000000000 0000000000000000000000000000000011011101011000001000000000000000 0000000000000000000000000000000011011101011001001000000000000000 0000000000000000000000000000000011011101011010001000000000000000 0000000000000000000000000000000011011101011011001000000000000000 0000000000000000000000000000000011011101011100001000000000000000 0000000000000000000000000000000011011101011101001000000000000000 0000000000000000000000000000000011011101011110001000000000000000 0000000000000000000000000000000011011101011111001000000000000000 0000000000000000000000000000000011011101100000001000000000000000 Flat (DUA) global addressing instructions. For global instructions note that a VGPR address must be specified. In sp3 an SGPR address may be omitted by specifying "off" or "null" in the SADDR operand slot ("off" is a legacy syntax and is translated to "null"). ADDR source flat address VGPR 8 32 DATA source data 8 40 DLC Something about GL2 cache control; also known as the Fowler bit. 1 12 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 16 LDS Write Data to LDS. Must be zero for all stores and atomics. 1 13 OFFSET 12-bit signed offset 12 0 OP Opcode. 7 18 SADDR addr/offset SGPR 7 48 SEG GLOBAL=10 2 14 SLC System Level Coherent. 1 17 VDST destination VGPR 8 56 ENC_FLAT_SCRATCH 64 0000000000000000000000000000000011111101111111001100000000000000 0000000000000000000000000000000011011100001000000100000000000000 0000000000000000000000000000000011011100001001000100000000000000 0000000000000000000000000000000011011100001010000100000000000000 0000000000000000000000000000000011011100001011000100000000000000 0000000000000000000000000000000011011100001100000100000000000000 0000000000000000000000000000000011011100001101000100000000000000 0000000000000000000000000000000011011100001110000100000000000000 0000000000000000000000000000000011011100001111000100000000000000 0000000000000000000000000000000011011100011000000100000000000000 0000000000000000000000000000000011011100011001000100000000000000 0000000000000000000000000000000011011100011010000100000000000000 0000000000000000000000000000000011011100011011000100000000000000 0000000000000000000000000000000011011100011100000100000000000000 0000000000000000000000000000000011011100011101000100000000000000 0000000000000000000000000000000011011100011110000100000000000000 0000000000000000000000000000000011011100011111000100000000000000 0000000000000000000000000000000011011100100000000100000000000000 0000000000000000000000000000000011011100100001000100000000000000 0000000000000000000000000000000011011100100010000100000000000000 0000000000000000000000000000000011011100100011000100000000000000 0000000000000000000000000000000011011100100100000100000000000000 0000000000000000000000000000000011011100100101000100000000000000 Flat (DUA) scratch addressing instructions. For scratch instructions at most one of a VGPR address or an SGPR address must be specified. Both addresses cannot be used. For no address, in sp3 specify "off" or "null" for both the ADDR and SADDR operand slots. In binary microcode the SADDR field is set to 0x7f (EXEC_HI), this is not a real operand but instead signals a case of no address. For only a vector address, in sp3 specify "off" or "null" for the SADDR operand slot. This generates "null" in the SADDR field ("off" is a legacy syntax). For only a scalar address, in sp3 specify "off" or "null" for the ADDR operand slot. This causes SADDR to be generated normally, which in turn causes hardware to ignore the ADDR operand. ADDR source flat address VGPR 8 32 DATA source data 8 40 DLC Something about GL2 cache control; also known as the Fowler bit. 1 12 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 16 LDS Write Data to LDS. Must be zero for all stores and atomics. 1 13 OFFSET 12-bit signed offset 12 0 OP Opcode. 7 18 SADDR addr/offset SGPR 7 48 SEG SCRATCH=01 2 14 SLC System Level Coherent. 1 17 VDST destination VGPR 8 56 MIMG_NSA1 96 000000000000000000000000000000000000000000000000000000000000000011111101111111000000000000000000 000000000000000000000000000000000000000000000000000000000000000011110000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000011110000000001000000000000000000 000000000000000000000000000000000000000000000000000000000000000011110000000010000000000000000000 000000000000000000000000000000000000000000000000000000000000000011110000000011000000000000000000 000000000000000000000000000000000000000000000000000000000000000011110000000100000000000000000000 000000000000000000000000000000000000000000000000000000000000000011110000000101000000000000000000 000000000000000000000000000000000000000000000000000000000000000011110000001000000000000000000000 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000000000000000000000000000000000000000000000000000000000000000011110011101111000000000000000000 has_nsa_1 == .fieldderef .fieldderef INST MIMG NSA I 32 1 I 32 U 1 Memory image (texture) operations. Example from textri: s_load_dwordx8 s[20:27], s[2:3], 0x0 // load image resource buffer s_load_dwordx4 s[28:31], s[4:5], 0x0 // load image sampler buffer s_waitcnt lgkmcnt(0) // v4..v7 -> incoming texture coordinates // v16..v19 -> the resulting sample from the texture image_sample v16, v4, s20, s28 dmask:0xf ... s_waitcnt vmcnt(0) // now save to access v16..v19 NSA example: image_sample v[0:3], [v9,v4], s[20:27], s[28:31] // address component is NSA A16 Texture coordinates size: 1=16b, 0=32b 1 62 D16 If set, convert 32 bit floating point texture return data to 16 bit. 1 63 DA Declare Array: 1=shader declared this texture to be an array and SH sends array-index (slice#) to TA; 0=shader declared non-array type and does not send out array-index (slice#). TA assumes slice# is zero when it doesn't receive one. DEPRECATED in GFX10 mode. 1 14 DIM Dimensionality of resource constant, used to determine the number of addresses supplied for this instruction. This should be set the same as bits [3:1] of the resource TYPE field. (GFX10+ only). 3 3 DLC If set, operation is L1-coherent (synced between WGPs in a shader engine). 1 7 DMASK Enable mask for image read/write data components. bit0=red, 1=green, 2=blue, 3=alpha. At least 1 bit must be on. Data is assumed to be packed into consecutive VGPRs. 4 8 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 13 LWE LOD Warning Enable (for partially resident textures). 1 17 NSA Non Sequential Address mode: triggers reading additional dwords in the instruction stream to obtain all the address components. Specifies the number of additional DWORDs carrying address registers, 0 means no additional dwords. GFX10+ only. 2 1 OP Opcode. 7 18 OPM Opcode -- extension for MSBs. 1 0 R128 Texture resource size: 1=128b, 0=256b 1 15 SLC System Level Coherent. 1 25 SRSRC Scalar GPR that specifies the resource constant, in units of 4 SGPRs. 5 48 2 00 SSAMP Scalar GPR that specifies the sampler constant, in units of 4 SGPRs. 5 53 2 00 TFE Texture Fail Enable (for partially resident textures). 1 16 UNORM Force address to be un-normalized regardless of texture sampler setting. Must be set to 1 for image store and atomic operations. 1 12 VADDR Address source - may carry an offset or an index. 8 32 VADDRA Address source - may carry an offset or an index. 8 64 VADDRB Address source - may carry an offset or an index. 8 72 VADDRC Address source - may carry an offset or an index. 8 80 VADDRD Address source - may carry an offset or an index. 8 88 VDATA Vector GPR to write result to. 8 40 MIMG_NSA2 128 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111101111111000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011110000000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011110000000001000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011110000000010000000000000000000 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Example from textri: s_load_dwordx8 s[20:27], s[2:3], 0x0 // load image resource buffer s_load_dwordx4 s[28:31], s[4:5], 0x0 // load image sampler buffer s_waitcnt lgkmcnt(0) // v4..v7 -> incoming texture coordinates // v16..v19 -> the resulting sample from the texture image_sample v16, v4, s20, s28 dmask:0xf ... s_waitcnt vmcnt(0) // now save to access v16..v19 NSA example: image_sample v[0:3], [v9,v4], s[20:27], s[28:31] // address component is NSA A16 Texture coordinates size: 1=16b, 0=32b 1 62 D16 If set, convert 32 bit floating point texture return data to 16 bit. 1 63 DA Declare Array: 1=shader declared this texture to be an array and SH sends array-index (slice#) to TA; 0=shader declared non-array type and does not send out array-index (slice#). TA assumes slice# is zero when it doesn't receive one. DEPRECATED in GFX10 mode. 1 14 DIM Dimensionality of resource constant, used to determine the number of addresses supplied for this instruction. This should be set the same as bits [3:1] of the resource TYPE field. (GFX10+ only). 3 3 DLC If set, operation is L1-coherent (synced between WGPs in a shader engine). 1 7 DMASK Enable mask for image read/write data components. bit0=red, 1=green, 2=blue, 3=alpha. At least 1 bit must be on. Data is assumed to be packed into consecutive VGPRs. 4 8 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 13 LWE LOD Warning Enable (for partially resident textures). 1 17 NSA Non Sequential Address mode: triggers reading additional dwords in the instruction stream to obtain all the address components. Specifies the number of additional DWORDs carrying address registers, 0 means no additional dwords. GFX10+ only. 2 1 OP Opcode. 7 18 OPM Opcode -- extension for MSBs. 1 0 R128 Texture resource size: 1=128b, 0=256b 1 15 SLC System Level Coherent. 1 25 SRSRC Scalar GPR that specifies the resource constant, in units of 4 SGPRs. 5 48 2 00 SSAMP Scalar GPR that specifies the sampler constant, in units of 4 SGPRs. 5 53 2 00 TFE Texture Fail Enable (for partially resident textures). 1 16 UNORM Force address to be un-normalized regardless of texture sampler setting. Must be set to 1 for image store and atomic operations. 1 12 VADDR Address source - may carry an offset or an index. 8 32 VADDRA Address source - may carry an offset or an index. 8 64 VADDRB Address source - may carry an offset or an index. 8 72 VADDRC Address source - may carry an offset or an index. 8 80 VADDRD Address source - may carry an offset or an index. 8 88 VADDRE Address source - may carry an offset or an index. 8 96 VADDRF Address source - may carry an offset or an index. 8 104 VADDRG Address source - may carry an offset or an index. 8 112 VADDRH Address source - may carry an offset or an index. 8 120 VDATA Vector GPR to write result to. 8 40 MIMG_NSA3 160 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111101111111000000000000000000 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011110000000000000000000000000000 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0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011110011101111000000000000000000 has_nsa_3 == .fieldderef .fieldderef INST MIMG NSA I 32 3 I 32 U 1 Memory image (texture) operations. Example from textri: s_load_dwordx8 s[20:27], s[2:3], 0x0 // load image resource buffer s_load_dwordx4 s[28:31], s[4:5], 0x0 // load image sampler buffer s_waitcnt lgkmcnt(0) // v4..v7 -> incoming texture coordinates // v16..v19 -> the resulting sample from the texture image_sample v16, v4, s20, s28 dmask:0xf ... s_waitcnt vmcnt(0) // now save to access v16..v19 NSA example: image_sample v[0:3], [v9,v4], s[20:27], s[28:31] // address component is NSA A16 Texture coordinates size: 1=16b, 0=32b 1 62 D16 If set, convert 32 bit floating point texture return data to 16 bit. 1 63 DA Declare Array: 1=shader declared this texture to be an array and SH sends array-index (slice#) to TA; 0=shader declared non-array type and does not send out array-index (slice#). TA assumes slice# is zero when it doesn't receive one. DEPRECATED in GFX10 mode. 1 14 DIM Dimensionality of resource constant, used to determine the number of addresses supplied for this instruction. This should be set the same as bits [3:1] of the resource TYPE field. (GFX10+ only). 3 3 DLC If set, operation is L1-coherent (synced between WGPs in a shader engine). 1 7 DMASK Enable mask for image read/write data components. bit0=red, 1=green, 2=blue, 3=alpha. At least 1 bit must be on. Data is assumed to be packed into consecutive VGPRs. 4 8 ENCODING Encoding. 6 26 GLC If set, operation is globally coherent. 1 13 LWE LOD Warning Enable (for partially resident textures). 1 17 NSA Non Sequential Address mode: triggers reading additional dwords in the instruction stream to obtain all the address components. Specifies the number of additional DWORDs carrying address registers, 0 means no additional dwords. GFX10+ only. 2 1 OP Opcode. 7 18 OPM Opcode -- extension for MSBs. 1 0 R128 Texture resource size: 1=128b, 0=256b 1 15 SLC System Level Coherent. 1 25 SRSRC Scalar GPR that specifies the resource constant, in units of 4 SGPRs. 5 48 2 00 SSAMP Scalar GPR that specifies the sampler constant, in units of 4 SGPRs. 5 53 2 00 TFE Texture Fail Enable (for partially resident textures). 1 16 UNORM Force address to be un-normalized regardless of texture sampler setting. Must be set to 1 for image store and atomic operations. 1 12 VADDR Address source - may carry an offset or an index. 8 32 VADDRA Address source - may carry an offset or an index. 8 64 VADDRB Address source - may carry an offset or an index. 8 72 VADDRC Address source - may carry an offset or an index. 8 80 VADDRD Address source - may carry an offset or an index. 8 88 VADDRE Address source - may carry an offset or an index. 8 96 VADDRF Address source - may carry an offset or an index. 8 104 VADDRG Address source - may carry an offset or an index. 8 112 VADDRH Address source - may carry an offset or an index. 8 120 VADDRI Address source - may carry an offset or an index. 8 128 VADDRJ Address source - may carry an offset or an index. 8 136 VADDRK Address source - may carry an offset or an index. 8 144 VADDRL Address source - may carry an offset or an index. 8 152 VDATA Vector GPR to write result to. 8 40 SOP1_INST_LITERAL 64 0000000000000000000000000000000011111111100000001111111100000000 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0000000000000000000000000000000010111110100000000100011100000000 0000000000000000000000000000000010111110100000000100100100000000 has_lit_0 == .fieldderef .fieldderef INST SOP1 SSRC0 I 32 255 I 32 U 1 Scalar ALU operations with one destination and one source. Allowed patterns: SOP1 (32 bits) SOP1 + LITERAL (64 bits) ENCODING Encoding. 9 23 OP Opcode. 8 8 SDST Destination for instruction. 7 16 SIMM32 32-bit literal constant. 32 32 SSRC0 Operand for instruction. 8 0 SOP2_INST_LITERAL 64 0000000000000000000000000000000011111111100000000000000000000000 0000000000000000000000000000000010000000000000000000000000000000 0000000000000000000000000000000010000000100000000000000000000000 0000000000000000000000000000000010000001000000000000000000000000 0000000000000000000000000000000010000001100000000000000000000000 0000000000000000000000000000000010000010000000000000000000000000 0000000000000000000000000000000010000010100000000000000000000000 0000000000000000000000000000000010000011000000000000000000000000 0000000000000000000000000000000010000011100000000000000000000000 0000000000000000000000000000000010000100000000000000000000000000 0000000000000000000000000000000010000100100000000000000000000000 0000000000000000000000000000000010000101000000000000000000000000 0000000000000000000000000000000010000101100000000000000000000000 0000000000000000000000000000000010000111000000000000000000000000 0000000000000000000000000000000010000111100000000000000000000000 0000000000000000000000000000000010001000000000000000000000000000 0000000000000000000000000000000010001000100000000000000000000000 0000000000000000000000000000000010001001000000000000000000000000 0000000000000000000000000000000010001001100000000000000000000000 0000000000000000000000000000000010001010000000000000000000000000 0000000000000000000000000000000010001010100000000000000000000000 0000000000000000000000000000000010001011000000000000000000000000 0000000000000000000000000000000010001011100000000000000000000000 0000000000000000000000000000000010001100000000000000000000000000 0000000000000000000000000000000010001100100000000000000000000000 0000000000000000000000000000000010001101000000000000000000000000 0000000000000000000000000000000010001101100000000000000000000000 0000000000000000000000000000000010001110000000000000000000000000 0000000000000000000000000000000010001110100000000000000000000000 0000000000000000000000000000000010001111000000000000000000000000 0000000000000000000000000000000010001111100000000000000000000000 0000000000000000000000000000000010010000000000000000000000000000 0000000000000000000000000000000010010000100000000000000000000000 0000000000000000000000000000000010010001000000000000000000000000 0000000000000000000000000000000010010001100000000000000000000000 0000000000000000000000000000000010010010000000000000000000000000 0000000000000000000000000000000010010010100000000000000000000000 0000000000000000000000000000000010010011000000000000000000000000 0000000000000000000000000000000010010011100000000000000000000000 0000000000000000000000000000000010010100000000000000000000000000 0000000000000000000000000000000010010100100000000000000000000000 0000000000000000000000000000000010010101000000000000000000000000 0000000000000000000000000000000010010110000000000000000000000000 0000000000000000000000000000000010010111000000000000000000000000 0000000000000000000000000000000010010111100000000000000000000000 0000000000000000000000000000000010011000000000000000000000000000 0000000000000000000000000000000010011000100000000000000000000000 0000000000000000000000000000000010011001000000000000000000000000 0000000000000000000000000000000010011001100000000000000000000000 0000000000000000000000000000000010011010000000000000000000000000 0000000000000000000000000000000010011010100000000000000000000000 0000000000000000000000000000000010011011000000000000000000000000 has_lit_0 && == .fieldderef .fieldderef INST SOP2 SSRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST SOP2 SSRC1 I 32 255 I 32 U 1 U 1 has_lit_1 && != .fieldderef .fieldderef INST SOP2 SSRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST SOP2 SSRC1 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1 && == .fieldderef .fieldderef INST SOP2 SSRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST SOP2 SSRC1 I 32 255 I 32 U 1 U 1 Scalar ALU operations with one destination and two sources. Allowed patterns: SOP2 (32 bits) SOP2 + LITERAL (64 bits) ENCODING Encoding. 2 30 OP Opcode. 7 23 SDST Destination for instruction. 7 16 SIMM32 32-bit literal constant. 32 32 SSRC0 First operand for instruction. 8 0 SSRC1 Second operand for instruction. 8 8 SOPC_INST_LITERAL 64 0000000000000000000000000000000011111111111111110000000000000000 0000000000000000000000000000000010111111000000000000000000000000 0000000000000000000000000000000010111111000000010000000000000000 0000000000000000000000000000000010111111000000100000000000000000 0000000000000000000000000000000010111111000000110000000000000000 0000000000000000000000000000000010111111000001000000000000000000 0000000000000000000000000000000010111111000001010000000000000000 0000000000000000000000000000000010111111000001100000000000000000 0000000000000000000000000000000010111111000001110000000000000000 0000000000000000000000000000000010111111000010000000000000000000 0000000000000000000000000000000010111111000010010000000000000000 0000000000000000000000000000000010111111000010100000000000000000 0000000000000000000000000000000010111111000010110000000000000000 0000000000000000000000000000000010111111000011000000000000000000 0000000000000000000000000000000010111111000011010000000000000000 0000000000000000000000000000000010111111000011100000000000000000 0000000000000000000000000000000010111111000011110000000000000000 0000000000000000000000000000000010111111000100100000000000000000 0000000000000000000000000000000010111111000100110000000000000000 has_lit_0 && == .fieldderef .fieldderef INST SOPC SSRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST SOPC SSRC1 I 32 255 I 32 U 1 U 1 has_lit_1 && != .fieldderef .fieldderef INST SOPC SSRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST SOPC SSRC1 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1 && == .fieldderef .fieldderef INST SOPC SSRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST SOPC SSRC1 I 32 255 I 32 U 1 U 1 Scalar ALU comparison operations with two sources. Allowed patterns: SOPC (32 bits) SOPC + LITERAL (64 bits) ENCODING Encoding. 9 23 OP Opcode. 7 16 SIMM32 32-bit literal constant. 32 32 SSRC0 First operand for instruction. 8 0 SSRC1 Second operand for instruction. 8 8 SOPK_INST_LITERAL 64 0000000000000000000000000000000011111111100000000000000000000000 0000000000000000000000000000000010111010100000000000000000000000 default 1 U 1 Scalar ALU operations with one destination and one 16-bit constant source. Allowed patterns: SOPK (32 bits) SOPK + LITERAL (64 bits) ENCODING Encoding. 4 28 OP Opcode. 5 23 SDST Destination for instruction. 7 16 SIMM16 16-bit integer input for opcode. Signedness is determined by opcode. 16 0 SIMM32 32-bit literal constant. 32 32 VOP3_INST_LITERAL 96 000000000000000000000000000000000000000000000000000000000000000011111111111111110000000000000000 000000000000000000000000000000000000000000000000000000000000000011010110000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000011010110000000010000000000000000 000000000000000000000000000000000000000000000000000000000000000011010110000000100000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101100000010000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101100000100000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101100000110000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101100001000000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101100001010000000000000000 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I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_1 && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1 && && == .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_2 && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_2 && && == .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_1_has_lit_2 && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1_has_lit_2 && && == .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 Vector ALU operations requiring three sources or modifiers; also some obscure opcodes that cannot be encoded in smaller instructions due to limited OP bits. Almost all VOP1, VOP2, VOPC and VINTRP opcodes can be promoted to VOP3 to use input and output modifiers. Allowed patterns: VOP3 (64 bits) VOP3 + LITERAL (96 bits) ABS If ABS[N] set, take the floating-point absolute value of the N'th input operand. This is applied before negation. 3 8 CLAMP If set, clamp output to [0.0, 1.0]. Applied after output modifier. 1 15 ENCODING Encoding. 6 26 NEG If NEG[N] set, take the floating-point negation of the N'th input operand. This is applied after absolute value. 3 61 OMOD Output modifier for instruction. Applied before clamping. 2 59 OP Opcode. 10 16 OP_SEL OP_SEL [0,1,2] to select src0,src1,src2 lower[0:15] or higher order[16:31] bits. OP_SEL[3] to select destination.If 0 select [0:15] If 1 select [16:31].For destination 0 sets higher order bits to zero and [0:15] is result. If 1 result in higher order bits and bits preserved in [0:15]. 4 11 SIMM32 32-bit literal constant. 32 64 SRC0 First operand for instruction. 9 32 SRC1 Second operand for instruction. 9 41 SRC2 Third operand for instruction. 9 50 VDST Destination for instruction. 8 0 VOP1_VOP_DPP16 64 0000000000000000000000000000000011111110000000011111111000000000 0000000000000000000000000000000001111110000000000000001000000000 0000000000000000000000000000000001111110000000000000101000000000 0000000000000000000000000000000001111110000000000000110000000000 0000000000000000000000000000000001111110000000000000111000000000 0000000000000000000000000000000001111110000000000001000000000000 0000000000000000000000000000000001111110000000000001010000000000 0000000000000000000000000000000001111110000000000001011000000000 0000000000000000000000000000000001111110000000000001100000000000 0000000000000000000000000000000001111110000000000001101000000000 0000000000000000000000000000000001111110000000000001110000000000 0000000000000000000000000000000001111110000000000010001000000000 0000000000000000000000000000000001111110000000000010010000000000 0000000000000000000000000000000001111110000000000010011000000000 0000000000000000000000000000000001111110000000000010100000000000 0000000000000000000000000000000001111110000000000100000000000000 0000000000000000000000000000000001111110000000000100001000000000 0000000000000000000000000000000001111110000000000100010000000000 0000000000000000000000000000000001111110000000000100011000000000 0000000000000000000000000000000001111110000000000100100000000000 0000000000000000000000000000000001111110000000000100101000000000 0000000000000000000000000000000001111110000000000100111000000000 0000000000000000000000000000000001111110000000000101010000000000 0000000000000000000000000000000001111110000000000101011000000000 0000000000000000000000000000000001111110000000000101110000000000 0000000000000000000000000000000001111110000000000110011000000000 0000000000000000000000000000000001111110000000000110101000000000 0000000000000000000000000000000001111110000000000110110000000000 0000000000000000000000000000000001111110000000000110111000000000 0000000000000000000000000000000001111110000000000111000000000000 0000000000000000000000000000000001111110000000000111001000000000 0000000000000000000000000000000001111110000000000111010000000000 0000000000000000000000000000000001111110000000000111011000000000 0000000000000000000000000000000001111110000000000111111000000000 0000000000000000000000000000000001111110000000001000000000000000 0000000000000000000000000000000001111110000000001000010000000000 0000000000000000000000000000000001111110000000001000011000000000 0000000000000000000000000000000001111110000000001000100000000000 0000000000000000000000000000000001111110000000001001000000000000 0000000000000000000000000000000001111110000000001010000000000000 0000000000000000000000000000000001111110000000001010001000000000 0000000000000000000000000000000001111110000000001010010000000000 0000000000000000000000000000000001111110000000001010011000000000 0000000000000000000000000000000001111110000000001010100000000000 0000000000000000000000000000000001111110000000001010101000000000 0000000000000000000000000000000001111110000000001010110000000000 0000000000000000000000000000000001111110000000001010111000000000 0000000000000000000000000000000001111110000000001011000000000000 0000000000000000000000000000000001111110000000001011001000000000 0000000000000000000000000000000001111110000000001011010000000000 0000000000000000000000000000000001111110000000001011011000000000 0000000000000000000000000000000001111110000000001011100000000000 0000000000000000000000000000000001111110000000001011101000000000 0000000000000000000000000000000001111110000000001011110000000000 0000000000000000000000000000000001111110000000001011111000000000 0000000000000000000000000000000001111110000000001100000000000000 0000000000000000000000000000000001111110000000001100001000000000 0000000000000000000000000000000001111110000000001100010000000000 0000000000000000000000000000000001111110000000001100011000000000 0000000000000000000000000000000001111110000000001100100000000000 default == .fieldderef .fieldderef INST VOP SRC0 I 32 250 I 32 U 1 Vector ALU operations with one destination and one source. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Instructions in this encoding may use SDWA or DPP modes unless otherwise noted. Allowed patterns: VOP1 (32 bits) VOP1 + LITERAL (64 bits) VOP1 + SDWA (64 bits) VOP1 + DPP (64 bits) BANK_MASK Bank enable mask. If bit N is set, then lanes[4*N:4*N+3, 4*N+16:4*N+19, 4*N+32:4*N+35, 4*N+48:4*N+51] are enabled. 4 56 BOUND_CTRL Specifies behaviour when shared data is invalid. 0: set write-enable to zero. 1: set source data to zero. 1 51 DPP_CTRL Data-parallel primitive control. 9 40 ENCODING Encoding. 7 25 FI If true, reads GPRs when fetching data from an inactive lane (Fetch Inactive mode). If false, reads ZERO when fetching data from an inactive lane. 1 50 OP Opcode. 8 9 ROW_MASK Row enable mask. If bit N is set, then lanes[16*N:16*N+15] are enabled. 4 60 SRC0 First operand for instruction. 9 0 SRC0_ABS If true, take the floating-point absolute value of src0. 1 53 SRC0_NEG If true, take the floating-point negation of src0. 1 52 SRC1_ABS If true, take the floating-point absolute value of src1. 1 55 SRC1_NEG If true, take the floating-point negation of src1. 1 54 VDST Destination for instruction. 8 17 VSRC0 VGPR address for src0. 8 32 VOP1_VOP_DPP8 64 0000000000000000000000000000000011111110000000011111111000000000 0000000000000000000000000000000001111110000000000000001000000000 0000000000000000000000000000000001111110000000000000101000000000 0000000000000000000000000000000001111110000000000000110000000000 0000000000000000000000000000000001111110000000000000111000000000 0000000000000000000000000000000001111110000000000001000000000000 0000000000000000000000000000000001111110000000000001010000000000 0000000000000000000000000000000001111110000000000001011000000000 0000000000000000000000000000000001111110000000000001100000000000 0000000000000000000000000000000001111110000000000001101000000000 0000000000000000000000000000000001111110000000000001110000000000 0000000000000000000000000000000001111110000000000010001000000000 0000000000000000000000000000000001111110000000000010010000000000 0000000000000000000000000000000001111110000000000010011000000000 0000000000000000000000000000000001111110000000000010100000000000 0000000000000000000000000000000001111110000000000100000000000000 0000000000000000000000000000000001111110000000000100001000000000 0000000000000000000000000000000001111110000000000100010000000000 0000000000000000000000000000000001111110000000000100011000000000 0000000000000000000000000000000001111110000000000100100000000000 0000000000000000000000000000000001111110000000000100101000000000 0000000000000000000000000000000001111110000000000100111000000000 0000000000000000000000000000000001111110000000000101010000000000 0000000000000000000000000000000001111110000000000101011000000000 0000000000000000000000000000000001111110000000000101110000000000 0000000000000000000000000000000001111110000000000110011000000000 0000000000000000000000000000000001111110000000000110101000000000 0000000000000000000000000000000001111110000000000110110000000000 0000000000000000000000000000000001111110000000000110111000000000 0000000000000000000000000000000001111110000000000111000000000000 0000000000000000000000000000000001111110000000000111001000000000 0000000000000000000000000000000001111110000000000111010000000000 0000000000000000000000000000000001111110000000000111011000000000 0000000000000000000000000000000001111110000000000111111000000000 0000000000000000000000000000000001111110000000001000000000000000 0000000000000000000000000000000001111110000000001000010000000000 0000000000000000000000000000000001111110000000001000011000000000 0000000000000000000000000000000001111110000000001000100000000000 0000000000000000000000000000000001111110000000001001000000000000 0000000000000000000000000000000001111110000000001010000000000000 0000000000000000000000000000000001111110000000001010001000000000 0000000000000000000000000000000001111110000000001010010000000000 0000000000000000000000000000000001111110000000001010011000000000 0000000000000000000000000000000001111110000000001010100000000000 0000000000000000000000000000000001111110000000001010101000000000 0000000000000000000000000000000001111110000000001010110000000000 0000000000000000000000000000000001111110000000001010111000000000 0000000000000000000000000000000001111110000000001011000000000000 0000000000000000000000000000000001111110000000001011001000000000 0000000000000000000000000000000001111110000000001011010000000000 0000000000000000000000000000000001111110000000001011011000000000 0000000000000000000000000000000001111110000000001011100000000000 0000000000000000000000000000000001111110000000001011101000000000 0000000000000000000000000000000001111110000000001011110000000000 0000000000000000000000000000000001111110000000001011111000000000 0000000000000000000000000000000001111110000000001100000000000000 0000000000000000000000000000000001111110000000001100001000000000 0000000000000000000000000000000001111110000000001100010000000000 0000000000000000000000000000000001111110000000001100011000000000 0000000000000000000000000000000001111110000000001100100000000000 default || == .fieldderef .fieldderef INST VOP SRC0 I 32 233 I 32 U 1 == .fieldderef .fieldderef INST VOP SRC0 I 32 234 I 32 U 1 U 1 Vector ALU operations with one destination and one source. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Instructions in this encoding may use SDWA or DPP modes unless otherwise noted. Allowed patterns: VOP1 (32 bits) VOP1 + LITERAL (64 bits) VOP1 + SDWA (64 bits) VOP1 + DPP (64 bits) ENCODING Encoding. 7 25 LANE_SEL_0 Specify which lane to read from for first lane in the 8-lane group. 3 40 LANE_SEL_1 Specify which lane to read from for second lane in the 8-lane group. 3 43 LANE_SEL_2 Specify which lane to read from for third lane in the 8-lane group. 3 46 LANE_SEL_3 Specify which lane to read from for fourth lane in the 8-lane group. 3 49 LANE_SEL_4 Specify which lane to read from for fifth lane in the 8-lane group. 3 52 LANE_SEL_5 Specify which lane to read from for sixth lane in the 8-lane group. 3 55 LANE_SEL_6 Specify which lane to read from for seventh lane in the 8-lane group. 3 58 LANE_SEL_7 Specify which lane to read from for eighth lane in the 8-lane group. 3 61 OP Opcode. 8 9 SRC0 First operand for instruction. 9 0 VDST Destination for instruction. 8 17 VSRC0 VGPR address for src0. 8 32 VOP1_VOP_SDWA 64 0000000000000000000000000000000011111110000000011111111000000000 0000000000000000000000000000000001111110000000000000001000000000 0000000000000000000000000000000001111110000000000000101000000000 0000000000000000000000000000000001111110000000000000110000000000 0000000000000000000000000000000001111110000000000000111000000000 0000000000000000000000000000000001111110000000000001000000000000 0000000000000000000000000000000001111110000000000001010000000000 0000000000000000000000000000000001111110000000000001011000000000 0000000000000000000000000000000001111110000000000001100000000000 0000000000000000000000000000000001111110000000000001101000000000 0000000000000000000000000000000001111110000000000001110000000000 0000000000000000000000000000000001111110000000000010001000000000 0000000000000000000000000000000001111110000000000010010000000000 0000000000000000000000000000000001111110000000000010011000000000 0000000000000000000000000000000001111110000000000010100000000000 0000000000000000000000000000000001111110000000000100000000000000 0000000000000000000000000000000001111110000000000100001000000000 0000000000000000000000000000000001111110000000000100010000000000 0000000000000000000000000000000001111110000000000100011000000000 0000000000000000000000000000000001111110000000000100100000000000 0000000000000000000000000000000001111110000000000100101000000000 0000000000000000000000000000000001111110000000000100111000000000 0000000000000000000000000000000001111110000000000101010000000000 0000000000000000000000000000000001111110000000000101011000000000 0000000000000000000000000000000001111110000000000101110000000000 0000000000000000000000000000000001111110000000000110011000000000 0000000000000000000000000000000001111110000000000110101000000000 0000000000000000000000000000000001111110000000000110110000000000 0000000000000000000000000000000001111110000000000110111000000000 0000000000000000000000000000000001111110000000000111000000000000 0000000000000000000000000000000001111110000000000111001000000000 0000000000000000000000000000000001111110000000000111010000000000 0000000000000000000000000000000001111110000000000111011000000000 0000000000000000000000000000000001111110000000000111111000000000 0000000000000000000000000000000001111110000000001000000000000000 0000000000000000000000000000000001111110000000001000010000000000 0000000000000000000000000000000001111110000000001000011000000000 0000000000000000000000000000000001111110000000001000100000000000 0000000000000000000000000000000001111110000000001001000000000000 0000000000000000000000000000000001111110000000001010000000000000 0000000000000000000000000000000001111110000000001010001000000000 0000000000000000000000000000000001111110000000001010010000000000 0000000000000000000000000000000001111110000000001010011000000000 0000000000000000000000000000000001111110000000001010100000000000 0000000000000000000000000000000001111110000000001010101000000000 0000000000000000000000000000000001111110000000001010110000000000 0000000000000000000000000000000001111110000000001010111000000000 0000000000000000000000000000000001111110000000001011000000000000 0000000000000000000000000000000001111110000000001011001000000000 0000000000000000000000000000000001111110000000001011010000000000 0000000000000000000000000000000001111110000000001011011000000000 0000000000000000000000000000000001111110000000001011100000000000 0000000000000000000000000000000001111110000000001011101000000000 0000000000000000000000000000000001111110000000001011110000000000 0000000000000000000000000000000001111110000000001011111000000000 0000000000000000000000000000000001111110000000001100000000000000 0000000000000000000000000000000001111110000000001100001000000000 0000000000000000000000000000000001111110000000001100010000000000 0000000000000000000000000000000001111110000000001100011000000000 0000000000000000000000000000000001111110000000001100100000000000 default == .fieldderef .fieldderef INST VOP SRC0 I 32 249 I 32 U 1 Vector ALU operations with one destination and one source. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Instructions in this encoding may use SDWA or DPP modes unless otherwise noted. Allowed patterns: VOP1 (32 bits) VOP1 + LITERAL (64 bits) VOP1 + SDWA (64 bits) VOP1 + DPP (64 bits) CLAMP If true, clamp output. 1 45 DST_SEL Destination data select. 3 40 DST_UNUSED Format for unused destination bits. 2 43 ENCODING Encoding. 7 25 OMOD Output modifier for instruction. 2 46 OP Opcode. 8 9 S0 If 0 src0 is VGPR address. If 1 src0 is SGPR or built in inline constant. 1 55 S1 If 0 src1 in VOP2/VOPC is VGPR address. If 1 src1 is SGPR or built in inline constant. 1 63 SRC0 First operand for instruction. 9 0 SRC0_ABS If true, take the floating-point absolute value of src0. 1 53 SRC0_NEG If true, take the floating-point negation of src0. 1 52 SRC0_SEL Source data select for src0. 3 48 SRC0_SEXT If true, sign-extend data for src0. If false, zero-extend. 1 51 SRC1_ABS If true, take the floating-point absolute value of src1. 1 61 SRC1_NEG If true, take the floating-point negation of src1. 1 60 SRC1_SEL Source data select for src1. 3 56 SRC1_SEXT If true, sign-extend data for src1. If false, zero-extend. 1 59 VDST Destination for instruction. 8 17 VSRC0 VGPR address for src0. 8 32 VOP1_INST_LITERAL 64 0000000000000000000000000000000011111110000000011111111000000000 0000000000000000000000000000000001111110000000000000001000000000 0000000000000000000000000000000001111110000000000000010000000000 0000000000000000000000000000000001111110000000000000011000000000 0000000000000000000000000000000001111110000000000000100000000000 0000000000000000000000000000000001111110000000000000101000000000 0000000000000000000000000000000001111110000000000000110000000000 0000000000000000000000000000000001111110000000000000111000000000 0000000000000000000000000000000001111110000000000001000000000000 0000000000000000000000000000000001111110000000000001010000000000 0000000000000000000000000000000001111110000000000001011000000000 0000000000000000000000000000000001111110000000000001100000000000 0000000000000000000000000000000001111110000000000001101000000000 0000000000000000000000000000000001111110000000000001110000000000 0000000000000000000000000000000001111110000000000001111000000000 0000000000000000000000000000000001111110000000000010000000000000 0000000000000000000000000000000001111110000000000010001000000000 0000000000000000000000000000000001111110000000000010010000000000 0000000000000000000000000000000001111110000000000010011000000000 0000000000000000000000000000000001111110000000000010100000000000 0000000000000000000000000000000001111110000000000010101000000000 0000000000000000000000000000000001111110000000000010110000000000 0000000000000000000000000000000001111110000000000010111000000000 0000000000000000000000000000000001111110000000000011000000000000 0000000000000000000000000000000001111110000000000011001000000000 0000000000000000000000000000000001111110000000000011010000000000 0000000000000000000000000000000001111110000000000100000000000000 0000000000000000000000000000000001111110000000000100001000000000 0000000000000000000000000000000001111110000000000100010000000000 0000000000000000000000000000000001111110000000000100011000000000 0000000000000000000000000000000001111110000000000100100000000000 0000000000000000000000000000000001111110000000000100101000000000 0000000000000000000000000000000001111110000000000100111000000000 0000000000000000000000000000000001111110000000000101010000000000 0000000000000000000000000000000001111110000000000101011000000000 0000000000000000000000000000000001111110000000000101110000000000 0000000000000000000000000000000001111110000000000101111000000000 0000000000000000000000000000000001111110000000000110001000000000 0000000000000000000000000000000001111110000000000110011000000000 0000000000000000000000000000000001111110000000000110100000000000 0000000000000000000000000000000001111110000000000110101000000000 0000000000000000000000000000000001111110000000000110110000000000 0000000000000000000000000000000001111110000000000110111000000000 0000000000000000000000000000000001111110000000000111000000000000 0000000000000000000000000000000001111110000000000111001000000000 0000000000000000000000000000000001111110000000000111010000000000 0000000000000000000000000000000001111110000000000111011000000000 0000000000000000000000000000000001111110000000000111100000000000 0000000000000000000000000000000001111110000000000111101000000000 0000000000000000000000000000000001111110000000000111110000000000 0000000000000000000000000000000001111110000000000111111000000000 0000000000000000000000000000000001111110000000001000000000000000 0000000000000000000000000000000001111110000000001000010000000000 0000000000000000000000000000000001111110000000001000011000000000 0000000000000000000000000000000001111110000000001000100000000000 0000000000000000000000000000000001111110000000001001000000000000 0000000000000000000000000000000001111110000000001010000000000000 0000000000000000000000000000000001111110000000001010001000000000 0000000000000000000000000000000001111110000000001010010000000000 0000000000000000000000000000000001111110000000001010011000000000 0000000000000000000000000000000001111110000000001010100000000000 0000000000000000000000000000000001111110000000001010101000000000 0000000000000000000000000000000001111110000000001010110000000000 0000000000000000000000000000000001111110000000001010111000000000 0000000000000000000000000000000001111110000000001011000000000000 0000000000000000000000000000000001111110000000001011001000000000 0000000000000000000000000000000001111110000000001011010000000000 0000000000000000000000000000000001111110000000001011011000000000 0000000000000000000000000000000001111110000000001011100000000000 0000000000000000000000000000000001111110000000001011101000000000 0000000000000000000000000000000001111110000000001011110000000000 0000000000000000000000000000000001111110000000001011111000000000 0000000000000000000000000000000001111110000000001100000000000000 0000000000000000000000000000000001111110000000001100001000000000 0000000000000000000000000000000001111110000000001100010000000000 0000000000000000000000000000000001111110000000001100011000000000 0000000000000000000000000000000001111110000000001100100000000000 has_lit == .fieldderef .fieldderef INST VOP1 SRC0 I 32 255 I 32 U 1 Vector ALU operations with one destination and one source. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Instructions in this encoding may use SDWA or DPP modes unless otherwise noted. Allowed patterns: VOP1 (32 bits) VOP1 + LITERAL (64 bits) VOP1 + SDWA (64 bits) VOP1 + DPP (64 bits) ENCODING Encoding. 7 25 OP Opcode. 8 9 SIMM32 32-bit literal constant. 32 32 SRC0 First operand for instruction. 9 0 VDST Destination for instruction. 8 17 VOP2_VOP_DPP16 64 0000000000000000000000000000000011111110000000000000000000000000 0000000000000000000000000000000000000010000000000000000000000000 0000000000000000000000000000000000000100000000000000000000000000 0000000000000000000000000000000000000110000000000000000000000000 0000000000000000000000000000000000001000000000000000000000000000 0000000000000000000000000000000000001010000000000000000000000000 0000000000000000000000000000000000001110000000000000000000000000 0000000000000000000000000000000000010000000000000000000000000000 0000000000000000000000000000000000010010000000000000000000000000 0000000000000000000000000000000000010100000000000000000000000000 0000000000000000000000000000000000010110000000000000000000000000 0000000000000000000000000000000000011000000000000000000000000000 0000000000000000000000000000000000011010000000000000000000000000 0000000000000000000000000000000000011110000000000000000000000000 0000000000000000000000000000000000100000000000000000000000000000 0000000000000000000000000000000000100010000000000000000000000000 0000000000000000000000000000000000100100000000000000000000000000 0000000000000000000000000000000000100110000000000000000000000000 0000000000000000000000000000000000101000000000000000000000000000 0000000000000000000000000000000000101100000000000000000000000000 0000000000000000000000000000000000110000000000000000000000000000 0000000000000000000000000000000000110100000000000000000000000000 0000000000000000000000000000000000110110000000000000000000000000 0000000000000000000000000000000000111000000000000000000000000000 0000000000000000000000000000000000111010000000000000000000000000 0000000000000000000000000000000000111100000000000000000000000000 0000000000000000000000000000000000111110000000000000000000000000 0000000000000000000000000000000001001010000000000000000000000000 0000000000000000000000000000000001001100000000000000000000000000 0000000000000000000000000000000001001110000000000000000000000000 0000000000000000000000000000000001010000000000000000000000000000 0000000000000000000000000000000001010010000000000000000000000000 0000000000000000000000000000000001010100000000000000000000000000 0000000000000000000000000000000001010110000000000000000000000000 0000000000000000000000000000000001011110000000000000000000000000 0000000000000000000000000000000001100100000000000000000000000000 0000000000000000000000000000000001100110000000000000000000000000 0000000000000000000000000000000001101000000000000000000000000000 0000000000000000000000000000000001101010000000000000000000000000 0000000000000000000000000000000001101100000000000000000000000000 0000000000000000000000000000000001110010000000000000000000000000 0000000000000000000000000000000001110100000000000000000000000000 0000000000000000000000000000000001110110000000000000000000000000 0000000000000000000000000000000001111000000000000000000000000000 default == .fieldderef .fieldderef INST VOP SRC0 I 32 250 I 32 U 1 Vector ALU operations with one destination and two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. SDWA and DPP modes are allowed unless otherwise noted. Allowed patterns: VOP2 (32 bits) VOP2 + LITERAL (64 bits) VOP2 + SDWA (64 bits) VOP2 + DPP (64 bits) BANK_MASK Bank enable mask. If bit N is set, then lanes[4*N:4*N+3, 4*N+16:4*N+19, 4*N+32:4*N+35, 4*N+48:4*N+51] are enabled. 4 56 BOUND_CTRL Specifies behaviour when shared data is invalid. 0: set write-enable to zero. 1: set source data to zero. 1 51 DPP_CTRL Data-parallel primitive control. 9 40 ENCODING Encoding. 1 31 FI If true, reads GPRs when fetching data from an inactive lane (Fetch Inactive mode). If false, reads ZERO when fetching data from an inactive lane. 1 50 OP Opcode. 6 25 ROW_MASK Row enable mask. If bit N is set, then lanes[16*N:16*N+15] are enabled. 4 60 SRC0 First operand for instruction. 9 0 SRC0_ABS If true, take the floating-point absolute value of src0. 1 53 SRC0_NEG If true, take the floating-point negation of src0. 1 52 SRC1_ABS If true, take the floating-point absolute value of src1. 1 55 SRC1_NEG If true, take the floating-point negation of src1. 1 54 VDST Destination for instruction. 8 17 VSRC0 VGPR address for src0. 8 32 VSRC1 Second operand for instruction. 8 9 VOP2_VOP_DPP8 64 0000000000000000000000000000000011111110000000000000000000000000 0000000000000000000000000000000000000010000000000000000000000000 0000000000000000000000000000000000000100000000000000000000000000 0000000000000000000000000000000000000110000000000000000000000000 0000000000000000000000000000000000001000000000000000000000000000 0000000000000000000000000000000000001010000000000000000000000000 0000000000000000000000000000000000001110000000000000000000000000 0000000000000000000000000000000000010000000000000000000000000000 0000000000000000000000000000000000010010000000000000000000000000 0000000000000000000000000000000000010100000000000000000000000000 0000000000000000000000000000000000010110000000000000000000000000 0000000000000000000000000000000000011000000000000000000000000000 0000000000000000000000000000000000011010000000000000000000000000 0000000000000000000000000000000000011110000000000000000000000000 0000000000000000000000000000000000100000000000000000000000000000 0000000000000000000000000000000000100010000000000000000000000000 0000000000000000000000000000000000100100000000000000000000000000 0000000000000000000000000000000000100110000000000000000000000000 0000000000000000000000000000000000101000000000000000000000000000 0000000000000000000000000000000000101100000000000000000000000000 0000000000000000000000000000000000110000000000000000000000000000 0000000000000000000000000000000000110100000000000000000000000000 0000000000000000000000000000000000110110000000000000000000000000 0000000000000000000000000000000000111000000000000000000000000000 0000000000000000000000000000000000111010000000000000000000000000 0000000000000000000000000000000000111100000000000000000000000000 0000000000000000000000000000000000111110000000000000000000000000 0000000000000000000000000000000001001010000000000000000000000000 0000000000000000000000000000000001001100000000000000000000000000 0000000000000000000000000000000001001110000000000000000000000000 0000000000000000000000000000000001010000000000000000000000000000 0000000000000000000000000000000001010010000000000000000000000000 0000000000000000000000000000000001010100000000000000000000000000 0000000000000000000000000000000001010110000000000000000000000000 0000000000000000000000000000000001011110000000000000000000000000 0000000000000000000000000000000001100100000000000000000000000000 0000000000000000000000000000000001100110000000000000000000000000 0000000000000000000000000000000001101000000000000000000000000000 0000000000000000000000000000000001101010000000000000000000000000 0000000000000000000000000000000001101100000000000000000000000000 0000000000000000000000000000000001110010000000000000000000000000 0000000000000000000000000000000001110100000000000000000000000000 0000000000000000000000000000000001110110000000000000000000000000 0000000000000000000000000000000001111000000000000000000000000000 default || == .fieldderef .fieldderef INST VOP SRC0 I 32 233 I 32 U 1 == .fieldderef .fieldderef INST VOP SRC0 I 32 234 I 32 U 1 U 1 Vector ALU operations with one destination and two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. SDWA and DPP modes are allowed unless otherwise noted. Allowed patterns: VOP2 (32 bits) VOP2 + LITERAL (64 bits) VOP2 + SDWA (64 bits) VOP2 + DPP (64 bits) ENCODING Encoding. 1 31 LANE_SEL_0 Specify which lane to read from for first lane in the 8-lane group. 3 40 LANE_SEL_1 Specify which lane to read from for second lane in the 8-lane group. 3 43 LANE_SEL_2 Specify which lane to read from for third lane in the 8-lane group. 3 46 LANE_SEL_3 Specify which lane to read from for fourth lane in the 8-lane group. 3 49 LANE_SEL_4 Specify which lane to read from for fifth lane in the 8-lane group. 3 52 LANE_SEL_5 Specify which lane to read from for sixth lane in the 8-lane group. 3 55 LANE_SEL_6 Specify which lane to read from for seventh lane in the 8-lane group. 3 58 LANE_SEL_7 Specify which lane to read from for eighth lane in the 8-lane group. 3 61 OP Opcode. 6 25 SRC0 First operand for instruction. 9 0 VDST Destination for instruction. 8 17 VSRC0 VGPR address for src0. 8 32 VSRC1 Second operand for instruction. 8 9 VOP2_VOP_SDWA 64 0000000000000000000000000000000011111110000000000000000000000000 0000000000000000000000000000000000000010000000000000000000000000 0000000000000000000000000000000000000110000000000000000000000000 0000000000000000000000000000000000001000000000000000000000000000 0000000000000000000000000000000000001010000000000000000000000000 0000000000000000000000000000000000001110000000000000000000000000 0000000000000000000000000000000000010000000000000000000000000000 0000000000000000000000000000000000010010000000000000000000000000 0000000000000000000000000000000000010100000000000000000000000000 0000000000000000000000000000000000010110000000000000000000000000 0000000000000000000000000000000000011000000000000000000000000000 0000000000000000000000000000000000011110000000000000000000000000 0000000000000000000000000000000000100000000000000000000000000000 0000000000000000000000000000000000100010000000000000000000000000 0000000000000000000000000000000000100100000000000000000000000000 0000000000000000000000000000000000100110000000000000000000000000 0000000000000000000000000000000000101000000000000000000000000000 0000000000000000000000000000000000101100000000000000000000000000 0000000000000000000000000000000000110000000000000000000000000000 0000000000000000000000000000000000110100000000000000000000000000 0000000000000000000000000000000000110110000000000000000000000000 0000000000000000000000000000000000111000000000000000000000000000 0000000000000000000000000000000000111010000000000000000000000000 0000000000000000000000000000000000111100000000000000000000000000 0000000000000000000000000000000001001010000000000000000000000000 0000000000000000000000000000000001001100000000000000000000000000 0000000000000000000000000000000001001110000000000000000000000000 0000000000000000000000000000000001011110000000000000000000000000 0000000000000000000000000000000001100100000000000000000000000000 0000000000000000000000000000000001100110000000000000000000000000 0000000000000000000000000000000001101000000000000000000000000000 0000000000000000000000000000000001101010000000000000000000000000 0000000000000000000000000000000001110010000000000000000000000000 0000000000000000000000000000000001110100000000000000000000000000 0000000000000000000000000000000001110110000000000000000000000000 default == .fieldderef .fieldderef INST VOP SRC0 I 32 249 I 32 U 1 Vector ALU operations with one destination and two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. SDWA and DPP modes are allowed unless otherwise noted. Allowed patterns: VOP2 (32 bits) VOP2 + LITERAL (64 bits) VOP2 + SDWA (64 bits) VOP2 + DPP (64 bits) CLAMP If true, clamp output. 1 45 DST_SEL Destination data select. 3 40 DST_UNUSED Format for unused destination bits. 2 43 ENCODING Encoding. 1 31 OMOD Output modifier for instruction. 2 46 OP Opcode. 6 25 S0 If 0 src0 is VGPR address. If 1 src0 is SGPR or built in inline constant. 1 55 S1 If 0 src1 in VOP2/VOPC is VGPR address. If 1 src1 is SGPR or built in inline constant. 1 63 SRC0 First operand for instruction. 9 0 SRC0_ABS If true, take the floating-point absolute value of src0. 1 53 SRC0_NEG If true, take the floating-point negation of src0. 1 52 SRC0_SEL Source data select for src0. 3 48 SRC0_SEXT If true, sign-extend data for src0. If false, zero-extend. 1 51 SRC1_ABS If true, take the floating-point absolute value of src1. 1 61 SRC1_NEG If true, take the floating-point negation of src1. 1 60 SRC1_SEL Source data select for src1. 3 56 SRC1_SEXT If true, sign-extend data for src1. If false, zero-extend. 1 59 VDST Destination for instruction. 8 17 VSRC0 VGPR address for src0. 8 32 VSRC1 Second operand for instruction. 8 9 VOP2_INST_LITERAL 64 0000000000000000000000000000000011111110000000000000000000000000 0000000000000000000000000000000000000010000000000000000000000000 0000000000000000000000000000000000000100000000000000000000000000 0000000000000000000000000000000000000110000000000000000000000000 0000000000000000000000000000000000001000000000000000000000000000 0000000000000000000000000000000000001010000000000000000000000000 0000000000000000000000000000000000001100000000000000000000000000 0000000000000000000000000000000000001110000000000000000000000000 0000000000000000000000000000000000010000000000000000000000000000 0000000000000000000000000000000000010010000000000000000000000000 0000000000000000000000000000000000010100000000000000000000000000 0000000000000000000000000000000000010110000000000000000000000000 0000000000000000000000000000000000011000000000000000000000000000 0000000000000000000000000000000000011010000000000000000000000000 0000000000000000000000000000000000011110000000000000000000000000 0000000000000000000000000000000000100000000000000000000000000000 0000000000000000000000000000000000100010000000000000000000000000 0000000000000000000000000000000000100100000000000000000000000000 0000000000000000000000000000000000100110000000000000000000000000 0000000000000000000000000000000000101000000000000000000000000000 0000000000000000000000000000000000101100000000000000000000000000 0000000000000000000000000000000000110000000000000000000000000000 0000000000000000000000000000000000110100000000000000000000000000 0000000000000000000000000000000000110110000000000000000000000000 0000000000000000000000000000000000111000000000000000000000000000 0000000000000000000000000000000000111010000000000000000000000000 0000000000000000000000000000000000111100000000000000000000000000 0000000000000000000000000000000000111110000000000000000000000000 0000000000000000000000000000000001000000000000000000000000000000 0000000000000000000000000000000001000010000000000000000000000000 0000000000000000000000000000000001001010000000000000000000000000 0000000000000000000000000000000001001100000000000000000000000000 0000000000000000000000000000000001001110000000000000000000000000 0000000000000000000000000000000001010000000000000000000000000000 0000000000000000000000000000000001010010000000000000000000000000 0000000000000000000000000000000001010100000000000000000000000000 0000000000000000000000000000000001010110000000000000000000000000 0000000000000000000000000000000001011000000000000000000000000000 0000000000000000000000000000000001011010000000000000000000000000 0000000000000000000000000000000001011110000000000000000000000000 0000000000000000000000000000000001100100000000000000000000000000 0000000000000000000000000000000001100110000000000000000000000000 0000000000000000000000000000000001101000000000000000000000000000 0000000000000000000000000000000001101010000000000000000000000000 0000000000000000000000000000000001101100000000000000000000000000 0000000000000000000000000000000001101110000000000000000000000000 0000000000000000000000000000000001110000000000000000000000000000 0000000000000000000000000000000001110010000000000000000000000000 0000000000000000000000000000000001110100000000000000000000000000 0000000000000000000000000000000001110110000000000000000000000000 0000000000000000000000000000000001111000000000000000000000000000 has_lit == .fieldderef .fieldderef INST VOP2 SRC0 I 32 255 I 32 U 1 default && && && != .fieldderef .fieldderef INST VOP2 SRC0 I 32 250 I 32 U 1 && != .fieldderef .fieldderef INST VOP2 SRC0 I 32 233 I 32 U 1 != .fieldderef .fieldderef INST VOP2 SRC0 I 32 234 I 32 U 1 U 1 U 1 != .fieldderef .fieldderef INST VOP2 SRC0 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP2 SRC0 I 32 249 I 32 U 1 U 1 Vector ALU operations with one destination and two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. SDWA and DPP modes are allowed unless otherwise noted. Allowed patterns: VOP2 (32 bits) VOP2 + LITERAL (64 bits) VOP2 + SDWA (64 bits) VOP2 + DPP (64 bits) ENCODING Encoding. 1 31 OP Opcode. 6 25 SIMM32 32-bit literal constant. 32 32 SRC0 First operand for instruction. 9 0 VDST Destination for instruction. 8 17 VSRC1 Second operand for instruction. 8 9 VOP2_VOP_SDWA_SDST_ENC 64 0000000000000000000000000000000011111110000000000000000000000000 0000000000000000000000000000000001010000000000000000000000000000 0000000000000000000000000000000001010010000000000000000000000000 0000000000000000000000000000000001010100000000000000000000000000 default == .fieldderef .fieldderef INST VOP SRC0 I 32 249 I 32 U 1 Vector ALU operations with one destination and two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. SDWA and DPP modes are allowed unless otherwise noted. Allowed patterns: VOP2 (32 bits) VOP2 + LITERAL (64 bits) VOP2 + SDWA (64 bits) VOP2 + DPP (64 bits) ENCODING Encoding. 1 31 OP Opcode. 6 25 S0 If 0 src0 is VGPR address. If 1 src0 is SGPR or built in inline constant. 1 55 S1 If 0 src1 in VOP2/VOPC is VGPR address. If 1 src1 is SGPR or built in inline constant. 1 63 SD If 1 then use SDST field. If 0 then write VCC (ops without OPF_WREX flag) or EXEC (ops with OPF_WREX flag). SD must be set to 0 for ops with OPF_WREX flag. 1 47 SDST Destination for compare result. 7 40 SRC0 First operand for instruction. 9 0 SRC0_ABS If true, take the floating-point absolute value of src0. 1 53 SRC0_NEG If true, take the floating-point negation of src0. 1 52 SRC0_SEL Source data select for src0. 3 48 SRC0_SEXT If true, sign-extend data for src0. If false, zero-extend. 1 51 SRC1_ABS If true, take the floating-point absolute value of src1. 1 61 SRC1_NEG If true, take the floating-point negation of src1. 1 60 SRC1_SEL Source data select for src1. 3 56 SRC1_SEXT If true, sign-extend data for src1. If false, zero-extend. 1 59 VDST Destination for instruction. 8 17 VSRC0 VGPR address for src0. 8 32 VSRC1 Second operand for instruction. 8 9 VOP3_SDST_ENC 64 0000000000000000000000000000000011111111111111110000000000000000 0000000000000000000000000000000011010101001010000000000000000000 0000000000000000000000000000000011010101001010010000000000000000 0000000000000000000000000000000011010101001010100000000000000000 0000000000000000000000000000000011010101011011010000000000000000 0000000000000000000000000000000011010101011011100000000000000000 0000000000000000000000000000000011010101011101100000000000000000 0000000000000000000000000000000011010101011101110000000000000000 0000000000000000000000000000000011010111000011110000000000000000 0000000000000000000000000000000011010111000100000000000000000000 0000000000000000000000000000000011010111000110010000000000000000 default && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 Vector ALU operations requiring three sources or modifiers; also some obscure opcodes that cannot be encoded in smaller instructions due to limited OP bits. Almost all VOP1, VOP2, VOPC and VINTRP opcodes can be promoted to VOP3 to use input and output modifiers. Allowed patterns: VOP3 (64 bits) VOP3 + LITERAL (96 bits) CLAMP If set, clamp output to [0.0, 1.0]. Applied after output modifier. 1 15 ENCODING Encoding. 6 26 NEG If NEG[N] set, take the floating-point negation of the N'th input operand. This is applied after absolute value. 3 61 OMOD Output modifier for instruction. Applied before clamping. 2 59 OP Opcode. 10 16 SDST Destination for compare result. 7 8 SRC0 First operand for instruction. 9 32 SRC1 Second operand for instruction. 9 41 SRC2 Third operand for instruction. 9 50 VDST Destination for instruction. 8 0 VOP3_SDST_ENC_INST_LITERAL 96 000000000000000000000000000000000000000000000000000000000000000011111111111111110000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101001010000000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101001010010000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101001010100000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101011011010000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101011011100000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101011101100000000000000000 000000000000000000000000000000000000000000000000000000000000000011010101011101110000000000000000 000000000000000000000000000000000000000000000000000000000000000011010111000011110000000000000000 000000000000000000000000000000000000000000000000000000000000000011010111000100000000000000000000 000000000000000000000000000000000000000000000000000000000000000011010111000110010000000000000000 has_lit_0 && && == .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_1 && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1 && && == .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_2 && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_2 && && == .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_1_has_lit_2 && && != .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1_has_lit_2 && && == .fieldderef .fieldderef INST VOP3 SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3 SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3 SRC2 I 32 255 I 32 U 1 U 1 Vector ALU operations requiring three sources or modifiers; also some obscure opcodes that cannot be encoded in smaller instructions due to limited OP bits. Almost all VOP1, VOP2, VOPC and VINTRP opcodes can be promoted to VOP3 to use input and output modifiers. Allowed patterns: VOP3 (64 bits) VOP3 + LITERAL (96 bits) CLAMP If set, clamp output to [0.0, 1.0]. Applied after output modifier. 1 15 ENCODING Encoding. 6 26 NEG If NEG[N] set, take the floating-point negation of the N'th input operand. This is applied after absolute value. 3 61 OMOD Output modifier for instruction. Applied before clamping. 2 59 OP Opcode. 10 16 SDST Destination for compare result. 7 8 SIMM32 32-bit literal constant. 32 64 SRC0 First operand for instruction. 9 32 SRC1 Second operand for instruction. 9 41 SRC2 Third operand for instruction. 9 50 VDST Destination for instruction. 8 0 VOP3P_INST_LITERAL 96 000000000000000000000000000000000000000000000000000000000000000011111100011111110000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000000010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000000100000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000000110000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000001000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000001010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000001100000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000001110000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000010000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000010010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000010100000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000010110000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000011000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000011010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000011100000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000011110000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000100000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000100010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000100100000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000100110000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000101000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000101010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000101100000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000101110000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000110000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100000110010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100001000000000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100001000010000000000000000 000000000000000000000000000000000000000000000000000000000000000011001100001000100000000000000000 has_lit_0 && && == .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 has_lit_1 && && != .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1 && && == .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 != .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 has_lit_2 && && != .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_2 && && == .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 != .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 has_lit_1_has_lit_2 && && != .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 has_lit_0_has_lit_1_has_lit_2 && && == .fieldderef .fieldderef INST VOP3P SRC0 I 32 255 I 32 U 1 == .fieldderef .fieldderef INST VOP3P SRC1 I 32 255 I 32 U 1 U 1 == .fieldderef .fieldderef INST VOP3P SRC2 I 32 255 I 32 U 1 U 1 Packed math instructions: vector ALU operations requiring two or three sources and performing two 16 bit ops in one instruction. Allowed patterns: VOP3P (64 bits) VOP3P + LITERAL (96 bits) CLAMP If set, clamp output to [0.0, 1.0]. Applied after output modifier. 1 15 ENCODING Encoding. 6 26 NEG If NEG[N] set, take the floating-point negation of the N'th input low opcode. This is applied after absolute value. 3 61 NEG_HI If NEG_HI[N] set, take the floating-point negation of the N'th input high opcode. This is applied after absolute value. 3 8 OP Opcode. 7 16 OP_SEL Input modifier for low opcode src0, src1 and src2. If 0 select src[0:15]. If 1 select src[16:31]. 3 11 OP_SEL_HI Input modifier for high opcode src0 and src1. If 0 select src[0:15]. If 1 select src[16:31]. 2 59 OP_SEL_HI_2 Input modifier for high opcode src2. If 0 select src2[0:15]. If 1 select src2[16:31]. 1 14 SIMM32 32-bit literal constant. 32 64 SRC0 First operand for instruction. 9 32 SRC1 Second operand for instruction. 9 41 SRC2 Third operand for instruction. 9 50 VDST Destination for instruction. 8 0 VOPC_VOP_SDWA_SDST_ENC 64 0000000000000000000000000000000011111111111111100000000000000000 0000000000000000000000000000000001111100000000000000000000000000 0000000000000000000000000000000001111100000000100000000000000000 0000000000000000000000000000000001111100000001000000000000000000 0000000000000000000000000000000001111100000001100000000000000000 0000000000000000000000000000000001111100000010000000000000000000 0000000000000000000000000000000001111100000010100000000000000000 0000000000000000000000000000000001111100000011000000000000000000 0000000000000000000000000000000001111100000011100000000000000000 0000000000000000000000000000000001111100000100000000000000000000 0000000000000000000000000000000001111100000100100000000000000000 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0000000000000000000000000000000001111101110111100000000000000000 0000000000000000000000000000000001111101111100000000000000000000 0000000000000000000000000000000001111101111100100000000000000000 0000000000000000000000000000000001111101111101000000000000000000 0000000000000000000000000000000001111101111101100000000000000000 0000000000000000000000000000000001111101111110000000000000000000 0000000000000000000000000000000001111101111110100000000000000000 0000000000000000000000000000000001111101111111000000000000000000 0000000000000000000000000000000001111101111111100000000000000000 default == .fieldderef .fieldderef INST VOP SRC0 I 32 249 I 32 U 1 Vector ALU comparison operations with two sources. Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Note that vector compare instructions respect the EXEC mask for computing the result in each thread; if EXEC[laneId] is zero, then the comparison for that thread is not performed and the result of VCC[laneId] is zero. SDWA is allowed but DPP is not allowed. Note when using SDWA format, the SDWA_SDST_ENC format must be used; this means the dst_sel, dst_unused, omod and clamp modifiers are unavailable. Allowed patterns: VOPC (32 bits) VOPC + LITERAL (64 bits) VOPC + SDWA (64 bits) ENCODING Encoding. 7 25 OP Opcode. 8 17 S0 If 0 src0 is VGPR address. If 1 src0 is SGPR or built in inline constant. 1 55 S1 If 0 src1 in VOP2/VOPC is VGPR address. If 1 src1 is SGPR or built in inline constant. 1 63 SD If 1 then use SDST field. If 0 then write VCC (ops without OPF_WREX flag) or EXEC (ops with OPF_WREX flag). SD must be set to 0 for ops with OPF_WREX flag. 1 47 SDST Destination for compare result. 7 40 SRC0 First operand for instruction. 9 0 SRC0_ABS If true, take the floating-point absolute value of src0. 1 53 SRC0_NEG If true, take the floating-point negation of src0. 1 52 SRC0_SEL Source data select for src0. 3 48 SRC0_SEXT If true, sign-extend data for src0. If false, zero-extend. 1 51 SRC1_ABS If true, take the floating-point absolute value of src1. 1 61 SRC1_NEG If true, take the floating-point negation of src1. 1 60 SRC1_SEL Source data select for src1. 3 56 SRC1_SEXT If true, sign-extend data for src1. If false, zero-extend. 1 59 VSRC0 VGPR address for src0. 8 32 VSRC1 Second operand for instruction. 8 9 VOPC_INST_LITERAL 64 0000000000000000000000000000000011111111111111100000000000000000 0000000000000000000000000000000001111100000000000000000000000000 0000000000000000000000000000000001111100000000100000000000000000 0000000000000000000000000000000001111100000001000000000000000000 0000000000000000000000000000000001111100000001100000000000000000 0000000000000000000000000000000001111100000010000000000000000000 0000000000000000000000000000000001111100000010100000000000000000 0000000000000000000000000000000001111100000011000000000000000000 0000000000000000000000000000000001111100000011100000000000000000 0000000000000000000000000000000001111100000100000000000000000000 0000000000000000000000000000000001111100000100100000000000000000 0000000000000000000000000000000001111100000101000000000000000000 0000000000000000000000000000000001111100000101100000000000000000 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Instructions in this encoding may be promoted to VOP3 unless otherwise noted. Note that vector compare instructions respect the EXEC mask for computing the result in each thread; if EXEC[laneId] is zero, then the comparison for that thread is not performed and the result of VCC[laneId] is zero. SDWA is allowed but DPP is not allowed. Note when using SDWA format, the SDWA_SDST_ENC format must be used; this means the dst_sel, dst_unused, omod and clamp modifiers are unavailable. Allowed patterns: VOPC (32 bits) VOPC + LITERAL (64 bits) VOPC + SDWA (64 bits) ENCODING Encoding. 7 25 OP Opcode. 8 17 SIMM32 32-bit literal constant. 32 32 SRC0 First operand for instruction. 9 0 VSRC1 Second operand for instruction. 8 9 FALSE FALSE FALSE FALSE FALSE DS_ADD_U32 Add two unsigned 32-bit integer values stored in the data register and a location in a data share. ENC_DS default 0 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_SUB_U32 Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share. ENC_DS default 1 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_RSUB_U32 Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register. ENC_DS default 2 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_INC_U32 Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. ENC_DS default 3 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_DEC_U32 Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value. ENC_DS default 4 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_I32 Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 5 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_I32 OPR_DSMEM 32 FMT_NUM_I32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_I32 Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 6 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_I32 OPR_DSMEM 32 FMT_NUM_I32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_U32 Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 7 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_U32 Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 8 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_AND_B32 Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. ENC_DS default 9 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_OR_B32 Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share. ENC_DS default 10 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_XOR_B32 Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share. ENC_DS default 11 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MSKOR_B32 Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers. ENC_DS default 12 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B32 Store 32 bits of data from a vector input register into a data share. ENC_DS default 13 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE2_B32 Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. ENC_DS default 14 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE2ST64_B32 Store 32 bits of data from one vector input register and then 32 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address. ENC_DS default 15 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_B32 Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 16 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_F32 Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 17 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 DATA1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_F32 Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share. ENC_DS default 18 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_F32 Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. ENC_DS default 19 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_NOP Do nothing. ENC_DS default 20 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_ADD_F32 Add two single-precision float values stored in the data register and a location in a data share. ENC_DS default 21 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_GWS_SEMA_RELEASE_ALL GDS Only: The GWS resource (rid) indicated processes this opcode by updating the counter and labeling the specified resource as a semaphore. ENC_DS default 24 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_GWS_INIT GDS Only: Initialize a barrier or semaphore resource. ENC_DS default 25 ADDR FMT_NUM_B32 OPR_VGPR 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_GWS_SEMA_V GDS Only: The GWS resource indicated processes this opcode by updating the counter and labeling the resource as a semaphore. ENC_DS default 26 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_GWS_SEMA_BR GDS Only: The GWS resource indicated processes this opcode by updating the counter by the bulk release delivered count and labeling the resource as a semaphore. ENC_DS default 27 ADDR FMT_NUM_B32 OPR_VGPR 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_GWS_SEMA_P GDS Only: The GWS resource indicated processes this opcode by queueing it until counter enables a release and then decrementing the counter of the resource as a semaphore. ENC_DS default 28 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_GWS_BARRIER GDS Only: The GWS resource indicated processes this opcode by queueing it until barrier is satisfied. The number of waves needed is passed in as DATA of first valid thread. ENC_DS default 29 ADDR FMT_NUM_B32 OPR_VGPR 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B8 Store 8 bits of data from a vector register into a data share. ENC_DS default 30 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B8 OPR_VGPR 8 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B16 Store 16 bits of data from a vector register into a data share. ENC_DS default 31 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B16 OPR_VGPR 16 FMT_NUM_B16 OPR_DSMEM 16 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_ADD_RTN_U32 Add two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 32 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_SUB_RTN_U32 Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a data share. Store the original value from data share into a vector register. ENC_DS default 33 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_RSUB_RTN_U32 Subtract an unsigned 32-bit integer value stored in a location in a data share from a value stored in the data register. Store the original value from data share into a vector register. ENC_DS default 34 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_INC_RTN_U32 Increment an unsigned 32-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. Store the original value from data share into a vector register. ENC_DS default 35 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_DEC_RTN_U32 Decrement an unsigned 32-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from data share into a vector register. ENC_DS default 36 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_RTN_I32 Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 37 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_I32 OPR_DSMEM 32 FMT_NUM_I32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_RTN_I32 Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 38 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_I32 OPR_DSMEM 32 FMT_NUM_I32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_RTN_U32 Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 39 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_RTN_U32 Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 40 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_U32 OPR_DSMEM 32 FMT_NUM_U32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_AND_RTN_B32 Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 41 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_OR_RTN_B32 Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 42 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_XOR_RTN_B32 Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 43 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MSKOR_RTN_B32 Calculate masked bitwise OR on an unsigned 32-bit integer location in a data share, given mask value and bits to OR in the data registers. ENC_DS default 44 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRXCHG_RTN_B32 Swap an unsigned 32-bit integer value in the data register with a location in a data share. ENC_DS default 45 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRXCHG2_RTN_B32 Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. ENC_DS default 46 VDST FMT_NUM_B32 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRXCHG2ST64_RTN_B32 Swap two unsigned 32-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address. ENC_DS default 47 VDST FMT_NUM_B32 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_RTN_B32 Compare an unsigned 32-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 48 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_RTN_F32 Compare a single-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 49 VDST FMT_NUM_F32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 DATA1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_RTN_F32 Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 50 VDST FMT_NUM_F32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_RTN_F32 Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 51 VDST FMT_NUM_F32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRAP_RTN_B32 Given a minuend from a location in data share and a subtrahend from a vector register, subtract the two values iff the result is nonnegative; otherwise add a value from a second vector register to the memory location. ENC_DS default 52 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 DATA1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_SWIZZLE_B32 Dword swizzle, no data is written to LDS memory. ENC_DS default 53 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_B32 Load 32 bits of data from a data share into a vector register. ENC_DS default 54 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ2_B32 Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register. ENC_DS default 55 VDST FMT_NUM_B32 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ2ST64_B32 Load 32 bits of data from one location in a data share and then 32 bits of data from a second location in a data share and store the results into a 64-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address. ENC_DS default 56 VDST FMT_NUM_B32 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_I8 Load 8 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. ENC_DS default 57 VDST FMT_NUM_B8 OPR_VGPR 8 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_U8 Load 8 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. ENC_DS default 58 VDST FMT_NUM_B8 OPR_VGPR 8 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_I16 Load 16 bits of signed data from a data share, sign extend to 32 bits and store the result into a vector register. ENC_DS default 59 VDST FMT_NUM_B16 OPR_VGPR 16 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B16 OPR_DSMEM 16 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_U16 Load 16 bits of unsigned data from a data share, zero extend to 32 bits and store the result into a vector register. ENC_DS default 60 VDST FMT_NUM_B16 OPR_VGPR 16 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B16 OPR_DSMEM 16 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CONSUME LDS & GDS. Subtract (count_bits(exec_mask)) from the value stored in DS memory at (M0.base + instr_offset). Return the pre-operation value to VGPRs. ENC_DS default 61 VDST FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_APPEND LDS & GDS. Add (count_bits(exec_mask)) to the value stored in DS memory at (M0.base + instr_offset). Return the pre-operation value to VGPRs. ENC_DS default 62 VDST FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_ORDERED_COUNT GDS-only. Add (count_bits(exec_mask)) to one of 4 dedicated ordered-count counters (aka 'packers'). Additional bits of instr.offset field are overloaded to hold packer-id, 'last'. ENC_DS default 63 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_ADD_U64 Add two unsigned 64-bit integer values stored in the data register and a location in a data share. ENC_DS default 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_SUB_U64 Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share. ENC_DS default 65 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_RSUB_U64 Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register. ENC_DS default 66 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_INC_U64 Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. ENC_DS default 67 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_DEC_U64 Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value. ENC_DS default 68 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_I64 Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 69 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_I64 OPR_DSMEM 64 FMT_NUM_I64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_I64 Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 70 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_I64 OPR_DSMEM 64 FMT_NUM_I64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_U64 Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 71 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_U64 Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. ENC_DS default 72 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_AND_B64 Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. ENC_DS default 73 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_OR_B64 Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share. ENC_DS default 74 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_XOR_B64 Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share. ENC_DS default 75 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MSKOR_B64 Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers. ENC_DS default 76 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B64 Store 64 bits of data from a vector input register into a data share. ENC_DS default 77 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE2_B64 Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. ENC_DS default 78 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE2ST64_B64 Store 64 bits of data from one vector input register and then 64 bits of data from a second vector input register into a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address. ENC_DS default 79 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_B64 Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 80 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_F64 Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 81 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F64 OPR_VGPR 64 DATA1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_F64 OPR_DSMEM 64 FMT_NUM_F64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_F64 Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share. ENC_DS default 82 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_F64 OPR_DSMEM 64 FMT_NUM_F64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_F64 Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. ENC_DS default 83 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_F64 OPR_DSMEM 64 FMT_NUM_F64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_ADD_RTN_F32 Add two single-precision float values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 85 VDST FMT_NUM_F32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_DSMEM 32 FMT_NUM_F32 OPR_DSMEM 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_ADD_RTN_U64 Add two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 96 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_SUB_RTN_U64 Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a data share. Store the original value from data share into a vector register. ENC_DS default 97 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_RSUB_RTN_U64 Subtract an unsigned 64-bit integer value stored in a location in a data share from a value stored in the data register. Store the original value from data share into a vector register. ENC_DS default 98 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_INC_RTN_U64 Increment an unsigned 64-bit integer value from a location in a data share with wraparound to 0 if the value exceeds a value in the data register. Store the original value from data share into a vector register. ENC_DS default 99 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_DEC_RTN_U64 Decrement an unsigned 64-bit integer value from a location in a data share with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from data share into a vector register. ENC_DS default 100 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_RTN_I64 Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 101 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_I64 OPR_DSMEM 64 FMT_NUM_I64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_RTN_I64 Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 102 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_I64 OPR_DSMEM 64 FMT_NUM_I64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_RTN_U64 Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 103 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_RTN_U64 Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 104 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_U64 OPR_DSMEM 64 FMT_NUM_U64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_AND_RTN_B64 Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 105 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_OR_RTN_B64 Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 106 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_XOR_RTN_B64 Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 107 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MSKOR_RTN_B64 Calculate masked bitwise OR on an unsigned 64-bit integer location in a data share, given mask value and bits to OR in the data registers. ENC_DS default 108 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRXCHG_RTN_B64 Swap an unsigned 64-bit integer value in the data register with a location in a data share. ENC_DS default 109 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRXCHG2_RTN_B64 Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. ENC_DS default 110 VDST FMT_NUM_B64 OPR_VGPR 128 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRXCHG2ST64_RTN_B64 Swap two unsigned 64-bit integer values in the data registers with two locations in a data share. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address. ENC_DS default 111 VDST FMT_NUM_B64 OPR_VGPR 128 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_RTN_B64 Compare an unsigned 64-bit integer value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 112 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 DATA1 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CMPST_RTN_F64 Compare a double-precision float value in the data comparison register with a location in a data share, and modify the memory location with a value in the data source register if the comparison is equal. ENC_DS default 113 VDST FMT_NUM_F64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F64 OPR_VGPR 64 DATA1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_F64 OPR_DSMEM 64 FMT_NUM_F64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MIN_RTN_F64 Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 114 VDST FMT_NUM_F64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_F64 OPR_DSMEM 64 FMT_NUM_F64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_MAX_RTN_F64 Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a data share. Store the original value from data share into a vector register. ENC_DS default 115 VDST FMT_NUM_F64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_F64 OPR_DSMEM 64 FMT_NUM_F64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_B64 Load 64 bits of data from a data share into a vector register. ENC_DS default 118 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ2_B64 Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register. ENC_DS default 119 VDST FMT_NUM_B64 OPR_VGPR 128 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ2ST64_B64 Load 64 bits of data from one location in a data share and then 64 bits of data from a second location in a data share and store the results into a 128-bit vector register. Treat each offset as an index and multiply by a stride of 64 elements (256 bytes) to generate an offset for each DS address. ENC_DS default 120 VDST FMT_NUM_B64 OPR_VGPR 128 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_CONDXCHG32_RTN_B64 Perform 2 conditional write exchanges, where each conditional write exchange writes a 32 bit value from a data register to a location in data share iff the most significant bit of the data value is set. ENC_DS default 126 VDST FMT_NUM_B64 OPR_VGPR 64 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B64 OPR_VGPR 64 FMT_NUM_B64 OPR_DSMEM 64 FMT_NUM_B64 OPR_DSMEM 64 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B8_D16_HI Store 8 bits of data from the high bits of a vector register into a data share. ENC_DS default 160 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B8 OPR_VGPR 8 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B16_D16_HI Store 16 bits of data from the high bits of a vector register into a data share. ENC_DS default 161 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B16 OPR_VGPR 16 FMT_NUM_B16 OPR_DSMEM 16 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_U8_D16 Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the low 16 bits of a vector register. ENC_DS default 162 VDST FMT_NUM_B8 OPR_VGPR 8 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_U8_D16_HI Load 8 bits of unsigned data from a data share, zero extend to 16 bits and store the result into the high 16 bits of a vector register. ENC_DS default 163 VDST FMT_NUM_B8 OPR_VGPR 8 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_I8_D16 Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the low 16 bits of a vector register. ENC_DS default 164 VDST FMT_NUM_B8 OPR_VGPR 8 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_I8_D16_HI Load 8 bits of signed data from a data share, sign extend to 16 bits and store the result into the high 16 bits of a vector register. ENC_DS default 165 VDST FMT_NUM_B8 OPR_VGPR 8 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B8 OPR_DSMEM 8 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_U16_D16 Load 16 bits of unsigned data from a data share and store the result into the low 16 bits of a vector register. ENC_DS default 166 VDST FMT_NUM_B16 OPR_VGPR 16 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B16 OPR_DSMEM 16 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_U16_D16_HI Load 16 bits of unsigned data from a data share and store the result into the high 16 bits of a vector register. ENC_DS default 167 VDST FMT_NUM_B16 OPR_VGPR 16 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B16 OPR_DSMEM 16 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_ADDTID_B32 Store 32 bits of data from a vector input register into a data share. The memory base address is provided as an immediate value and the lane ID is used as an offset. ENC_DS default 176 DATA0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_SDST_M0 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_ADDTID_B32 Load 32 bits of data from a data share into a vector register. The memory base address is provided as an immediate value and the lane ID is used as an offset. ENC_DS default 177 VDST FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_DSMEM 32 FMT_NUM_B32 OPR_SDST_M0 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_PERMUTE_B32 Forward permute. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS to implement an arbitrary swizzle across threads in a wavefront. ENC_DS default 178 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_BPERMUTE_B32 Backward permute. This does not access LDS memory and may be called even if no LDS memory is allocated to the wave. It uses LDS hardware to implement an arbitrary swizzle across threads in a wavefront. ENC_DS default 179 VDST FMT_NUM_B32 OPR_VGPR 32 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B32 OPR_VGPR 32 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B96 Store 96 bits of data from a vector input register into a data share. ENC_DS default 222 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B96 OPR_VGPR 96 FMT_NUM_B96 OPR_DSMEM 96 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_WRITE_B128 Store 128 bits of data from a vector input register into a data share. ENC_DS default 223 ADDR FMT_NUM_B32 OPR_VGPR 32 DATA0 FMT_NUM_B128 OPR_VGPR 128 FMT_NUM_B128 OPR_DSMEM 128 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_B96 Load 96 bits of data from a data share into a vector register. ENC_DS default 254 VDST FMT_NUM_B96 OPR_VGPR 96 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B96 OPR_DSMEM 96 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE DS_READ_B128 Load 128 bits of data from a data share into a vector register. ENC_DS default 255 VDST FMT_NUM_B128 OPR_VGPR 128 ADDR FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B128 OPR_DSMEM 128 VMEM DATA_SHARE FALSE FALSE FALSE FALSE FALSE EXP Export graphics data to the next stage of the render pipeline. The target and up to four channels of data are specified as operands. ENC_EXP default 0 TGT FMT_ANY OPR_TGT 128 VSRC0 FMT_ANY OPR_VGPR 32 VSRC1 FMT_ANY OPR_VGPR 32 VSRC2 FMT_ANY OPR_VGPR 32 VSRC3 FMT_ANY OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 EXPORT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_UBYTE Load 8 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register. ENC_FLAT default 8 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_SBYTE Load 8 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register. ENC_FLAT default 9 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_USHORT Load 16 bits of unsigned data from the flat aperture, zero extend to 32 bits and store the result into a vector register. ENC_FLAT default 10 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_SSHORT Load 16 bits of signed data from the flat aperture, sign extend to 32 bits and store the result into a vector register. ENC_FLAT default 11 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_DWORD Load 32 bits of data from the flat aperture into a vector register. ENC_FLAT default 12 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_DWORDX2 Load 64 bits of data from the flat aperture into a vector register. ENC_FLAT default 13 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_DWORDX4 Load 128 bits of data from the flat aperture into a vector register. ENC_FLAT default 14 VDST FMT_ANY OPR_VGPR 128 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_DWORDX3 Load 96 bits of data from the flat aperture into a vector register. ENC_FLAT default 15 VDST FMT_ANY OPR_VGPR 96 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_BYTE Store 8 bits of data from a vector register into the flat aperture. ENC_FLAT default 24 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_BYTE_D16_HI Store 8 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture. ENC_FLAT default 25 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_SHORT Store 16 bits of data from a vector register into the flat aperture. ENC_FLAT default 26 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_SHORT_D16_HI Store 16 bits of data from the high 16 bits of a 32-bit vector register into the flat aperture. ENC_FLAT default 27 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_DWORD Store 32 bits of data from vector input registers into the flat aperture. ENC_FLAT default 28 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_DWORDX2 Store 64 bits of data from vector input registers into the flat aperture. ENC_FLAT default 29 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_DWORDX4 Store 128 bits of data from vector input registers into the flat aperture. ENC_FLAT default 30 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 128 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_STORE_DWORDX3 Store 96 bits of data from vector input registers into the flat aperture. ENC_FLAT default 31 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 96 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_UBYTE_D16 Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT default 32 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_UBYTE_D16_HI Load 8 bits of unsigned data from the flat aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT default 33 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_SBYTE_D16 Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT default 34 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_SBYTE_D16_HI Load 8 bits of signed data from the flat aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT default 35 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_SHORT_D16 Load 16 bits of unsigned data from the flat aperture and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT default 36 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_LOAD_SHORT_D16_HI Load 16 bits of unsigned data from the flat aperture and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT default 37 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SWAP Swap an unsigned 32-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 48 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_CMPSWAP Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 49 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_ADD Add two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 50 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SUB Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 51 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SMIN Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 53 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_UMIN Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 54 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SMAX Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 55 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_UMAX Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 56 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_AND Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 57 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_OR Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 58 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_XOR Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 59 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_INC Increment an unsigned 32-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 60 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_DEC Decrement an unsigned 32-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 61 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_FCMPSWAP Compare two single-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 62 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_FMIN Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 63 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_FMAX Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 64 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SWAP_X2 Swap an unsigned 64-bit integer value in the data register with a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 80 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_CMPSWAP_X2 Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 81 VDST FMT_ANY OPR_VGPR 128 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 128 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_ADD_X2 Add two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 82 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SUB_X2 Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 83 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SMIN_X2 Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 85 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_UMIN_X2 Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 86 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_SMAX_X2 Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 87 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_UMAX_X2 Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 88 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_AND_X2 Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 89 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_OR_X2 Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 90 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_XOR_X2 Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 91 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_INC_X2 Increment an unsigned 64-bit integer value from a location in the flat aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 92 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_DEC_X2 Decrement an unsigned 64-bit integer value from a location in the flat aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 93 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_FCMPSWAP_X2 Compare two double-precision float values stored in the data comparison register and a location in the flat aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 94 VDST FMT_ANY OPR_VGPR 128 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 128 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_FMIN_X2 Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 95 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE FLAT_ATOMIC_FMAX_X2 Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the flat aperture. Store the original value from flat aperture into a vector register iff the GLC bit is set. ENC_FLAT default 96 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_UBYTE Load 8 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register. ENC_FLAT_GLBL default 8 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_SBYTE Load 8 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register. ENC_FLAT_GLBL default 9 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_USHORT Load 16 bits of unsigned data from the global aperture, zero extend to 32 bits and store the result into a vector register. ENC_FLAT_GLBL default 10 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_SSHORT Load 16 bits of signed data from the global aperture, sign extend to 32 bits and store the result into a vector register. ENC_FLAT_GLBL default 11 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_DWORD Load 32 bits of data from the global aperture into a vector register. ENC_FLAT_GLBL default 12 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_DWORDX2 Load 64 bits of data from the global aperture into a vector register. ENC_FLAT_GLBL default 13 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_DWORDX4 Load 128 bits of data from the global aperture into a vector register. ENC_FLAT_GLBL default 14 VDST FMT_ANY OPR_VGPR 128 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_DWORDX3 Load 96 bits of data from the global aperture into a vector register. ENC_FLAT_GLBL default 15 VDST FMT_ANY OPR_VGPR 96 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_BYTE Store 8 bits of data from a vector register into the global aperture. ENC_FLAT_GLBL default 24 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_BYTE_D16_HI Store 8 bits of data from the high 16 bits of a 32-bit vector register into the global aperture. ENC_FLAT_GLBL default 25 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_SHORT Store 16 bits of data from a vector register into the global aperture. ENC_FLAT_GLBL default 26 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_SHORT_D16_HI Store 16 bits of data from the high 16 bits of a 32-bit vector register into the global aperture. ENC_FLAT_GLBL default 27 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_DWORD Store 32 bits of data from vector input registers into the global aperture. ENC_FLAT_GLBL default 28 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_DWORDX2 Store 64 bits of data from vector input registers into the global aperture. ENC_FLAT_GLBL default 29 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_DWORDX4 Store 128 bits of data from vector input registers into the global aperture. ENC_FLAT_GLBL default 30 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 128 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_STORE_DWORDX3 Store 96 bits of data from vector input registers into the global aperture. ENC_FLAT_GLBL default 31 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 96 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_UBYTE_D16 Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT_GLBL default 32 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_UBYTE_D16_HI Load 8 bits of unsigned data from the global aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT_GLBL default 33 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_SBYTE_D16 Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT_GLBL default 34 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_SBYTE_D16_HI Load 8 bits of signed data from the global aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT_GLBL default 35 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_SHORT_D16 Load 16 bits of unsigned data from the global aperture and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT_GLBL default 36 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_LOAD_SHORT_D16_HI Load 16 bits of unsigned data from the global aperture and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT_GLBL default 37 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SWAP Swap an unsigned 32-bit integer value in the data register with a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 48 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_CMPSWAP Compare two unsigned 32-bit integer values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 49 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_ADD Add two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 50 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SUB Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 51 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SMIN Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 53 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_UMIN Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 54 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SMAX Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 55 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_UMAX Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 56 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_AND Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 57 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_OR Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 58 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_XOR Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 59 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_INC Increment an unsigned 32-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 60 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_DEC Decrement an unsigned 32-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 61 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_FCMPSWAP Compare two single-precision float values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 62 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_FMIN Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 63 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_FMAX Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 64 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SWAP_X2 Swap an unsigned 64-bit integer value in the data register with a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 80 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_CMPSWAP_X2 Compare two unsigned 64-bit integer values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 81 VDST FMT_ANY OPR_VGPR 128 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 128 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_ADD_X2 Add two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 82 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SUB_X2 Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 83 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SMIN_X2 Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 85 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_UMIN_X2 Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 86 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_SMAX_X2 Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 87 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_UMAX_X2 Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 88 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_AND_X2 Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 89 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_OR_X2 Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 90 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_XOR_X2 Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 91 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_INC_X2 Increment an unsigned 64-bit integer value from a location in the global aperture with wraparound to 0 if the value exceeds a value in the data register. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 92 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_DEC_X2 Decrement an unsigned 64-bit integer value from a location in the global aperture with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 93 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_FCMPSWAP_X2 Compare two double-precision float values stored in the data comparison register and a location in the global aperture. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 94 VDST FMT_ANY OPR_VGPR 128 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 128 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_FMIN_X2 Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 95 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE GLOBAL_ATOMIC_FMAX_X2 Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in the global aperture. Store the original value from global aperture into a vector register iff the GLC bit is set. ENC_FLAT_GLBL default 96 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 64 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_UBYTE Load 8 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register. ENC_FLAT_SCRATCH default 8 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_SBYTE Load 8 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register. ENC_FLAT_SCRATCH default 9 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_USHORT Load 16 bits of unsigned data from the scratch aperture, zero extend to 32 bits and store the result into a vector register. ENC_FLAT_SCRATCH default 10 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_SSHORT Load 16 bits of signed data from the scratch aperture, sign extend to 32 bits and store the result into a vector register. ENC_FLAT_SCRATCH default 11 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_DWORD Load 32 bits of data from the scratch aperture into a vector register. ENC_FLAT_SCRATCH default 12 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_DWORDX2 Load 64 bits of data from the scratch aperture into a vector register. ENC_FLAT_SCRATCH default 13 VDST FMT_ANY OPR_VGPR 64 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_DWORDX4 Load 128 bits of data from the scratch aperture into a vector register. ENC_FLAT_SCRATCH default 14 VDST FMT_ANY OPR_VGPR 128 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_DWORDX3 Load 96 bits of data from the scratch aperture into a vector register. ENC_FLAT_SCRATCH default 15 VDST FMT_ANY OPR_VGPR 96 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_BYTE Store 8 bits of data from a vector register into the scratch aperture. ENC_FLAT_SCRATCH default 24 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_BYTE_D16_HI Store 8 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture. ENC_FLAT_SCRATCH default 25 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_SHORT Store 16 bits of data from a vector register into the scratch aperture. ENC_FLAT_SCRATCH default 26 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_SHORT_D16_HI Store 16 bits of data from the high 16 bits of a 32-bit vector register into the scratch aperture. ENC_FLAT_SCRATCH default 27 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_DWORD Store 32 bits of data from vector input registers into the scratch aperture. ENC_FLAT_SCRATCH default 28 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_DWORDX2 Store 64 bits of data from vector input registers into the scratch aperture. ENC_FLAT_SCRATCH default 29 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 64 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_DWORDX4 Store 128 bits of data from vector input registers into the scratch aperture. ENC_FLAT_SCRATCH default 30 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 128 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_STORE_DWORDX3 Store 96 bits of data from vector input registers into the scratch aperture. ENC_FLAT_SCRATCH default 31 ADDR FMT_ANY OPR_VGPR 32 DATA FMT_ANY OPR_VGPR 96 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_UBYTE_D16 Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT_SCRATCH default 32 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_UBYTE_D16_HI Load 8 bits of unsigned data from the scratch aperture, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT_SCRATCH default 33 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_SBYTE_D16 Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT_SCRATCH default 34 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_SBYTE_D16_HI Load 8 bits of signed data from the scratch aperture, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT_SCRATCH default 35 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_SHORT_D16 Load 16 bits of unsigned data from the scratch aperture and store the result into the low 16 bits of a 32-bit vector register. ENC_FLAT_SCRATCH default 36 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE SCRATCH_LOAD_SHORT_D16_HI Load 16 bits of unsigned data from the scratch aperture and store the result into the high 16 bits of a 32-bit vector register. ENC_FLAT_SCRATCH default 37 VDST FMT_ANY OPR_VGPR 32 ADDR FMT_ANY OPR_VGPR 32 SADDR FMT_ANY OPR_SREG 32 FMT_NUM_B64 OPR_FLAT_SCRATCH 64 FMT_NUM_B32 OPR_SDST_M0 32 VMEM FLAT FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD Load a texel from the largest miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. No sampling is performed. ENC_MIMG default 0 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 0 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 0 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 0 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_MIP Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. No sampling is performed. ENC_MIMG default 1 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 1 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 1 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 1 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_PCK Load a texel from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. No sampling is performed. ENC_MIMG default 2 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 2 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 2 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 2 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_PCK_SGN Load a texel from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are sign-extended. The format specified in the resource descriptor is ignored. No sampling is performed. ENC_MIMG default 3 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 3 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 3 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 3 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_MIP_PCK Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. No sampling is performed. ENC_MIMG default 4 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 4 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 4 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 4 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_MIP_PCK_SGN Load a texel from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are sign-extended. The format specified in the resource descriptor is ignored. No sampling is performed. ENC_MIMG default 5 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 5 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 5 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 5 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE Store a texel from a vector register to the largest miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage. ENC_MIMG default 8 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 8 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 8 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 8 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_MIP Store a texel from a vector register to a user-specified miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage. ENC_MIMG default 9 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 9 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 9 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 9 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_PCK Store a texel from a vector register to the largest miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored. ENC_MIMG default 10 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 10 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 10 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 10 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_MIP_PCK Store a texel from a vector register to a user-specified miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored. ENC_MIMG default 11 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 11 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 11 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 11 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_GET_RESINFO Gather resource information for a given miplevel provided in the address register. Returns 4 integer values into registers 3:0 as { num_mip_levels, depth, height, width }. No memory access is performed. ENC_MIMG default 14 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 32 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 14 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 32 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 14 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 32 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 14 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 32 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_SWAP Swap an unsigned 32-bit integer value in the data register with a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 15 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 15 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 15 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 15 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_CMPSWAP Compare two unsigned 32-bit integer values stored in the data comparison register and a location in an image surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 16 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 16 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 16 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 16 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_ADD Add two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 17 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 17 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 17 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 17 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_SUB Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 18 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 18 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 18 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 18 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_SMIN Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 20 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 20 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 20 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 20 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_UMIN Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 21 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 21 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 21 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 21 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_SMAX Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 22 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 22 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 22 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 22 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_UMAX Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 23 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 23 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 23 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 23 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_AND Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 24 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 24 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 24 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 24 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_OR Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 25 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 25 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 25 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 25 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_XOR Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 26 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 26 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 26 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 26 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_INC Increment an unsigned 32-bit integer value from a location in an image surface with wraparound to 0 if the value exceeds a value in the data register. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 27 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 27 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 27 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 27 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_DEC Decrement an unsigned 32-bit integer value from a location in an image surface with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 28 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 28 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 28 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 28 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_FCMPSWAP Compare two single-precision float values stored in the data comparison register and a location in an image surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 29 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 29 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 29 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 29 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_FMIN Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 30 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 30 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 30 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 30 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_ATOMIC_FMAX Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in an image surface. Store the original value from image surface into a vector register iff the GLC bit is set. ENC_MIMG default 31 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 31 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 31 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 31 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. ENC_MIMG default 32 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 32 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 32 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 32 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD clamp are provided by the address registers. ENC_MIMG default 33 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 33 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 33 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 33 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for user derivatives are provided by the address registers. ENC_MIMG default 34 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 34 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 34 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 34 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for user derivatives, LOD clamp are provided by the address registers. ENC_MIMG default 35 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 35 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 35 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 35 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_L Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD are provided by the address registers. ENC_MIMG default 36 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 36 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 36 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 36 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_B Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD bias are provided by the address registers. ENC_MIMG default 37 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 37 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 37 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 37 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_B_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD bias, LOD clamp are provided by the address registers. ENC_MIMG default 38 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 38 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 38 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 38 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_LZ Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 39 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 39 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 39 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 39 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF are provided by the address registers. ENC_MIMG default 40 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 40 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 40 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 40 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD clamp are provided by the address registers. ENC_MIMG default 41 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 41 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 41 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 41 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user derivatives are provided by the address registers. ENC_MIMG default 42 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 42 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 42 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 42 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user derivatives, LOD clamp are provided by the address registers. ENC_MIMG default 43 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 43 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 43 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 43 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_L Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD are provided by the address registers. ENC_MIMG default 44 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 44 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 44 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 44 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_B Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD bias are provided by the address registers. ENC_MIMG default 45 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 45 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 45 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 45 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_B_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD bias, LOD clamp are provided by the address registers. ENC_MIMG default 46 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 46 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 46 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 46 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_LZ Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 47 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 47 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 47 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 47 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for user offsets are provided by the address registers. ENC_MIMG default 48 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 48 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 48 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 48 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 49 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 49 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 49 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 49 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for user derivatives, user offsets are provided by the address registers. ENC_MIMG default 50 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 50 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 50 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 50 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for user derivatives, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 51 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 51 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 51 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 51 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_L_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD, user offsets are provided by the address registers. ENC_MIMG default 52 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 52 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 52 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 52 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_B_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD bias, user offsets are provided by the address registers. ENC_MIMG default 53 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 53 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 53 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 53 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_B_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD bias, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 54 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 54 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 54 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 54 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_LZ_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for user offsets are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 55 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 55 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 55 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 55 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user offsets are provided by the address registers. ENC_MIMG default 56 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 56 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 56 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 56 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 57 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 57 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 57 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 57 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user derivatives, user offsets are provided by the address registers. ENC_MIMG default 58 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 58 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 58 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 58 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user derivatives, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 59 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 59 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 59 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 59 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_L_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD, user offsets are provided by the address registers. ENC_MIMG default 60 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 60 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 60 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 60 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_B_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD bias, user offsets are provided by the address registers. ENC_MIMG default 61 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 61 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 61 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 61 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_B_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD bias, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 62 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 62 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 62 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 62 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_LZ_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user offsets are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 63 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 63 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 63 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 63 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4 Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. ENC_MIMG default 64 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 64 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 64 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 64 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_CL Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD clamp are provided by the address registers. ENC_MIMG default 65 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 65 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 65 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 65 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_BY2 Load 2 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. Illegal for formats with more than 2 components. No sampling is performed. ENC_MIMG default 66 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 66 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 66 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 66 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_BY4 Load 4 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. Illegal for formats with more than 1 component. No sampling is performed. ENC_MIMG default 67 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 67 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 67 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 67 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_L Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD are provided by the address registers. ENC_MIMG default 68 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 68 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 68 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 68 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_B Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD bias are provided by the address registers. ENC_MIMG default 69 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 69 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 69 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 69 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_B_CL Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD bias, LOD clamp are provided by the address registers. ENC_MIMG default 70 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 70 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 70 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 70 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_LZ Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 71 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 71 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 71 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 71 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF are provided by the address registers. ENC_MIMG default 72 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 72 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 72 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 72 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_CL Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD clamp are provided by the address registers. ENC_MIMG default 73 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 73 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 73 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 73 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_MIP_BY2 Load 2 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. Illegal for formats with more than 2 components. No sampling is performed. ENC_MIMG default 74 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 74 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 74 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 74 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_MIP_BY4 Load 4 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. Perform the format conversion specified by the resource descriptor. Illegal for formats with more than 1 component. No sampling is performed. ENC_MIMG default 75 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 75 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 75 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 75 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_L Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD are provided by the address registers. ENC_MIMG default 76 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 76 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 76 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 76 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_B Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD bias are provided by the address registers. ENC_MIMG default 77 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 77 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 77 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 77 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_B_CL Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD bias, LOD clamp are provided by the address registers. ENC_MIMG default 78 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 78 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 78 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 78 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_LZ Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 79 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 79 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 79 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 79 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for user offsets are provided by the address registers. ENC_MIMG default 80 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 80 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 80 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 80 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_CL_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 81 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 81 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 81 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 81 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_BY2 Store 2 horizontal elements from a vector register to the largest miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage. Illegal for formats with more than 2 components. ENC_MIMG default 82 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 82 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 82 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 82 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_BY4 Store 4 horizontal elements from a vector register to the largest miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage. Illegal for formats with more than 1 component. ENC_MIMG default 83 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 83 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 83 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 83 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_L_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD, user offsets are provided by the address registers. ENC_MIMG default 84 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 84 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 84 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 84 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_B_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD bias, user offsets are provided by the address registers. ENC_MIMG default 85 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 85 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 85 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 85 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_B_CL_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for LOD bias, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 86 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 86 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 86 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 86 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_LZ_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for user offsets are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 87 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 87 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 87 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 87 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, user offsets are provided by the address registers. ENC_MIMG default 88 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 88 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 88 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 88 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_CL_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 89 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 89 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 89 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 89 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_MIP_BY2 Store 2 horizontal elements from a vector register to a user-specified miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage. Illegal for formats with more than 2 components. ENC_MIMG default 90 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 90 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 90 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 90 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_MIP_BY4 Store 4 horizontal elements from a vector register to a user-specified miplevel in an image surface. The texel data is converted using the format conversion specified by the resource descriptor prior to storage. Illegal for formats with more than 1 component. ENC_MIMG default 91 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 91 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 91 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 91 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_L_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD, user offsets are provided by the address registers. ENC_MIMG default 92 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 92 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 92 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 92 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_B_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD bias, user offsets are provided by the address registers. ENC_MIMG default 93 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 93 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 93 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 93 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 192 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_B_CL_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, LOD bias, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 94 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 94 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 94 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 94 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4_C_LZ_O Gather 4 single-component texels from a 2x2 matrix on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. Additional data for PCF, user offsets are provided by the address registers. Mipmap level is set to zero. ENC_MIMG default 95 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 95 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 95 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 95 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 160 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GET_LOD Return the calculated level of detail (LOD) for the provided input as two single-precision float values. No memory access is performed. ENC_MIMG default 96 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 96 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 96 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 96 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4H Gather 4 single-component texels from a 4x1 row vector on an image surface. Store the result into vector registers. The DMASK selects which channel to read from (R, G, B, A) and must only have one bit set to 1. ENC_MIMG default 97 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 97 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 97 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 97 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER4H_PCK Gather all components of 4 texels from a 4x1 row vector on an image surface. Store the result into vector registers. The DMASK selects how many channels to write. ENC_MIMG default 98 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 98 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 98 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 98 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_GATHER8H_PCK Gather all components of 8 texels from a 8x1 row vector on an image surface. Store the result into vector registers. The DMASK selects how many channels to write. ENC_MIMG default 99 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 99 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 99 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 99 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 96 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives are provided by the address registers. ENC_MIMG default 104 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 104 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 104 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 104 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives, LOD clamp are provided by the address registers. ENC_MIMG default 105 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 105 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 105 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 105 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives are provided by the address registers. ENC_MIMG default 106 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 106 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 106 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 106 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD_CL Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, LOD clamp are provided by the address registers. ENC_MIMG default 107 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 107 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 107 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 107 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives, user offsets are provided by the address registers. ENC_MIMG default 108 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 108 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 108 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 108 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 109 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 109 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 109 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 109 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, user offsets are provided by the address registers. ENC_MIMG default 110 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 110 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 110 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 110 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 352 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD_CL_O Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, LOD clamp, user offsets are provided by the address registers. ENC_MIMG default 111 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 111 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 111 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 111 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 384 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_PCK2 Load 2 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. Illegal for element sizes greater than 64 bits. No sampling is performed. ENC_MIMG default 112 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 112 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 112 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 112 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_PCK4 Load 4 horizontal elements from the largest miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. Illegal for element sizes greater than 32 bits. No sampling is performed. ENC_MIMG default 113 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 113 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 113 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 113 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_MIP_PCK2 Load 2 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. Illegal for element sizes greater than 64 bits. No sampling is performed. ENC_MIMG default 115 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 115 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 115 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 115 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_LOAD_MIP_PCK4 Load 4 horizontal elements from a user-specified miplevel in an image surface and store the result into a vector register. 8- and 16-bit components are zero-extended. The format specified in the resource descriptor is ignored. Illegal for element sizes greater than 32 bits. No sampling is performed. ENC_MIMG default 116 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 116 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 116 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 116 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_PCK2 Store 2 horizontal elements from a vector register to the largest miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored. Illegal for element sizes greater than 64 bits. ENC_MIMG default 118 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 118 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 118 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 118 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_PCK4 Store 4 horizontal elements from a vector register to the largest miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored. Illegal for element sizes greater than 32 bits. ENC_MIMG default 119 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 119 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 119 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 119 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_MIP_PCK2 Store 2 horizontal elements from a vector register to a user-specified miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored. Illegal for element sizes greater than 64 bits. ENC_MIMG default 121 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 121 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 121 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 121 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_STORE_MIP_PCK4 Store 4 horizontal elements from a vector register to a user-specified miplevel in an image surface. The texel data is already packed and the format specified in the resource descriptor is ignored. Illegal for element sizes greater than 32 bits. ENC_MIMG default 122 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 122 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 122 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 122 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_MSAA_LOAD Load up to 4 samples of 1 component from an MSAA resource with a user-specified fragment ID. No sampling is performed. ENC_MIMG default 128 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA1 has_nsa_1 128 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA2 has_nsa_2 128 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 MIMG_NSA3 has_nsa_3 128 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 128 SRSRC FMT_IMG OPR_SREG_NONULL 256 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for 16-bit derivatives are provided by the address registers. ENC_MIMG default 162 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 162 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 162 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 162 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D_CL_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD clamp, 16-bit derivatives are provided by the address registers. ENC_MIMG default 163 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 163 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 163 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 163 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, 16-bit derivatives are provided by the address registers. ENC_MIMG default 170 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 170 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 170 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 170 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D_CL_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD clamp, 16-bit derivatives are provided by the address registers. ENC_MIMG default 171 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 171 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 171 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 171 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 178 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 178 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 178 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 178 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_D_CL_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for LOD clamp, user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 179 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 179 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 179 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 179 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 186 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 186 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 186 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 186 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_D_CL_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, LOD clamp, user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 187 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 187 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 187 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 187 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives, 16-bit derivatives are provided by the address registers. ENC_MIMG default 232 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 232 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 232 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 232 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 224 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD_CL_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives, LOD clamp, 16-bit derivatives are provided by the address registers. ENC_MIMG default 233 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 233 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 233 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 233 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, 16-bit derivatives are provided by the address registers. ENC_MIMG default 234 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 234 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 234 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 234 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD_CL_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, LOD clamp, 16-bit derivatives are provided by the address registers. ENC_MIMG default 235 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 235 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 235 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 235 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives, user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 236 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 236 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 236 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 236 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 256 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_CD_CL_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for coarse derivatives, LOD clamp, user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 237 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 237 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 237 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 237 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 238 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 238 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 238 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 238 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 288 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE IMAGE_SAMPLE_C_CD_CL_O_G16 Sample texels from an image surface using texel coordinates provided by the address input registers and store the result into vector registers. Additional data for PCF, coarse derivatives, LOD clamp, user offsets, 16-bit derivatives are provided by the address registers. ENC_MIMG default 239 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA1 has_nsa_1 239 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA2 has_nsa_2 239 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 MIMG_NSA3 has_nsa_3 239 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_NUM_F32 OPR_VGPR 320 SRSRC FMT_IMG OPR_SREG_NONULL 256 SSAMP FMT_SAMP OPR_SREG_NONULL 128 VMEM SAMPLE FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_X Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 0 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_XY Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 1 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_XYZ Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 2 VDATA FMT_ANY OPR_VGPR 96 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_XYZW Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 3 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_X Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 4 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_XY Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 5 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_XYZ Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 6 VDATA FMT_ANY OPR_VGPR 96 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_XYZW Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 7 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_D16_X Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 8 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_D16_XY Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 9 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_D16_XYZ Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 10 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_LOAD_FORMAT_D16_XYZW Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 11 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_D16_X Convert 16 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 12 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_D16_XY Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 13 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_D16_XYZ Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 14 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE TBUFFER_STORE_FORMAT_D16_XYZW Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MTBUF default 15 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_X Load 1-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 0 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_XY Load 2-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 1 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_XYZ Load 3-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 2 VDATA FMT_ANY OPR_VGPR 96 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_XYZW Load 4-component formatted data from a buffer surface, convert the data to 32 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 3 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_X Convert 32 bits of data from vector input registers into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 4 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_XY Convert 64 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 5 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_XYZ Convert 96 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 6 VDATA FMT_ANY OPR_VGPR 96 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_XYZW Convert 128 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 7 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_UBYTE Load 8 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. ENC_MUBUF default 8 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_SBYTE Load 8 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. ENC_MUBUF default 9 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_USHORT Load 16 bits of unsigned data from a buffer surface, zero extend to 32 bits and store the result into a vector register. ENC_MUBUF default 10 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_SSHORT Load 16 bits of signed data from a buffer surface, sign extend to 32 bits and store the result into a vector register. ENC_MUBUF default 11 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_DWORD Load 32 bits of data from a buffer surface into a vector register. ENC_MUBUF default 12 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_DWORDX2 Load 64 bits of data from a buffer surface into a vector register. ENC_MUBUF default 13 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_DWORDX4 Load 128 bits of data from a buffer surface into a vector register. ENC_MUBUF default 14 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_DWORDX3 Load 96 bits of data from a buffer surface into a vector register. ENC_MUBUF default 15 VDATA FMT_ANY OPR_VGPR 96 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_BYTE Store 8 bits of data from a vector register into a buffer surface. ENC_MUBUF default 24 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_BYTE_D16_HI Store 8 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. ENC_MUBUF default 25 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_SHORT Store 16 bits of data from a vector register into a buffer surface. ENC_MUBUF default 26 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_SHORT_D16_HI Store 16 bits of data from the high 16 bits of a 32-bit vector register into a buffer surface. ENC_MUBUF default 27 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_DWORD Store 32 bits of data from vector input registers into a buffer surface. ENC_MUBUF default 28 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_DWORDX2 Store 64 bits of data from vector input registers into a buffer surface. ENC_MUBUF default 29 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_DWORDX4 Store 128 bits of data from vector input registers into a buffer surface. ENC_MUBUF default 30 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_DWORDX3 Store 96 bits of data from vector input registers into a buffer surface. ENC_MUBUF default 31 VDATA FMT_ANY OPR_VGPR 96 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_UBYTE_D16 Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_MUBUF default 32 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_UBYTE_D16_HI Load 8 bits of unsigned data from a buffer surface, zero extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_MUBUF default 33 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_SBYTE_D16 Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the low 16 bits of a 32-bit vector register. ENC_MUBUF default 34 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_SBYTE_D16_HI Load 8 bits of signed data from a buffer surface, sign extend to 16 bits and store the result into the high 16 bits of a 32-bit vector register. ENC_MUBUF default 35 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_SHORT_D16 Load 16 bits of unsigned data from a buffer surface and store the result into the low 16 bits of a 32-bit vector register. ENC_MUBUF default 36 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_SHORT_D16_HI Load 16 bits of unsigned data from a buffer surface and store the result into the high 16 bits of a 32-bit vector register. ENC_MUBUF default 37 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_D16_HI_X Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into the high 16 bits of a 32-bit vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 38 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_D16_HI_X Convert 16 bits of data from the high 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 39 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SWAP Swap an unsigned 32-bit integer value in the data register with a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 48 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_CMPSWAP Compare two unsigned 32-bit integer values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 49 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_ADD Add two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 50 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SUB Subtract an unsigned 32-bit integer value stored in the data register from a value stored in a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 51 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SMIN Select the minimum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 53 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_UMIN Select the minimum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 54 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SMAX Select the maximum of two signed 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 55 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_UMAX Select the maximum of two unsigned 32-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 56 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_AND Calculate bitwise AND given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 57 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_OR Calculate bitwise OR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 58 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_XOR Calculate bitwise XOR given two unsigned 32-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 59 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_INC Increment an unsigned 32-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 60 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_DEC Decrement an unsigned 32-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 61 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_FCMPSWAP Compare two single-precision float values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 62 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_FMIN Select the minimum of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 63 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_FMAX Select the maximum of two single-precision float inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 64 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SWAP_X2 Swap an unsigned 64-bit integer value in the data register with a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 80 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_CMPSWAP_X2 Compare two unsigned 64-bit integer values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 81 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_ADD_X2 Add two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 82 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SUB_X2 Subtract an unsigned 64-bit integer value stored in the data register from a value stored in a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 83 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SMIN_X2 Select the minimum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 85 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_UMIN_X2 Select the minimum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 86 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_SMAX_X2 Select the maximum of two signed 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 87 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_UMAX_X2 Select the maximum of two unsigned 64-bit integer inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 88 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_AND_X2 Calculate bitwise AND given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 89 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_OR_X2 Calculate bitwise OR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 90 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_XOR_X2 Calculate bitwise XOR given two unsigned 64-bit integer values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 91 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_INC_X2 Increment an unsigned 64-bit integer value from a location in a buffer surface with wraparound to 0 if the value exceeds a value in the data register. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 92 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_DEC_X2 Decrement an unsigned 64-bit integer value from a location in a buffer surface with wraparound to a value in the data register if the decrement yields a negative value. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 93 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_FCMPSWAP_X2 Compare two double-precision float values stored in the data comparison register and a location in a buffer surface. Modify the memory location with a value in the data source register iff the comparison is equal. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 94 VDATA FMT_ANY OPR_VGPR 128 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_FMIN_X2 Select the minimum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 95 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_ATOMIC_FMAX_X2 Select the maximum of two double-precision float inputs, given two values stored in the data register and a location in a buffer surface. Store the original value from buffer surface into a vector register iff the GLC bit is set. ENC_MUBUF default 96 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_SCRATCH OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM ATOMIC FALSE FALSE FALSE FALSE FALSE BUFFER_GL0_INV Write back and invalidate the shader L0. Returns ACK to shader. ENC_MUBUF default 113 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_GL1_INV Invalidate the GL1 cache only. Returns ACK to shader. ENC_MUBUF default 114 VMEM TEXTURE FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_D16_X Load 1-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into the low 16 bits of a 32-bit vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 128 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_D16_XY Load 2-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 129 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_D16_XYZ Load 3-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 130 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_LOAD_FORMAT_D16_XYZW Load 4-component formatted data from a buffer surface, convert the data to packed 16 bit integral or floating point format, then store the result into a vector register. The resource descriptor specifies the data format of the surface. ENC_MUBUF default 131 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM LOAD FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_D16_X Convert 16 bits of data from the low 16 bits of a 32-bit vector input register into 1-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 132 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_D16_XY Convert 32 bits of data from vector input registers into 2-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 133 VDATA FMT_ANY OPR_VGPR 32 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_D16_XYZ Convert 48 bits of data from vector input registers into 3-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 134 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE BUFFER_STORE_FORMAT_D16_XYZW Convert 64 bits of data from vector input registers into 4-component formatted data and store the data into a buffer surface. The instruction specifies the data format of the surface, overriding the resource descriptor. ENC_MUBUF default 135 VDATA FMT_ANY OPR_VGPR 64 VADDR FMT_ANY OPR_VGPR 64 SRSRC FMT_RSRC_TYPED OPR_SREG_NONULL 128 SOFFSET FMT_ANY OPR_SREG_M0_INL 32 VMEM STORE FALSE FALSE FALSE FALSE FALSE S_LOAD_DWORD Load 32 bits of data from the scalar memory into a scalar register. ENC_SMEM default 0 SDATA FMT_ANY OPR_SREG 32 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_LOAD_DWORDX2 Load 64 bits of data from the scalar memory into a scalar register. ENC_SMEM default 1 SDATA FMT_ANY OPR_SREG 64 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_LOAD_DWORDX4 Load 128 bits of data from the scalar memory into a scalar register. ENC_SMEM default 2 SDATA FMT_ANY OPR_SREG 128 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_LOAD_DWORDX8 Load 256 bits of data from the scalar memory into a scalar register. ENC_SMEM default 3 SDATA FMT_ANY OPR_SREG 256 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_LOAD_DWORDX16 Load 512 bits of data from the scalar memory into a scalar register. ENC_SMEM default 4 SDATA FMT_ANY OPR_SREG 512 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_SCRATCH_LOAD_DWORD Load 32 bits of data from the scalar scratch aperture into a scalar register. ENC_SMEM default 5 SDATA FMT_ANY OPR_SREG 32 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_SCRATCH_LOAD_DWORDX2 Load 64 bits of data from the scalar scratch aperture into a scalar register. ENC_SMEM default 6 SDATA FMT_ANY OPR_SREG 64 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_SCRATCH_LOAD_DWORDX4 Load 128 bits of data from the scalar scratch aperture into a scalar register. ENC_SMEM default 7 SDATA FMT_ANY OPR_SREG 128 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_BUFFER_LOAD_DWORD Load 32 bits of data from a scalar buffer surface into a scalar register. ENC_SMEM default 8 SDATA FMT_ANY OPR_SREG 32 SBASE FMT_RSRC_SCALAR OPR_SREG_NONULL 128 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_BUFFER_LOAD_DWORDX2 Load 64 bits of data from a scalar buffer surface into a scalar register. ENC_SMEM default 9 SDATA FMT_ANY OPR_SREG 64 SBASE FMT_RSRC_SCALAR OPR_SREG_NONULL 128 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_BUFFER_LOAD_DWORDX4 Load 128 bits of data from a scalar buffer surface into a scalar register. ENC_SMEM default 10 SDATA FMT_ANY OPR_SREG 128 SBASE FMT_RSRC_SCALAR OPR_SREG_NONULL 128 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_BUFFER_LOAD_DWORDX8 Load 256 bits of data from a scalar buffer surface into a scalar register. ENC_SMEM default 11 SDATA FMT_ANY OPR_SREG 256 SBASE FMT_RSRC_SCALAR OPR_SREG_NONULL 128 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_BUFFER_LOAD_DWORDX16 Load 512 bits of data from a scalar buffer surface into a scalar register. ENC_SMEM default 12 SDATA FMT_ANY OPR_SREG 512 SBASE FMT_RSRC_SCALAR OPR_SREG_NONULL 128 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_GL1_INV Invalidate the GL1 cache only. ENC_SMEM default 31 SMEM FALSE FALSE FALSE FALSE FALSE S_DCACHE_INV Invalidate the scalar data L0 cache. ENC_SMEM default 32 SMEM FALSE FALSE FALSE FALSE FALSE S_MEMTIME Return current 64-bit timestamp. ENC_SMEM default 36 SDATA FMT_NUM_B64 OPR_SREG 64 SMEM FALSE FALSE FALSE FALSE FALSE S_MEMREALTIME Return current 64-bit RTC. ENC_SMEM default 37 SDATA FMT_NUM_B64 OPR_SREG 64 SMEM FALSE FALSE FALSE FALSE FALSE S_ATC_PROBE Probe or prefetch an address into the scalar data cache. ENC_SMEM default 38 SDATA FMT_NUM_B8 OPR_SIMM8 8 SBASE FMT_BUF OPR_SREG_NONULL 64 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_ATC_PROBE_BUFFER Probe or prefetch an address into the scalar data cache. ENC_SMEM default 39 SDATA FMT_NUM_B8 OPR_SIMM8 8 SBASE FMT_RSRC_SCALAR OPR_SREG_NONULL 128 SOFFSET FMT_NUM_B32 OPR_SMEM_OFFSET 32 SMEM FALSE FALSE FALSE FALSE FALSE S_GET_WAVEID_IN_WORKGROUP Return the wave's ID within a workgroup 0-(N-1). Return zero if wave is not in a workgroup. ID reflects the order in which waves were created within each workgroup. ENC_SMEM default 42 SDATA FMT_NUM_B32 OPR_SREG 32 SMEM FALSE FALSE FALSE FALSE FALSE S_MOV_B32 Move scalar input into a scalar register. ENC_SOP1 default 3 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 3 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_MOV_B64 Move scalar input into a scalar register. ENC_SOP1 default 4 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_B64 OPR_SSRC_NOLDS 64 SOP1_INST_LITERAL has_lit_0 4 SDST FMT_NUM_B64 OPR_SDST 64 SIMM32 FMT_NUM_B64 OPR_SSRC_NOLDS 64 SALU FALSE FALSE FALSE FALSE FALSE S_CMOV_B32 Move scalar input into a scalar register iff SCC is nonzero. ENC_SOP1 default 5 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 5 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMOV_B64 Move scalar input into a scalar register iff SCC is nonzero. ENC_SOP1 default 6 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 6 SDST FMT_NUM_B64 OPR_SDST 64 SIMM32 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_NOT_B32 Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 7 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 7 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_NOT_B64 Calculate bitwise negation on a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 8 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 8 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_WQM_B32 Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 9 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 9 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_WQM_B64 Given an active pixel mask in a scalar input, calculate whole quad mode mask for that input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 10 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 10 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BREV_B32 Reverse the order of bits in a scalar input and store the result into a scalar register. ENC_SOP1 default 11 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 11 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_BREV_B64 Reverse the order of bits in a scalar input and store the result into a scalar register. ENC_SOP1 default 12 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SOP1_INST_LITERAL has_lit_0 12 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SALU FALSE FALSE FALSE FALSE FALSE S_BCNT0_I32_B32 Count the number of "0" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 13 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 13 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BCNT0_I32_B64 Count the number of "0" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 14 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 14 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BCNT1_I32_B32 Count the number of "1" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 15 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 15 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BCNT1_I32_B64 Count the number of "1" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 16 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 16 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_FF0_I32_B32 Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register. Store -1 if there are no "0" bits in the input. ENC_SOP1 default 17 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 17 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_FF0_I32_B64 Count the number of trailing "1" bits before the first "0" in a scalar input and store the result into a scalar register. Store -1 if there are no "0" bits in the input. ENC_SOP1 default 18 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SOP1_INST_LITERAL has_lit_0 18 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SALU FALSE FALSE FALSE FALSE FALSE S_FF1_I32_B32 Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits in the input. ENC_SOP1 default 19 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 19 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_FF1_I32_B64 Count the number of trailing "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits in the input. ENC_SOP1 default 20 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SOP1_INST_LITERAL has_lit_0 20 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SALU FALSE FALSE FALSE FALSE FALSE S_FLBIT_I32_B32 Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits. ENC_SOP1 default 21 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 21 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_FLBIT_I32_B64 Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits. ENC_SOP1 default 22 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SOP1_INST_LITERAL has_lit_0 22 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SALU FALSE FALSE FALSE FALSE FALSE S_FLBIT_I32 Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same. ENC_SOP1 default 23 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 23 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_FLBIT_I32_I64 Count the number of leading bits that are the same as the sign bit of a scalar input and store the result into a scalar register. Store -1 if all input bits are the same. ENC_SOP1 default 24 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SOP1_INST_LITERAL has_lit_0 24 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SALU FALSE FALSE FALSE FALSE FALSE S_SEXT_I32_I8 Sign extend a signed 8 bit scalar input to 32 bits and store the result into a scalar register. ENC_SOP1 default 25 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I16 OPR_SSRC_NOLDS 16 SOP1_INST_LITERAL has_lit_0 25 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I16 OPR_SSRC_NOLDS 16 SALU FALSE FALSE FALSE FALSE FALSE S_SEXT_I32_I16 Sign extend a signed 16 bit scalar input to 32 bits and store the result into a scalar register. ENC_SOP1 default 26 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I16 OPR_SSRC_NOLDS 16 SOP1_INST_LITERAL has_lit_0 26 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I16 OPR_SSRC_NOLDS 16 SALU FALSE FALSE FALSE FALSE FALSE S_BITSET0_B32 Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0. ENC_SOP1 default 27 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 27 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_BITSET0_B64 Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 0. ENC_SOP1 default 28 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 28 SDST FMT_NUM_B64 OPR_SDST 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_BITSET1_B32 Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1. ENC_SOP1 default 29 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 29 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_BITSET1_B64 Given a bit offset in a scalar input, set the indicated bit in the destination scalar register to 1. ENC_SOP1 default 30 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 30 SDST FMT_NUM_B64 OPR_SDST 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_GETPC_B64 Store the address of the next instruction to a scalar register. ENC_SOP1 default 31 SDST FMT_NUM_B64 OPR_SDST 64 FMT_NUM_B64 OPR_PC 64 SALU TRUE FALSE TRUE FALSE FALSE S_SETPC_B64 Jump to an address specified in a scalar register. ENC_SOP1 default 32 SSRC0 FMT_NUM_B64 OPR_SREG 64 FMT_NUM_B64 OPR_PC 64 SALU TRUE FALSE TRUE FALSE FALSE S_SWAPPC_B64 Store the address of the next instruction to a scalar register and then jump to an address specified in the scalar input. ENC_SOP1 default 33 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_B64 OPR_SREG 64 FMT_NUM_B64 OPR_PC 64 FMT_NUM_B64 OPR_PC 64 SALU TRUE FALSE TRUE FALSE FALSE S_RFE_B64 Return from the exception handler. Clear the wave's PRIV bit and then jump to an address specified by the scalar input. ENC_SOP1 default 34 SSRC0 FMT_NUM_B64 OPR_SREG 64 FMT_NUM_B64 OPR_PC 64 SOP1_INST_LITERAL has_lit_0 34 SIMM32 FMT_NUM_B64 OPR_SREG 64 FMT_NUM_B64 OPR_PC 64 TRAP FALSE FALSE FALSE FALSE FALSE S_AND_SAVEEXEC_B64 Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 36 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 36 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_OR_SAVEEXEC_B64 Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 37 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 37 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_XOR_SAVEEXEC_B64 Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 38 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 38 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN2_SAVEEXEC_B64 Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 39 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 39 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ORN2_SAVEEXEC_B64 Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 40 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 40 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_NAND_SAVEEXEC_B64 Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 41 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 41 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_NOR_SAVEEXEC_B64 Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 42 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 42 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_XNOR_SAVEEXEC_B64 Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 43 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 43 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_QUADMASK_B32 Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 44 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 44 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_QUADMASK_B64 Reduce a pixel mask from the scalar input into a quad mask, store the result in a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 45 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 45 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_MOVRELS_B32 Move data from a relatively-indexed scalar register into another scalar register. ENC_SOP1 default 46 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B32 OPR_SREG 32 FMT_NUM_B32 OPR_SDST_M0 32 SOP1_INST_LITERAL has_lit_0 46 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B32 OPR_SREG 32 FMT_NUM_B32 OPR_SDST_M0 32 SALU FALSE FALSE FALSE FALSE FALSE S_MOVRELS_B64 Move data from a relatively-indexed scalar register into another scalar register. ENC_SOP1 default 47 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_B64 OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 SOP1_INST_LITERAL has_lit_0 47 SDST FMT_NUM_B64 OPR_SDST 64 SIMM32 FMT_NUM_B64 OPR_SREG 64 FMT_NUM_B32 OPR_SDST_M0 32 SALU FALSE FALSE FALSE FALSE FALSE S_MOVRELD_B32 Move data from a scalar input into a relatively-indexed scalar register. ENC_SOP1 default 48 SDST FMT_NUM_B32 OPR_SREG 32 SSRC0 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B32 OPR_SDST_M0 32 SOP1_INST_LITERAL has_lit_0 48 SDST FMT_NUM_B32 OPR_SREG 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B32 OPR_SDST_M0 32 SALU FALSE FALSE FALSE FALSE FALSE S_MOVRELD_B64 Move data from a scalar input into a relatively-indexed scalar register. ENC_SOP1 default 49 SDST FMT_NUM_B64 OPR_SREG 64 SSRC0 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B32 OPR_SDST_M0 32 SOP1_INST_LITERAL has_lit_0 49 SDST FMT_NUM_B64 OPR_SREG 64 SIMM32 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B32 OPR_SDST_M0 32 SALU FALSE FALSE FALSE FALSE FALSE S_ABS_I32 Compute the absolute value of a scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP1 default 52 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP1_INST_LITERAL has_lit_0 52 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN1_SAVEEXEC_B64 Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 55 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 55 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ORN1_SAVEEXEC_B64 Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 56 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 56 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN1_WREXEC_B64 Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. ENC_SOP1 default 57 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 57 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN2_WREXEC_B64 Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. ENC_SOP1 default 58 SDST FMT_NUM_U64 OPR_SREG 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 58 SDST FMT_NUM_U64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_BITREPLICATE_B64_B32 Substitute each bit of a 32 bit scalar input with two instances of itself and store the result into a 64 bit scalar register. ENC_SOP1 default 59 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP1_INST_LITERAL has_lit_0 59 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_AND_SAVEEXEC_B32 Calculate bitwise AND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 60 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 60 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_OR_SAVEEXEC_B32 Calculate bitwise OR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 61 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 61 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_XOR_SAVEEXEC_B32 Calculate bitwise XOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 62 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 62 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN2_SAVEEXEC_B32 Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 63 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 63 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ORN2_SAVEEXEC_B32 Calculate bitwise OR on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 64 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 64 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_NAND_SAVEEXEC_B32 Calculate bitwise NAND on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 65 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 65 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_NOR_SAVEEXEC_B32 Calculate bitwise NOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 66 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 66 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_XNOR_SAVEEXEC_B32 Calculate bitwise XNOR on the scalar input and the EXEC mask, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 67 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 67 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN1_SAVEEXEC_B32 Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 68 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 68 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ORN1_SAVEEXEC_B32 Calculate bitwise OR on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask, set SCC iff the calculated result is nonzero and store the original value of the EXEC mask into the scalar destination register. ENC_SOP1 default 69 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 69 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN1_WREXEC_B32 Calculate bitwise AND on the EXEC mask and the negation of the scalar input, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. ENC_SOP1 default 70 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 70 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN2_WREXEC_B32 Calculate bitwise AND on the scalar input and the negation of the EXEC mask, store the calculated result into the EXEC mask and also into the scalar destination register, and set SCC iff the calculated result is nonzero. ENC_SOP1 default 71 SDST FMT_NUM_U32 OPR_SREG 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SOP1_INST_LITERAL has_lit_0 71 SDST FMT_NUM_U32 OPR_SREG 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_MOVRELSD_2_B32 Move data from a relatively-indexed scalar register into another relatively-indexed scalar register, using different offsets for each index. ENC_SOP1 default 73 SDST FMT_NUM_B32 OPR_SREG 32 SSRC0 FMT_NUM_B32 OPR_SREG 32 FMT_NUM_B32 OPR_SDST_M0 32 SOP1_INST_LITERAL has_lit_0 73 SDST FMT_NUM_B32 OPR_SREG 32 SIMM32 FMT_NUM_B32 OPR_SREG 32 FMT_NUM_B32 OPR_SDST_M0 32 SALU FALSE FALSE FALSE FALSE FALSE S_ADD_U32 Add two unsigned inputs, store the result into a scalar register and store the carry-out bit into SCC. ENC_SOP2 default 0 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 0 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 0 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 0 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_SUB_U32 Subtract the second unsigned input from the first input, store the result into a scalar register and store the carry-out bit into SCC. ENC_SOP2 default 1 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 1 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 1 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 1 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ADD_I32 Add two signed inputs, store the result into a scalar register and store the carry-out bit into SCC. ENC_SOP2 default 2 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 2 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 2 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 2 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_SUB_I32 Subtract the second signed input from the first input, store the result into a scalar register and store the carry-out bit into SCC. ENC_SOP2 default 3 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 3 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 3 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 3 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ADDC_U32 Add two unsigned inputs and a carry-in bit, store the result into a scalar register and store the carry-out bit into SCC. ENC_SOP2 default 4 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 4 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 4 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 4 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_SUBB_U32 Subtract the second unsigned input from the first input, subtract the carry-in bit, store the result into a scalar register and store the carry-out bit into SCC. ENC_SOP2 default 5 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 5 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 5 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 5 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_MIN_I32 Select the minimum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. ENC_SOP2 default 6 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 6 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 6 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 6 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_MIN_U32 Select the minimum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. ENC_SOP2 default 7 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 7 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 7 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 7 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_MAX_I32 Select the maximum of two signed 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. ENC_SOP2 default 8 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 8 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 8 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 8 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_MAX_U32 Select the maximum of two unsigned 32-bit integer inputs, store the selected value into a scalar register and set SCC iff the first value is selected. ENC_SOP2 default 9 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 9 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 9 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 9 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CSELECT_B32 Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register. ENC_SOP2 default 10 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 10 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 10 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 10 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CSELECT_B64 Select the first input if SCC is true otherwise select the second input, then store the selected input into a scalar register. ENC_SOP2 default 11 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_B64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 11 SDST FMT_NUM_B64 OPR_SDST 64 SIMM32 FMT_NUM_B64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 11 SDST FMT_NUM_B64 OPR_SDST 64 SSRC0 FMT_NUM_B64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 11 SDST FMT_NUM_B64 OPR_SDST 64 SIMM32 FMT_NUM_B64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_B64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_AND_B32 Calculate bitwise AND on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 14 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 14 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 14 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 14 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_AND_B64 Calculate bitwise AND on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 15 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 15 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 15 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 15 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_OR_B32 Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 16 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 16 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 16 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 16 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_OR_B64 Calculate bitwise OR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 17 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 17 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 17 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 17 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_XOR_B32 Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 18 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 18 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 18 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 18 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_XOR_B64 Calculate bitwise XOR on two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 19 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 19 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 19 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 19 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN2_B32 Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 20 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 20 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 20 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 20 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ANDN2_B64 Calculate bitwise AND with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 21 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 21 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 21 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 21 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ORN2_B32 Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 22 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 22 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 22 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 22 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ORN2_B64 Calculate bitwise OR with the first input and the negation of the second input, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 23 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 23 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 23 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 23 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_NAND_B32 Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 24 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 24 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 24 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 24 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_NAND_B64 Calculate bitwise NAND on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 25 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 25 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 25 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 25 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_NOR_B32 Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 26 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 26 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 26 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 26 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_NOR_B64 Calculate bitwise NOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 27 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 27 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 27 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 27 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_XNOR_B32 Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 28 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 28 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 28 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 28 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_XNOR_B64 Calculate bitwise XNOR on two scalar inputs, store the result into a scalar register and set SCC if the result is nonzero. ENC_SOP2 default 29 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 29 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 29 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 29 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHL_B32 Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 30 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 30 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 30 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 30 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHL_B64 Given a shift count in the second scalar input, calculate the logical shift left of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 31 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 31 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 31 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 31 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHR_B32 Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 32 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 32 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 32 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 32 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHR_B64 Given a shift count in the second scalar input, calculate the logical shift right of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 33 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 33 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 33 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 33 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ASHR_I32 Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 34 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 34 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 34 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 34 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ASHR_I64 Given a shift count in the second scalar input, calculate the arithmetic shift right (preserving sign bit) of the first scalar input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 35 SDST FMT_NUM_I64 OPR_SDST 64 SSRC0 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 35 SDST FMT_NUM_I64 OPR_SDST 64 SIMM32 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 35 SDST FMT_NUM_I64 OPR_SDST 64 SSRC0 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 35 SDST FMT_NUM_I64 OPR_SDST 64 SIMM32 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BFM_B32 Calculate a bitfield mask given a field offset and size and store the result in a scalar register. ENC_SOP2 default 36 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0 36 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_1 36 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0_has_lit_1 36 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_BFM_B64 Calculate a bitfield mask given a field offset and size and store the result in a scalar register. ENC_SOP2 default 37 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0 37 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_1 37 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0_has_lit_1 37 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_MUL_I32 Multiply two signed integers and store the result into a scalar register. ENC_SOP2 default 38 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0 38 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_1 38 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0_has_lit_1 38 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_BFE_U32 Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 39 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 39 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 39 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 39 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BFE_I32 Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 40 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 40 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 40 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 40 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BFE_U64 Extract an unsigned bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 41 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 41 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 41 SDST FMT_NUM_U64 OPR_SDST 64 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 41 SDST FMT_NUM_U64 OPR_SDST 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BFE_I64 Extract a signed bitfield from the first input using field offset and size encoded in the second input, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 42 SDST FMT_NUM_I64 OPR_SDST 64 SSRC0 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 42 SDST FMT_NUM_I64 OPR_SDST 64 SIMM32 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 42 SDST FMT_NUM_I64 OPR_SDST 64 SSRC0 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 42 SDST FMT_NUM_I64 OPR_SDST 64 SIMM32 FMT_NUM_I64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ABSDIFF_I32 Calculate the absolute value of difference between two scalar inputs, store the result into a scalar register and set SCC iff the result is nonzero. ENC_SOP2 default 44 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 44 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 44 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 44 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHL1_ADD_U32 Calculate the logical shift left of the first input by 1, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow. ENC_SOP2 default 46 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 46 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 46 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 46 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHL2_ADD_U32 Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow. ENC_SOP2 default 47 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 47 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 47 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 47 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHL3_ADD_U32 Calculate the logical shift left of the first input by 3, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow. ENC_SOP2 default 48 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 48 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 48 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 48 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_LSHL4_ADD_U32 Calculate the logical shift left of the first input by 4, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow. ENC_SOP2 default 49 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0 49 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_1 49 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOP2_INST_LITERAL has_lit_0_has_lit_1 49 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_PACK_LL_B32_B16 Pack two 16-bit scalar values into a scalar register. ENC_SOP2 default 50 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SSRC1 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SOP2_INST_LITERAL has_lit_0 50 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SSRC1 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SOP2_INST_LITERAL has_lit_1 50 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SIMM32 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SOP2_INST_LITERAL has_lit_0_has_lit_1 50 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SIMM32 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SALU FALSE FALSE FALSE FALSE FALSE S_PACK_LH_B32_B16 Pack two 16-bit scalar values into a scalar register. ENC_SOP2 default 51 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SSRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0 51 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SSRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_1 51 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0_has_lit_1 51 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B16 OPR_SSRC_NOLDS 16 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_PACK_HH_B32_B16 Pack two 16-bit scalar values into a scalar register. ENC_SOP2 default 52 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0 52 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_1 52 SDST FMT_NUM_B32 OPR_SDST 32 SSRC0 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0_has_lit_1 52 SDST FMT_NUM_B32 OPR_SDST 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_MUL_HI_U32 Multiply two unsigned integers and store the high 32 bits of the result into a scalar register. ENC_SOP2 default 53 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0 53 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_1 53 SDST FMT_NUM_U32 OPR_SDST 32 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0_has_lit_1 53 SDST FMT_NUM_U32 OPR_SDST 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_MUL_HI_I32 Multiply two signed integers and store the high 32 bits of the result into a scalar register. ENC_SOP2 default 54 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0 54 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_1 54 SDST FMT_NUM_I32 OPR_SDST 32 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SOP2_INST_LITERAL has_lit_0_has_lit_1 54 SDST FMT_NUM_I32 OPR_SDST 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_EQ_I32 Set SCC to 1 iff the first scalar input is equal to the second scalar input. ENC_SOPC default 0 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 0 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 0 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 0 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_LG_I32 Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. ENC_SOPC default 1 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 1 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 1 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 1 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_GT_I32 Set SCC to 1 iff the first scalar input is greater than the second scalar input. ENC_SOPC default 2 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 2 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 2 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 2 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_GE_I32 Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input. ENC_SOPC default 3 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 3 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 3 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 3 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_LT_I32 Set SCC to 1 iff the first scalar input is less than the second scalar input. ENC_SOPC default 4 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 4 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 4 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 4 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_LE_I32 Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input. ENC_SOPC default 5 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 5 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 5 SSRC0 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 5 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_EQ_U32 Set SCC to 1 iff the first scalar input is equal to the second scalar input. ENC_SOPC default 6 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 6 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 6 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 6 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_LG_U32 Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. ENC_SOPC default 7 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 7 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 7 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 7 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_GT_U32 Set SCC to 1 iff the first scalar input is greater than the second scalar input. ENC_SOPC default 8 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 8 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 8 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 8 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_GE_U32 Set SCC to 1 iff the first scalar input is greater than or equal to the second scalar input. ENC_SOPC default 9 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 9 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 9 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 9 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_LT_U32 Set SCC to 1 iff the first scalar input is less than the second scalar input. ENC_SOPC default 10 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 10 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 10 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 10 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_LE_U32 Set SCC to 1 iff the first scalar input is less than or equal to the second scalar input. ENC_SOPC default 11 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 11 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 11 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 11 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BITCMP0_B32 Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0. ENC_SOPC default 12 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 12 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 12 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 12 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BITCMP1_B32 Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1. ENC_SOPC default 13 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 13 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 13 SSRC0 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 13 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BITCMP0_B64 Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 0. ENC_SOPC default 14 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 14 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 14 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 14 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_BITCMP1_B64 Extract a bit from the first scalar input based on an index in the second scalar input, and set SCC to 1 iff the extracted bit is equal to 1. ENC_SOPC default 15 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 15 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 15 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 15 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U32 OPR_SSRC_NOLDS 32 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_EQ_U64 Set SCC to 1 iff the first scalar input is equal to the second scalar input. ENC_SOPC default 18 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 18 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 18 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 18 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMP_LG_U64 Set SCC to 1 iff the first scalar input is less than or greater than the second scalar input. ENC_SOPC default 19 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0 19 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SSRC1 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_1 19 SSRC0 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SOPC_INST_LITERAL has_lit_0_has_lit_1 19 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 SIMM32 FMT_NUM_U64 OPR_SSRC_NOLDS 64 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_MOVK_I32 Sign extend a literal 16-bit constant and store the result into a scalar register. ENC_SOPK default 0 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 SALU FALSE FALSE FALSE FALSE TRUE S_VERSION Perform no operation. This opcode is used to specify the microcode version for tools that interpret shader microcode. ENC_SOPK default 1 SIMM16 FMT_NUM_B16 OPR_VERSION 16 WAVE_CONTROL FALSE FALSE FALSE FALSE FALSE S_CMOVK_I32 Move the sign extension of a literal 16-bit constant into a scalar register iff SCC is nonzero. ENC_SOPK default 2 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_EQ_I32 Set SCC to 1 iff scalar input is equal to the sign extension of a literal 16-bit constant. ENC_SOPK default 3 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_LG_I32 Set SCC to 1 iff scalar input is less than or greater than the sign extension of a literal 16-bit constant. ENC_SOPK default 4 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_GT_I32 Set SCC to 1 iff scalar input is greater than the sign extension of a literal 16-bit constant. ENC_SOPK default 5 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_GE_I32 Set SCC to 1 iff scalar input is greater than or equal to the sign extension of a literal 16-bit constant. ENC_SOPK default 6 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_LT_I32 Set SCC to 1 iff scalar input is less than the sign extension of a literal 16-bit constant. ENC_SOPK default 7 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_LE_I32 Set SCC to 1 iff scalar input is less than or equal to the sign extension of a literal 16-bit constant. ENC_SOPK default 8 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_EQ_U32 Set SCC to 1 iff scalar input is equal to the zero extension of a literal 16-bit constant. ENC_SOPK default 9 SDST FMT_NUM_U32 OPR_SDST 32 SIMM16 FMT_NUM_U16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_LG_U32 Set SCC to 1 iff scalar input is less than or greater than the zero extension of a literal 16-bit constant. ENC_SOPK default 10 SDST FMT_NUM_U32 OPR_SDST 32 SIMM16 FMT_NUM_U16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_GT_U32 Set SCC to 1 iff scalar input is greater than the zero extension of a literal 16-bit constant. ENC_SOPK default 11 SDST FMT_NUM_U32 OPR_SDST 32 SIMM16 FMT_NUM_U16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_GE_U32 Set SCC to 1 iff scalar input is greater than or equal to the zero extension of a literal 16-bit constant. ENC_SOPK default 12 SDST FMT_NUM_U32 OPR_SDST 32 SIMM16 FMT_NUM_U16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_LT_U32 Set SCC to 1 iff scalar input is less than the zero extension of a literal 16-bit constant. ENC_SOPK default 13 SDST FMT_NUM_U32 OPR_SDST 32 SIMM16 FMT_NUM_U16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_CMPK_LE_U32 Set SCC to 1 iff scalar input is less than or equal to the zero extension of a literal 16-bit constant. ENC_SOPK default 14 SDST FMT_NUM_U32 OPR_SDST 32 SIMM16 FMT_NUM_U16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_ADDK_I32 Add a scalar input and the sign extension of a literal 16-bit constant, store the result into a scalar register and store the carry-out bit into SCC. ENC_SOPK default 15 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU FALSE FALSE FALSE FALSE FALSE S_MULK_I32 Multiply a scalar input with the sign extension of a literal 16-bit constant and store the result into a scalar register. ENC_SOPK default 16 SDST FMT_NUM_I32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_SIMM16 16 SALU FALSE FALSE FALSE FALSE FALSE S_GETREG_B32 Read some or all of a hardware register into the LSBs of destination. ENC_SOPK default 18 SDST FMT_NUM_B32 OPR_SDST 32 SIMM16 FMT_NUM_B16 OPR_HWREG 16 SALU FALSE FALSE FALSE FALSE FALSE S_SETREG_B32 Write some or all of the LSBs of source argument into a hardware register. ENC_SOPK default 19 SIMM16 FMT_NUM_B16 OPR_HWREG 16 SDST FMT_NUM_B32 OPR_SDST 32 SALU FALSE FALSE FALSE FALSE FALSE S_SETREG_IMM32_B32 Write some or all of the LSBs of a 32-bit literal constant into a hardware register; this instruction requires a 32-bit literal constant. SOPK_INST_LITERAL default 21 SIMM16 FMT_NUM_B16 OPR_HWREG 16 FMT_NUM_B32 OPR_SIMM32 32 SALU TRUE FALSE FALSE FALSE FALSE S_CALL_B64 Store the address of the next instruction to a scalar register and then jump to a constant offset relative to the current PC. ENC_SOPK default 22 SDST FMT_NUM_B64 OPR_SDST 64 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_B64 OPR_PC 64 FMT_NUM_B64 OPR_PC 64 SALU FALSE FALSE FALSE FALSE TRUE S_WAITCNT_VSCNT Wait for the VSCNT counter to be at or below the specified level. The VSCNT counter tracks the number of outstanding vector memory stores and atomics that do not return data. This counter is not used in 'all-in-order' mode. ENC_SOPK default 23 SDST FMT_NUM_B32 OPR_SDST 32 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_WAITCNT_VMCNT Wait for the VMCNT counter to be at or below the specified level. The VMCNT counter tracks the number of outstanding vector memory loads and atomics that do return data. When in 'all-in-order' mode, wait for all load and store vector memory events. ENC_SOPK default 24 SDST FMT_NUM_B32 OPR_SDST 32 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_WAITCNT_EXPCNT Wait for the EXPCNT counter to be at or below the specified level. The EXPCNT counter tracks the number of outstanding export events. ENC_SOPK default 25 SDST FMT_NUM_B32 OPR_SDST 32 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_WAITCNT_LGKMCNT Wait for the LGKMCNT counter to be at or below the specified level. The LGKMCNT counter tracks the number of outstanding local data share (L), global data share (G), scalar memory (K) and message (M) events. ENC_SOPK default 26 SDST FMT_NUM_B32 OPR_SDST 32 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL TRUE TRUE FALSE FALSE FALSE S_SUBVECTOR_LOOP_BEGIN Begin execution of a subvector block of code. ENC_SOPK default 27 SDST FMT_NUM_B32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU TRUE TRUE FALSE FALSE FALSE S_SUBVECTOR_LOOP_END End execution of a subvector block of code. ENC_SOPK default 28 SDST FMT_NUM_B32 OPR_SDST 32 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_M64 OPR_SDST_EXEC 64 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE TRUE S_NOP Do nothing. Delay issue of next instruction by a small, fixed amount. ENC_SOPP default 0 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE TRUE FALSE S_ENDPGM End of program; terminate wavefront. ENC_SOPP default 1 MESSAGE TRUE FALSE FALSE FALSE FALSE S_BRANCH Jump to a constant offset relative to the current PC. ENC_SOPP default 2 SIMM16 FMT_NUM_I16 OPR_LABEL 16 SALU FALSE FALSE FALSE FALSE FALSE S_WAKEUP Allow a wave to 'ping' all the other waves in its threadgroup to force them to wake up early from an S_SLEEP instruction. ENC_SOPP default 3 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_SCC0 If SCC is 0 then jump to a constant offset relative to the current PC. ENC_SOPP default 4 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_SCC1 If SCC is 1 then jump to a constant offset relative to the current PC. ENC_SOPP default 5 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_B1 OPR_SSRC_SPECIAL_SCC 1 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_VCCZ If VCCZ is 1 then jump to a constant offset relative to the current PC. ENC_SOPP default 6 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_M64 OPR_VCC 64 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_VCCNZ If VCCZ is 0 then jump to a constant offset relative to the current PC. ENC_SOPP default 7 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_M64 OPR_VCC 64 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_EXECZ If EXECZ is 1 then jump to a constant offset relative to the current PC. ENC_SOPP default 8 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_EXECNZ If EXECZ is 0 then jump to a constant offset relative to the current PC. ENC_SOPP default 9 SIMM16 FMT_NUM_I16 OPR_LABEL 16 FMT_NUM_M64 OPR_SDST_EXEC 64 SALU FALSE FALSE FALSE FALSE FALSE S_BARRIER Synchronize waves within a threadgroup. ENC_SOPP default 10 SALU FALSE FALSE FALSE FALSE TRUE S_SETKILL Kill this wave if the least significant bit of the immediate constant is 1. ENC_SOPP default 11 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_WAITCNT Wait for the counts of outstanding local data share, vector memory and export instructions to be at or below the specified levels. ENC_SOPP default 12 SIMM16 FMT_NUM_B16 OPR_WAITCNT 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_SETHALT Set or clear the HALT status bit. ENC_SOPP default 13 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_SLEEP Cause a wave to sleep for up to ~8000 clocks. ENC_SOPP default 14 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_SETPRIO Change wave user priority. ENC_SOPP default 15 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE FALSE S_SENDMSG Send a message upstream to graphics control hardware. ENC_SOPP default 16 SIMM16 FMT_NUM_B16 OPR_SENDMSG 16 FMT_NUM_B32 OPR_SDST_M0 32 SALU FALSE FALSE FALSE FALSE FALSE S_SENDMSGHALT Send a message to upstream control hardware and then HALT the wavefront; see S_SENDMSG for details. ENC_SOPP default 17 SIMM16 FMT_NUM_B16 OPR_SENDMSG 16 FMT_NUM_B32 OPR_SDST_M0 32 SALU TRUE FALSE TRUE FALSE FALSE S_TRAP Enter the trap handler. ENC_SOPP default 18 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 TRAP FALSE FALSE FALSE FALSE FALSE S_ICACHE_INV Invalidate entire first level instruction cache. ENC_SOPP default 19 SALU FALSE FALSE FALSE FALSE FALSE S_INCPERFLEVEL Increment performance counter specified in SIMM16[3:0] by 1. ENC_SOPP default 20 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 SALU FALSE FALSE FALSE FALSE FALSE S_DECPERFLEVEL Decrement performance counter specified in SIMM16[3:0] by 1. ENC_SOPP default 21 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 SALU FALSE FALSE FALSE FALSE FALSE S_TTRACEDATA Send M0 as user data to the thread trace stream. ENC_SOPP default 22 FMT_NUM_B32 OPR_SDST_M0 32 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_CDBGSYS If the system debug flag is set then jump to a constant offset relative to the current PC. ENC_SOPP default 23 SIMM16 FMT_NUM_I16 OPR_LABEL 16 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_CDBGUSER If the user debug flag is set then jump to a constant offset relative to the current PC. ENC_SOPP default 24 SIMM16 FMT_NUM_I16 OPR_LABEL 16 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_CDBGSYS_OR_USER If either the system debug flag or the user debug flag is set then jump to a constant offset relative to the current PC. ENC_SOPP default 25 SIMM16 FMT_NUM_I16 OPR_LABEL 16 SALU TRUE TRUE FALSE FALSE FALSE S_CBRANCH_CDBGSYS_AND_USER If both the system debug flag and the user debug flag are set then jump to a constant offset relative to the current PC. ENC_SOPP default 26 SIMM16 FMT_NUM_I16 OPR_LABEL 16 SALU FALSE FALSE FALSE TRUE FALSE S_ENDPGM_SAVED End of program; signal that a wave has been saved by the context-switch trap handler and terminate wavefront. ENC_SOPP default 27 MESSAGE FALSE FALSE FALSE TRUE FALSE S_ENDPGM_ORDERED_PS_DONE End of program; signal that a wave has exited its POPS critical section and terminate wavefront. ENC_SOPP default 30 MESSAGE TRUE FALSE TRUE FALSE FALSE S_CODE_END Generate an illegal instruction interrupt. This instruction is used to mark the end of a shader buffer for debug tools. ENC_SOPP default 31 SALU FALSE FALSE FALSE FALSE TRUE S_INST_PREFETCH Change instruction prefetch mode. This controls how many cachelines ahead of the current PC the shader attempts to prefetch. ENC_SOPP default 32 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_CLAUSE Mark the beginning of a clause. ENC_SOPP default 33 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_WAIT_IDLE Wait for all activity in the wave to be complete (all dependency and memory counters at zero). ENC_SOPP default 34 WAVE_CONTROL FALSE FALSE FALSE FALSE TRUE S_WAITCNT_DEPCTR Wait for one or more ALU-centric counters to fall below specified values. Used in expert scheduling mode. ENC_SOPP default 35 SIMM16 FMT_NUM_B16 OPR_WAITCNT_DEPCTR 16 WAVE_CONTROL FALSE FALSE FALSE FALSE FALSE S_ROUND_MODE Set floating point round mode using an immediate constant. ENC_SOPP default 36 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 SALU FALSE FALSE FALSE FALSE FALSE S_DENORM_MODE Set floating point denormal mode using an immediate constant. ENC_SOPP default 37 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 SALU FALSE FALSE FALSE FALSE FALSE S_TTRACEDATA_IMM Send SIMM16[7:0] as user data to the thread trace stream. ENC_SOPP default 40 SIMM16 FMT_NUM_B16 OPR_SIMM16 16 FMT_NUM_B32 OPR_SDST_M0 32 SALU FALSE FALSE FALSE FALSE FALSE V_INTERP_P1_F32 Given the I coordinate in a vector register and an attribute specifier, load parameter data from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F32 to complete the operation. ENC_VINTRP default 0 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC FMT_NUM_F32 OPR_VGPR 32 ATTR FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP3 default 512 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0 512 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_1 512 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 512 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_INTERP_P2_F32 Given the J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in the destination vector register, load parameter data from the local data share, compute the second part of parameter interpolation and store the final result into a vector register. ENC_VINTRP default 1 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC FMT_NUM_F32 OPR_VGPR 32 ATTR FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP3 default 513 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0 513 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_1 513 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 513 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_INTERP_MOV_F32 Given an attribute specifier and a parameter ID (P0, P10 or P20), load one of the parameter values from the local data share into a vector register. ENC_VINTRP default 2 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC FMT_ANY OPR_PARAM 32 ATTR FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP3 default 514 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_ANY OPR_PARAM 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0 514 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_ANY OPR_PARAM 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_1 514 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_ANY OPR_PARAM 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 514 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_ANY OPR_PARAM 32 SRC0 FMT_ANY OPR_ATTR 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_NOP Do nothing. ENC_VOP1 default 0 ENC_VOP3 default 384 VALU FALSE FALSE FALSE FALSE FALSE V_MOV_B32 Move data from a vector input into a vector register. VOP1_VOP_DPP16 default 1 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 VOP1_VOP_DPP8 default 1 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 VOP1_VOP_SDWA default 1 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 1 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 1 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 ENC_VOP3 default 385 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 385 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_READFIRSTLANE_B32 Read the scalar value in the lowest active lane of the input vector register and store it into a scalar register. ENC_VOP1 default 2 VDST FMT_NUM_B32 OPR_SREG 32 SRC0 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 VOP1_INST_LITERAL has_lit 2 VDST FMT_NUM_B32 OPR_SREG 32 SIMM32 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 ENC_VOP3 default 386 VDST FMT_NUM_B32 OPR_SREG 32 SRC0 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 VOP3_INST_LITERAL has_lit_0 386 VDST FMT_NUM_B32 OPR_SREG 32 SRC0 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_I32_F64 Convert from a double-precision float input to a signed 32-bit integer value and store the result into a vector register. ENC_VOP1 default 3 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 3 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 387 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 387 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F64_I32 Convert from a signed 32-bit integer input to a double-precision float value and store the result into a vector register. ENC_VOP1 default 4 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 4 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 ENC_VOP3 default 388 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 388 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_I32 Convert from a signed 32-bit integer input to a single-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 5 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VOP1_VOP_DPP8 default 5 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VOP1_VOP_SDWA default 5 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 5 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 5 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 ENC_VOP3 default 389 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 389 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_U32 Convert from an unsigned 32-bit integer input to a single-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 6 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 6 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 6 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 6 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 6 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 390 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 390 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_U32_F32 Convert from a single-precision float input to an unsigned 32-bit integer value and store the result into a vector register. VOP1_VOP_DPP16 default 7 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 7 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 7 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 7 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 7 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 391 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 391 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_I32_F32 Convert from a single-precision float input to a signed 32-bit integer value and store the result into a vector register. VOP1_VOP_DPP16 default 8 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 8 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 8 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 8 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 8 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 392 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 392 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F16_F32 Convert from a single-precision float input to a half-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 10 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 10 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 10 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 10 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 10 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 394 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 394 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_F16 Convert from a half-precision float input to a single-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 11 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 11 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 11 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 11 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 11 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 395 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 395 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_RPI_I32_F32 Convert from a single-precision float input to a signed 32-bit integer value using round to nearest integer semantics (ignore the default rounding mode) and store the result into a vector register. VOP1_VOP_DPP16 default 12 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 12 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 12 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 12 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 12 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 396 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 396 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_FLR_I32_F32 Convert from a single-precision float input to a signed 32-bit integer value using round-down semantics (ignore the default rounding mode) and store the result into a vector register. VOP1_VOP_DPP16 default 13 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 13 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 13 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 13 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 13 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 397 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 397 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_OFF_F32_I4 Convert from a signed 4-bit integer input to a single-precision float value using an offset table and store the result into a vector register. VOP1_VOP_DPP16 default 14 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VOP1_VOP_DPP8 default 14 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VOP1_VOP_SDWA default 14 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 14 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 14 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 ENC_VOP3 default 398 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 398 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_F64 Convert from a double-precision float input to a single-precision float value and store the result into a vector register. ENC_VOP1 default 15 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 15 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 399 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 399 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F64_F32 Convert from a single-precision float input to a double-precision float value and store the result into a vector register. ENC_VOP1 default 16 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 16 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 400 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 400 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_UBYTE0 Convert an unsigned byte in byte 0 of the input to a single-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 17 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 17 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 17 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 17 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 17 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 401 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 401 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_UBYTE1 Convert an unsigned byte in byte 1 of the input to a single-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 18 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 18 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 18 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 18 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 18 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 402 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 402 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_UBYTE2 Convert an unsigned byte in byte 2 of the input to a single-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 19 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 19 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 19 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 19 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 19 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 403 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 403 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F32_UBYTE3 Convert an unsigned byte in byte 3 of the input to a single-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 20 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 20 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 20 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 20 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 20 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 404 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 404 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_U32_F64 Convert from a double-precision float input to an unsigned 32-bit integer value and store the result into a vector register. ENC_VOP1 default 21 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 21 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 405 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 405 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F64_U32 Convert from an unsigned 32-bit integer input to a double-precision float value and store the result into a vector register. ENC_VOP1 default 22 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 22 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 406 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 406 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_TRUNC_F64 Compute the integer part of a double-precision float input using round toward zero semantics and store the result in floating point format into a vector register. ENC_VOP1 default 23 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 23 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 407 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 407 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_CEIL_F64 Round the double-precision float input up to next integer and store the result in floating point format into a vector register. ENC_VOP1 default 24 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 24 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 408 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 408 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_RNDNE_F64 Round the double-precision float input to the nearest even integer and store the result in floating point format into a vector register. ENC_VOP1 default 25 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 25 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 409 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 409 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_FLOOR_F64 Round the double-precision float input down to previous integer and store the result in floating point format into a vector register. ENC_VOP1 default 26 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 26 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 410 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 410 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_PIPEFLUSH Flush the vector ALU pipeline through the destination cache. ENC_VOP1 default 27 ENC_VOP3 default 411 VALU FALSE FALSE FALSE FALSE FALSE V_FRACT_F32 Compute the fractional portion of a single-precision float input and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 32 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 32 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 32 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 32 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 32 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 416 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 416 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_TRUNC_F32 Compute the integer part of a single-precision float input using round toward zero semantics and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 33 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 33 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 33 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 33 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 33 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 417 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 417 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CEIL_F32 Round the single-precision float input up to next integer and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 34 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 34 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 34 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 34 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 34 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 418 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 418 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_RNDNE_F32 Round the single-precision float input to the nearest even integer and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 35 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 35 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 35 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 35 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 35 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 419 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 419 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_FLOOR_F32 Round the single-precision float input down to previous integer and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 36 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 36 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 36 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 36 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 36 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 420 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 420 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_EXP_F32 Calculate 2 raised to the power of the single-precision float input and store the result into a vector register. VOP1_VOP_DPP16 default 37 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 37 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 37 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 37 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 37 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 421 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 421 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_LOG_F32 Calculate the base 2 logarithm of the single-precision float input and store the result into a vector register. VOP1_VOP_DPP16 default 39 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 39 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 39 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 39 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 39 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 423 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 423 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_RCP_F32 Calculate the reciprocal of the single-precision float input using IEEE rules and store the result into a vector register. VOP1_VOP_DPP16 default 42 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 42 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 42 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 42 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 42 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 426 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 426 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_RCP_IFLAG_F32 Calculate the reciprocal of the vector float input in a manner suitable for integer division and store the result into a vector register. This opcode is intended for use as part of an integer division macro. VOP1_VOP_DPP16 default 43 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 43 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 43 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 43 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 43 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 427 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 427 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_RSQ_F32 Calculate the reciprocal of the square root of the single-precision float input using IEEE rules and store the result into a vector register. VOP1_VOP_DPP16 default 46 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 46 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 46 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 46 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 46 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 430 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 430 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_RCP_F64 Calculate the reciprocal of the double-precision float input using IEEE rules and store the result into a vector register. ENC_VOP1 default 47 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 47 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 431 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 431 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_RSQ_F64 Calculate the reciprocal of the square root of the double-precision float input using IEEE rules and store the result into a vector register. ENC_VOP1 default 49 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 49 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 433 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 433 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_SQRT_F32 Calculate the square root of the single-precision float input using IEEE rules and store the result into a vector register. VOP1_VOP_DPP16 default 51 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 51 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 51 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 51 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 51 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 435 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 435 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_SQRT_F64 Calculate the square root of the double-precision float input using IEEE rules and store the result into a vector register. ENC_VOP1 default 52 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 52 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 436 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 436 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_SIN_F32 Calculate the trigonometric sine of a single-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI. VOP1_VOP_DPP16 default 53 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 53 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 53 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 53 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 53 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 437 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 437 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_COS_F32 Calculate the trigonometric cosine of a single-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI. VOP1_VOP_DPP16 default 54 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 54 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 54 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 54 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 54 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 438 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 438 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_NOT_B32 Calculate bitwise negation on a vector input and store the result into a vector register. VOP1_VOP_DPP16 default 55 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 55 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 55 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 55 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 55 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 439 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 439 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_BFREV_B32 Reverse the order of bits in a vector input and store the result into a vector register. VOP1_VOP_DPP16 default 56 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 VOP1_VOP_DPP8 default 56 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 VOP1_VOP_SDWA default 56 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 56 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 56 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 ENC_VOP3 default 440 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 440 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_FFBH_U32 Count the number of leading "0" bits before the first "1" in a vector input and store the result into a vector register. Store -1 if there are no "1" bits. VOP1_VOP_DPP16 default 57 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 57 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 57 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 57 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 57 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 441 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 441 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_FFBL_B32 Count the number of trailing "0" bits before the first "1" in a vector input and store the result into a vector register. Store -1 if there are no "1" bits in the input. VOP1_VOP_DPP16 default 58 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_DPP8 default 58 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VOP1_VOP_SDWA default 58 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 58 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 58 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 ENC_VOP3 default 442 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 442 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_FFBH_I32 Count the number of leading bits that are the same as the sign bit of a vector input and store the result into a vector register. Store -1 if all input bits are the same. VOP1_VOP_DPP16 default 59 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VOP1_VOP_DPP8 default 59 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VOP1_VOP_SDWA default 59 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 59 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 59 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 ENC_VOP3 default 443 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 443 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_FREXP_EXP_I32_F64 Extract the exponent of a double-precision float input and store the result as a signed 32-bit integer into a vector register. ENC_VOP1 default 60 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 60 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 444 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 444 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_FREXP_MANT_F64 Extract the binary significand, or mantissa, of a double-precision float input and store the result as a double-precision float into a vector register. ENC_VOP1 default 61 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 61 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 445 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 445 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_FRACT_F64 Compute the fractional portion of a double-precision float input and store the result in floating point format into a vector register. ENC_VOP1 default 62 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP1_INST_LITERAL has_lit 62 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOP3 default 446 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 446 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_FREXP_EXP_I32_F32 Extract the exponent of a single-precision float input and store the result as a signed 32-bit integer into a vector register. VOP1_VOP_DPP16 default 63 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 63 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 63 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 63 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 63 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 447 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 447 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_FREXP_MANT_F32 Extract the binary significand, or mantissa, of a single-precision float input and store the result as a single-precision float into a vector register. VOP1_VOP_DPP16 default 64 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_DPP8 default 64 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VOP1_VOP_SDWA default 64 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP1 default 64 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP1_INST_LITERAL has_lit 64 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 ENC_VOP3 default 448 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 448 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CLREXCP Clear this wave's exception state in the vector ALU. ENC_VOP1 default 65 ENC_VOP3 default 449 VALU FALSE FALSE FALSE FALSE FALSE V_MOVRELD_B32 Move data from a vector input into a relatively-indexed vector register. VOP1_VOP_DPP16 default 66 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_DPP8 default 66 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_SDWA default 66 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_SIMPLE 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP1 default 66 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_INST_LITERAL has_lit 66 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP3 default 450 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0 450 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_MOVRELS_B32 Move data from a relatively-indexed vector register into another vector register. VOP1_VOP_DPP16 default 67 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_DPP8 default 67 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_SDWA default 67 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP1 default 67 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_INST_LITERAL has_lit 67 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP3 default 451 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0 451 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_MOVRELSD_B32 Move data from a relatively-indexed vector register into another relatively-indexed vector register. VOP1_VOP_DPP16 default 68 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_DPP8 default 68 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_SDWA default 68 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP1 default 68 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_INST_LITERAL has_lit 68 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP3 default 452 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0 452 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_MOVRELSD_2_B32 Move data from a relatively-indexed vector register into another relatively-indexed vector register, using different offsets for each index. VOP1_VOP_DPP16 default 72 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_DPP8 default 72 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_VOP_SDWA default 72 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP1 default 72 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP1_INST_LITERAL has_lit 72 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 ENC_VOP3 default 456 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VOP3_INST_LITERAL has_lit_0 456 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F16_U16 Convert from an unsigned 16-bit integer input to a half-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 80 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_U16 OPR_VGPR 16 VOP1_VOP_DPP8 default 80 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_U16 OPR_VGPR 16 VOP1_VOP_SDWA default 80 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 80 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 80 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 ENC_VOP3 default 464 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 464 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_F16_I16 Convert from a signed 16-bit integer input to a half-precision float value and store the result into a vector register. VOP1_VOP_DPP16 default 81 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_I16 OPR_VGPR 16 VOP1_VOP_DPP8 default 81 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_I16 OPR_VGPR 16 VOP1_VOP_SDWA default 81 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 81 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 81 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 ENC_VOP3 default 465 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 465 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_U16_F16 Convert from a half-precision float input to an unsigned 16-bit integer value and store the result into a vector register. VOP1_VOP_DPP16 default 82 VDST FMT_NUM_U16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 82 VDST FMT_NUM_U16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 82 VDST FMT_NUM_U16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 82 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 82 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 466 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 466 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_I16_F16 Convert from a half-precision float input to a signed 16-bit integer value and store the result into a vector register. VOP1_VOP_DPP16 default 83 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 83 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 83 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 83 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 83 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 467 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 467 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_RCP_F16 Calculate the reciprocal of the half-precision float input using IEEE rules and store the result into a vector register. VOP1_VOP_DPP16 default 84 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 84 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 84 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 84 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 84 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 468 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 468 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_SQRT_F16 Calculate the square root of the half-precision float input using IEEE rules and store the result into a vector register. VOP1_VOP_DPP16 default 85 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 85 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 85 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 85 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 85 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 469 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 469 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_RSQ_F16 Calculate the reciprocal of the square root of the half-precision float input using IEEE rules and store the result into a vector register. VOP1_VOP_DPP16 default 86 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 86 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 86 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 86 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 86 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 470 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 470 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_LOG_F16 Calculate the base 2 logarithm of the half-precision float input and store the result into a vector register. VOP1_VOP_DPP16 default 87 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 87 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 87 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 87 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 87 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 471 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 471 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_EXP_F16 Calculate 2 raised to the power of the half-precision float input and store the result into a vector register. VOP1_VOP_DPP16 default 88 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 88 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 88 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 88 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 88 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 472 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 472 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_FREXP_MANT_F16 Extract the binary significand, or mantissa, of a half-precision float input and store the result as a half-precision float into a vector register. VOP1_VOP_DPP16 default 89 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 89 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 89 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 89 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 89 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 473 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 473 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_FREXP_EXP_I16_F16 Extract the exponent of a half-precision float input and store the result as a signed 16-bit integer into a vector register. VOP1_VOP_DPP16 default 90 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 90 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 90 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 90 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 90 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 474 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 474 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_FLOOR_F16 Round the half-precision float input down to previous integer and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 91 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 91 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 91 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 91 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 91 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 475 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 475 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_CEIL_F16 Round the half-precision float input up to next integer and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 92 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 92 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 92 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 92 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 92 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 476 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 476 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_TRUNC_F16 Compute the integer part of a half-precision float input using round toward zero semantics and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 93 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 93 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 93 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 93 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 93 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 477 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 477 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_RNDNE_F16 Round the half-precision float input to the nearest even integer and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 94 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 94 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 94 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 94 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 94 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 478 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 478 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_FRACT_F16 Compute the fractional portion of a half-precision float input and store the result in floating point format into a vector register. VOP1_VOP_DPP16 default 95 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 95 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 95 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 95 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 95 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 479 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 479 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_SIN_F16 Calculate the trigonometric sine of a half-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI. VOP1_VOP_DPP16 default 96 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 96 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 96 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 96 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 96 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 480 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 480 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_COS_F16 Calculate the trigonometric cosine of a half-precision float value using IEEE rules and store the result into a vector register. The operand is calculated by scaling the vector input by 2 PI. VOP1_VOP_DPP16 default 97 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 97 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 97 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 97 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 97 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 481 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 481 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_SAT_PK_U8_I16 Given two 16-bit unsigned integer inputs, saturate each input over an 8-bit unsigned range, pack the resulting values into a 16-bit word and store the result into a vector register. VOP1_VOP_DPP16 default 98 VDST FMT_NUM_PK_U8 OPR_VGPR 32 VSRC0 FMT_NUM_PK_I16 OPR_VGPR 32 VOP1_VOP_DPP8 default 98 VDST FMT_NUM_PK_U8 OPR_VGPR 32 VSRC0 FMT_NUM_PK_I16 OPR_VGPR 32 VOP1_VOP_SDWA default 98 VDST FMT_NUM_PK_U8 OPR_VGPR 32 VSRC0 FMT_NUM_PK_I16 OPR_SRC_SIMPLE 32 ENC_VOP1 default 98 VDST FMT_NUM_PK_U8 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 VOP1_INST_LITERAL has_lit 98 VDST FMT_NUM_PK_U8 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 ENC_VOP3 default 482 VDST FMT_NUM_PK_U8 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 VOP3_INST_LITERAL has_lit_0 482 VDST FMT_NUM_PK_U8 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_NORM_I16_F16 Convert from a half-precision float input to a signed normalized short and store the result into a vector register. VOP1_VOP_DPP16 default 99 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 99 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 99 VDST FMT_NUM_I16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 99 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 99 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 483 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 483 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_NORM_U16_F16 Convert from a half-precision float input to an unsigned normalized short and store the result into a vector register. VOP1_VOP_DPP16 default 100 VDST FMT_NUM_U16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_DPP8 default 100 VDST FMT_NUM_U16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VOP1_VOP_SDWA default 100 VDST FMT_NUM_U16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP1 default 100 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP1_INST_LITERAL has_lit 100 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 ENC_VOP3 default 484 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VOP3_INST_LITERAL has_lit_0 484 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VALU FALSE FALSE FALSE FALSE FALSE V_SWAP_B32 Swap the values in two vector registers. ENC_VOP1 default 101 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_SWAPREL_B32 Swap the values in two relatively-indexed vector registers. ENC_VOP1 default 104 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 FMT_NUM_B32 OPR_SDST_M0 32 VALU FALSE FALSE FALSE FALSE FALSE V_CNDMASK_B32 Copy data from one of two inputs based on the vector condition code and store the result into a vector register. VOP2_VOP_DPP16 default 1 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_DPP8 default 1 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_VGPR 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_SDWA default 1 VDST FMT_NUM_B32 OPR_VGPR 32 VSRC0 FMT_NUM_B32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_B32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_VCC 64 ENC_VOP2 default 1 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_INST_LITERAL has_lit 1 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 ENC_VOP3 default 257 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_INST_LITERAL has_lit_0 257 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_INST_LITERAL has_lit_1 257 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 257 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VALU FALSE FALSE FALSE FALSE FALSE V_DOT2C_F32_F16 Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate the resulting single-precision float value into the destination vector register. VOP2_VOP_DPP16 default 2 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_PK_F16 OPR_VGPR 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 VOP2_VOP_DPP8 default 2 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_PK_F16 OPR_VGPR 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 ENC_VOP2 default 2 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 2 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 ENC_VOP3 default 258 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 258 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 258 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 258 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_F32 Add two floating point inputs and store the result into a vector register. VOP2_VOP_DPP16 default 3 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 3 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 3 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 3 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 3 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 259 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 259 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 259 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 259 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_F32 Subtract the second floating point input from the first input and store the result into a vector register. VOP2_VOP_DPP16 default 4 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 4 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 4 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 4 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 4 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 260 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 260 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 260 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 260 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SUBREV_F32 Subtract the first floating point input from the second input and store the result into a vector register. VOP2_VOP_DPP16 default 5 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 5 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 5 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 5 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 5 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 261 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 261 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 261 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 261 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAC_LEGACY_F32 Multiply and add single-precision values, accumulate with destination. Follows DX9 rules where 0.0 times anything produces 0.0. ENC_VOP2 default 6 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 6 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 262 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 262 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 262 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 262 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_LEGACY_F32 Multiply two floating point inputs and store the result in a vector register. Follows DX9 rules where 0.0 times anything produces 0.0 (this differs from other APIs when the other input is infinity or NaN). VOP2_VOP_DPP16 default 7 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 7 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 7 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 7 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 7 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 263 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 263 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 263 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 263 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_F32 Multiply two floating point inputs and store the result into a vector register. VOP2_VOP_DPP16 default 8 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 8 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 8 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 8 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 8 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 264 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 264 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 264 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 264 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_I32_I24 Multiply two signed 24-bit integer inputs and store the result as a signed 32-bit integer into a vector register. VOP2_VOP_DPP16 default 9 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_DPP8 default 9 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_SDWA default 9 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 9 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 9 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 ENC_VOP3 default 265 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 265 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 265 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 265 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_HI_I32_I24 Multiply two signed 24-bit integer inputs and store the high 32 bits of the result as a signed 32-bit integer into a vector register. VOP2_VOP_DPP16 default 10 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_DPP8 default 10 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_SDWA default 10 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 10 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 10 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 ENC_VOP3 default 266 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 266 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 266 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 266 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_U32_U24 Multiply two unsigned 24-bit integer inputs and store the result as an unsigned 32-bit integer into a vector register. VOP2_VOP_DPP16 default 11 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 11 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 11 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 11 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 11 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 267 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 267 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 267 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 267 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_HI_U32_U24 Multiply two unsigned 24-bit integer inputs and store the high 32 bits of the result as an unsigned 32-bit integer into a vector register. VOP2_VOP_DPP16 default 12 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 12 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 12 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 12 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 12 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 268 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 268 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 268 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 268 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT4C_I32_I8 Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain and accumulate the resulting signed 32-bit integer value into the destination vector register. VOP2_VOP_DPP16 default 13 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_PK_I8 OPR_VGPR 32 VSRC1 FMT_NUM_PK_I8 OPR_VGPR 32 VOP2_VOP_DPP8 default 13 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_PK_I8 OPR_VGPR 32 VSRC1 FMT_NUM_PK_I8 OPR_VGPR 32 ENC_VOP2 default 13 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I8 OPR_SRC 32 VSRC1 FMT_NUM_PK_I8 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 13 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC 32 VSRC1 FMT_NUM_PK_I8 OPR_VGPR 32 ENC_VOP3 default 269 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I8 OPR_SRC 32 SRC1 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 269 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC 32 SRC1 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 269 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I8 OPR_SRC 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 269 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MIN_F32 Select the minimum of two single-precision float inputs and store the result into a vector register. VOP2_VOP_DPP16 default 15 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 15 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 15 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 15 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 15 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 271 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 271 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 271 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 271 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAX_F32 Select the maximum of two single-precision float inputs and store the result into a vector register. VOP2_VOP_DPP16 default 16 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 16 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 16 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 16 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 16 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 272 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 272 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 272 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 272 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MIN_I32 Select the minimum of two signed 32-bit integer inputs and store the selected value into a vector register. VOP2_VOP_DPP16 default 17 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_DPP8 default 17 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_SDWA default 17 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 17 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 17 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 ENC_VOP3 default 273 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 273 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 273 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 273 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAX_I32 Select the maximum of two signed 32-bit integer inputs and store the selected value into a vector register. VOP2_VOP_DPP16 default 18 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_DPP8 default 18 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_SDWA default 18 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 18 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 18 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 ENC_VOP3 default 274 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 274 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 274 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 274 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MIN_U32 Select the minimum of two unsigned 32-bit integer inputs and store the selected value into a vector register. VOP2_VOP_DPP16 default 19 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 19 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 19 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 19 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 19 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 275 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 275 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 275 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 275 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAX_U32 Select the maximum of two unsigned 32-bit integer inputs and store the selected value into a vector register. VOP2_VOP_DPP16 default 20 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 20 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 20 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 20 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 20 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 276 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 276 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 276 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 276 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_LSHRREV_B32 Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector register. VOP2_VOP_DPP16 default 22 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 22 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 22 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 22 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 22 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 278 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 278 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 278 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 278 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ASHRREV_I32 Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register. VOP2_VOP_DPP16 default 24 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_DPP8 default 24 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_VOP_SDWA default 24 VDST FMT_NUM_I32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 24 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 24 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 ENC_VOP3 default 280 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 280 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 280 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 280 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_LSHLREV_B32 Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector register. VOP2_VOP_DPP16 default 26 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 26 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 26 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 26 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 26 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 282 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 282 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 282 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 282 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_AND_B32 Calculate bitwise AND on two vector inputs and store the result into a vector register. VOP2_VOP_DPP16 default 27 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 27 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 27 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 27 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 27 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 283 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 283 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 283 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 283 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_OR_B32 Calculate bitwise OR on two vector inputs and store the result into a vector register. VOP2_VOP_DPP16 default 28 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 28 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 28 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 28 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 28 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 284 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 284 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 284 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 284 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_XOR_B32 Calculate bitwise XOR on two vector inputs and store the result into a vector register. VOP2_VOP_DPP16 default 29 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 29 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 29 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 29 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 29 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 285 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 285 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 285 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 285 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_XNOR_B32 Calculate bitwise XNOR on two vector inputs and store the result into a vector register. VOP2_VOP_DPP16 default 30 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 30 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 30 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 30 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 30 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 286 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 286 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 286 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 286 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAC_F32 Multiply two floating point inputs and accumulate the result into the destination register. VOP2_VOP_DPP16 default 31 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 31 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP2 default 31 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 31 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 287 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 287 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 287 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 287 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MADMK_F32 Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register. VOP2_INST_LITERAL default 32 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 FMT_NUM_F32 OPR_SIMM32 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 32 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 FMT_NUM_F32 OPR_SIMM32 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_MADAK_F32 Multiply two floating point inputs and add a literal constant, and store the result into a vector register. VOP2_INST_LITERAL default 33 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_SIMM32 32 VOP2_INST_LITERAL has_lit 33 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_SIMM32 32 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_NC_U32 Add two unsigned 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. VOP2_VOP_DPP16 default 37 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 37 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 37 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 37 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 37 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 293 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 293 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 293 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 293 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_NC_U32 Subtract the second unsigned input from the first input and store the result into a vector register. No carry-in or carry-out support. VOP2_VOP_DPP16 default 38 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 38 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 38 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 38 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 38 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 294 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 294 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 294 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 294 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SUBREV_NC_U32 Subtract the first unsigned input from the second input and store the result into a vector register. No carry-in or carry-out support. VOP2_VOP_DPP16 default 39 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_DPP8 default 39 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_VOP_SDWA default 39 VDST FMT_NUM_U32 OPR_VGPR 32 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 39 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 39 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 ENC_VOP3 default 295 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 295 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 295 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 295 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_CO_CI_U32 Add two unsigned inputs and a bit from a carry-in mask, store the result into a vector register and store the carry-out mask into a scalar register. VOP2_VOP_DPP16 default 40 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_DPP8 default 40 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_SDWA_SDST_ENC default 40 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_VCC 64 ENC_VOP2 default 40 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_INST_LITERAL has_lit 40 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP3_SDST_ENC default 296 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0 296 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1 296 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 296 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_CO_CI_U32 Subtract the second unsigned input from the first input, subtract a bit from the carry-in mask, store the result into a vector register and store the carry-out mask to a scalar register. VOP2_VOP_DPP16 default 41 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_DPP8 default 41 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_SDWA_SDST_ENC default 41 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_VCC 64 ENC_VOP2 default 41 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_INST_LITERAL has_lit 41 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP3_SDST_ENC default 297 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0 297 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1 297 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 297 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VALU FALSE FALSE FALSE FALSE FALSE V_SUBREV_CO_CI_U32 Subtract the first unsigned input from the second input, subtract a bit from the carry-in mask, store the result into a vector register and store the carry-out mask to a scalar register. VOP2_VOP_DPP16 default 42 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_DPP8 default 42 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_VGPR 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_VOP_SDWA_SDST_ENC default 42 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_VCC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_VCC 64 ENC_VOP2 default 42 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP2_INST_LITERAL has_lit 42 VDST FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_VCC 64 VOP3_SDST_ENC default 298 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0 298 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1 298 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 298 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_M64 OPR_SREG 64 VALU FALSE FALSE FALSE FALSE FALSE V_FMAC_F32 Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add. VOP2_VOP_DPP16 default 43 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 43 VDST FMT_NUM_F32 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP2 default 43 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 43 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 299 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 299 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 299 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 299 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMAMK_F32 Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the result into a vector register. VOP2_INST_LITERAL default 44 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 FMT_NUM_F32 OPR_SIMM32 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 44 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 FMT_NUM_F32 OPR_SIMM32 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMAAK_F32 Multiply two single-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register. VOP2_INST_LITERAL default 45 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_SIMM32 32 VOP2_INST_LITERAL has_lit 45 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_F32 OPR_SIMM32 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PKRTZ_F16_F32 Convert two single-precision float inputs to a packed half-precision float value using round toward zero semantics (ignore the current rounding mode), and store the result into a vector register. VOP2_VOP_DPP16 default 47 VDST FMT_NUM_PK_F16 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_DPP8 default 47 VDST FMT_NUM_PK_F16 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_VGPR 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_VOP_SDWA default 47 VDST FMT_NUM_PK_F16 OPR_VGPR 32 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP2 default 47 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 47 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 ENC_VOP3 default 303 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 303 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 303 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 303 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_F16 Add two floating point inputs and store the result into a vector register. VOP2_VOP_DPP16 default 50 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 50 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_SDWA default 50 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP2 default 50 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 50 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 306 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 306 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 306 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 306 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_F16 Subtract the second floating point input from the first input and store the result into a vector register. VOP2_VOP_DPP16 default 51 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 51 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_SDWA default 51 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP2 default 51 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 51 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 307 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 307 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 307 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 307 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_SUBREV_F16 Subtract the first floating point input from the second input and store the result into a vector register. VOP2_VOP_DPP16 default 52 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 52 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_SDWA default 52 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP2 default 52 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC_NOLDS 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 52 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 308 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 308 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 308 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 308 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_F16 Multiply two floating point inputs and store the result into a vector register. VOP2_VOP_DPP16 default 53 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 53 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_SDWA default 53 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP2 default 53 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 53 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 309 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 309 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 309 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 309 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_FMAC_F16 Multiply two floating point inputs and accumulate the result into the destination register using fused multiply add. VOP2_VOP_DPP16 default 54 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 54 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP2 default 54 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 54 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 310 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 310 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 310 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 310 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_FMAMK_F16 Multiply a half-precision float input with a literal constant and add a second half-precision float input using fused multiply add, and store the result into a vector register. VOP2_INST_LITERAL default 55 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 FMT_NUM_F16 OPR_SIMM32 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 55 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 FMT_NUM_F16 OPR_SIMM32 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_FMAAK_F16 Multiply two half-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register. VOP2_INST_LITERAL default 56 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_F16 OPR_SIMM32 16 VOP2_INST_LITERAL has_lit 56 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_F16 OPR_SIMM32 16 VALU FALSE FALSE FALSE FALSE FALSE V_MAX_F16 Select the maximum of two half-precision float inputs and store the result into a vector register. VOP2_VOP_DPP16 default 57 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 57 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_SDWA default 57 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP2 default 57 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 57 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 313 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 313 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 313 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 313 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MIN_F16 Select the minimum of two half-precision float inputs and store the result into a vector register. VOP2_VOP_DPP16 default 58 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 58 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_SDWA default 58 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP2 default 58 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 58 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 314 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 314 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 314 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 314 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_LDEXP_F16 Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register. VOP2_VOP_DPP16 default 59 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_DPP8 default 59 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_VGPR 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_VOP_SDWA default 59 VDST FMT_NUM_F16 OPR_VGPR 16 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP2 default 59 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOP2_INST_LITERAL has_lit 59 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 ENC_VOP3 default 315 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 315 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 315 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 315 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_PK_FMAC_F16 Multiply two packed half-precision float inputs component-wise and accumulate the result into the destination register using fused multiply add. VOP2_VOP_DPP16 default 60 VDST FMT_NUM_PK_F16 OPR_VGPR 32 VSRC0 FMT_NUM_PK_F16 OPR_VGPR 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 VOP2_VOP_DPP8 default 60 VDST FMT_NUM_PK_F16 OPR_VGPR 32 VSRC0 FMT_NUM_PK_F16 OPR_VGPR 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 ENC_VOP2 default 60 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 VOP2_INST_LITERAL has_lit 60 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 VSRC1 FMT_NUM_PK_F16 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_LEGACY_F32 Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0. ENC_VOP3 default 320 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 320 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 320 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 320 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 320 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 320 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 320 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 320 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_F32 Multiply two single-precision float inputs and add a third input, and store the result into a vector register. ENC_VOP3 default 321 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 321 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 321 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 321 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 321 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 321 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 321 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 321 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_I32_I24 Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register. ENC_VOP3 default 322 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I24 OPR_SRC 32 SRC1 FMT_NUM_I24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 322 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I24 OPR_SRC 32 SRC1 FMT_NUM_I24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 322 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I24 OPR_SRC 32 SIMM32 FMT_NUM_I24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 322 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I24 OPR_SRC 32 SIMM32 FMT_NUM_I24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 322 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I24 OPR_SRC 32 SRC1 FMT_NUM_I24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 322 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I24 OPR_SRC 32 SRC1 FMT_NUM_I24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 322 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I24 OPR_SRC 32 SIMM32 FMT_NUM_I24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 322 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I24 OPR_SRC 32 SIMM32 FMT_NUM_I24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_U32_U24 Multiply two unsigned 24-bit integer inputs in the unsigned 32-bit integer domain, add a unsigned 32-bit integer value from a third input, and store the result as an unsigned 32-bit integer into a vector register. ENC_VOP3 default 323 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U24 OPR_SRC 32 SRC1 FMT_NUM_U24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 323 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U24 OPR_SRC 32 SRC1 FMT_NUM_U24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 323 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U24 OPR_SRC 32 SIMM32 FMT_NUM_U24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 323 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U24 OPR_SRC 32 SIMM32 FMT_NUM_U24 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 323 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U24 OPR_SRC 32 SRC1 FMT_NUM_U24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 323 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U24 OPR_SRC 32 SRC1 FMT_NUM_U24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 323 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U24 OPR_SRC 32 SIMM32 FMT_NUM_U24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 323 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U24 OPR_SRC 32 SIMM32 FMT_NUM_U24 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CUBEID_F32 Compute the cubemap face ID of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register. ENC_VOP3 default 324 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 324 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 324 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 324 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 324 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 324 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 324 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 324 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CUBESC_F32 Compute the cubemap S coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register. ENC_VOP3 default 325 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 325 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 325 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 325 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 325 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 325 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 325 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 325 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CUBETC_F32 Compute the cubemap T coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register. ENC_VOP3 default 326 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 326 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 326 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 326 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 326 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 326 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 326 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 326 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CUBEMA_F32 Compute the cubemap major axis coordinate of a 3D coordinate specified as three single-precision float inputs. Store the result in single-precision float format into a vector register. ENC_VOP3 default 327 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 327 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 327 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 327 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 327 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 327 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 327 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 327 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_BFE_U32 Extract an unsigned bitfield from the first input using field offset from the second input and size from the third input, then store the result into a vector register. ENC_VOP3 default 328 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 328 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 328 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 328 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 328 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 328 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 328 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 328 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_BFE_I32 Extract a signed bitfield from the first input using field offset from the second input and size from the third input, then store the result into a vector register. ENC_VOP3 default 329 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 329 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 329 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 329 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 329 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 329 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 329 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 329 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_BFI_B32 Overwrite a bitfield in the third input with a bitfield from the second input using a mask from the first input, then store the result into a vector register. ENC_VOP3 default 330 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 330 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 330 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 330 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 330 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 330 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 330 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 330 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMA_F32 Multiply two single-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. ENC_VOP3 default 331 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 331 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 331 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 331 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 331 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 331 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 331 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 331 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMA_F64 Multiply two double-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. ENC_VOP3 default 332 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 332 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 332 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 332 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_2 332 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_2 332 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1_has_lit_2 332 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 332 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_LERP_U8 Average two 4-D vectors stored as packed bytes in the first two inputs with rounding control provided by the third input, then store the result into a vector register. Each byte in the third input acts as a rounding mode for the corresponding element; if the LSB is set then 0.5 rounds up, otherwise 0.5 truncates. ENC_VOP3 default 333 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 333 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 333 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 333 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 333 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 333 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 333 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 333 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ALIGNBIT_B32 Align a 64-bit value encoded in the first two inputs to a bit position specified in the third input, then store the result into a 32-bit vector register. ENC_VOP3 default 334 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 334 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 334 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 334 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 334 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 334 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 334 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 334 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ALIGNBYTE_B32 Align a 64-bit value encoded in the first two inputs to a byte position specified in the third input, then store the result into a 32-bit vector register. ENC_VOP3 default 335 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 335 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 335 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 335 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 335 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 335 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 335 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 335 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MULLIT_F32 Multiply two floating point inputs and store the result into a vector register. Specific rules apply to accommodate lighting calculations: 0.0 * x = 0.0 and alternate INF, NAN, overflow rules apply. ENC_VOP3 default 336 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 336 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 336 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 336 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 336 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 336 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 336 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 336 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MIN3_F32 Select the minimum of three single-precision float inputs and store the selected value into a vector register. ENC_VOP3 default 337 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 337 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 337 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 337 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 337 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 337 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 337 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 337 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MIN3_I32 Select the minimum of three signed 32-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 338 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 338 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 338 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 338 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 338 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 338 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 338 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 338 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MIN3_U32 Select the minimum of three unsigned 32-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 339 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 339 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 339 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 339 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 339 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 339 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 339 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 339 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAX3_F32 Select the maximum of three single-precision float inputs and store the selected value into a vector register. ENC_VOP3 default 340 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 340 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 340 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 340 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 340 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 340 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 340 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 340 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAX3_I32 Select the maximum of three signed 32-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 341 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 341 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 341 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 341 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 341 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 341 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 341 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 341 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAX3_U32 Select the maximum of three unsigned 32-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 342 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 342 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 342 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 342 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 342 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 342 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 342 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 342 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MED3_F32 Select the median of three single-precision float values and store the selected value into a vector register. ENC_VOP3 default 343 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 343 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 343 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 343 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 343 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 343 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 343 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 343 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MED3_I32 Select the median of three signed 32-bit integer values and store the selected value into a vector register. ENC_VOP3 default 344 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 344 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 344 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 344 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 344 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 344 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 344 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 344 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MED3_U32 Select the median of three unsigned 32-bit integer values and store the selected value into a vector register. ENC_VOP3 default 345 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 345 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 345 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 345 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 345 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 345 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 345 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 345 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SAD_U8 Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3 default 346 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 346 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 346 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 346 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 346 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 346 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 346 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 346 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SAD_HI_U8 Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, shift the sum left by 16 bits, add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3 default 347 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 347 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 347 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 347 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 347 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 347 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 347 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 347 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SAD_U16 Calculate the sum of absolute differences of elements in two packed 2-component unsigned 16-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3 default 348 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 348 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 348 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 348 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 348 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 348 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 348 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 348 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SAD_U32 Calculate the absolute difference of two unsigned 32-bit integer inputs, add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3 default 349 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 349 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 349 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 349 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 349 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 349 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 349 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 349 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PK_U8_F32 Convert a single-precision float value from the first input to an unsigned 8-bit integer value and pack the result into one byte of the third input using the second input as a byte select. Store the result into a vector register. ENC_VOP3 default 350 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 350 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 350 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 350 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 350 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 350 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 350 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 350 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DIV_FIXUP_F32 Given a single-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. ENC_VOP3 default 351 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 351 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 351 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 351 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 351 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 351 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 351 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 351 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DIV_FIXUP_F64 Given a double-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. ENC_VOP3 default 352 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 352 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 352 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 352 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_2 352 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_2 352 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1_has_lit_2 352 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 352 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_F64 Add two floating point inputs and store the result into a vector register. ENC_VOP3 default 356 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 356 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 356 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 356 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_F64 Multiply two floating point inputs and store the result into a vector register. ENC_VOP3 default 357 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 357 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 357 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 357 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_MIN_F64 Select the minimum of two double-precision float inputs and store the result into a vector register. ENC_VOP3 default 358 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 358 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 358 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 358 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_MAX_F64 Select the maximum of two double-precision float inputs and store the result into a vector register. ENC_VOP3 default 359 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 359 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 359 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 359 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_LDEXP_F64 Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register. ENC_VOP3 default 360 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 360 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 360 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 360 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_LO_U32 Multiply two unsigned 32-bit integer inputs and store the result into a vector register. ENC_VOP3 default 361 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 361 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 361 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 361 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_HI_U32 Multiply two unsigned 32-bit integer inputs and store the high 32 bits of the result into a vector register. ENC_VOP3 default 362 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 362 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 362 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 362 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_HI_I32 Multiply two signed 32-bit integer inputs and store the high 32 bits of the result into a vector register. ENC_VOP3 default 364 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 364 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 364 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 364 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DIV_SCALE_F32 Given a single-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the first input for division if required to avoid subnormal terms appearing during application of the Newton-Raphson correction method. Store the scaled result into a vector register and set the vector condition code iff post-scaling is required. VOP3_SDST_ENC default 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_1 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_2 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_2 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_1_has_lit_2 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 365 VDST FMT_NUM_F32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DIV_SCALE_F64 Given a double-precision float value to scale in the first input, a denominator in the second input and a numerator in the third input, scale the first input for division if required to avoid subnormal terms appearing during application of the Newton-Raphson correction method. Store the scaled result into a vector register and set the vector condition code iff post-scaling is required. VOP3_SDST_ENC default 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_2 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_2 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1_has_lit_2 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 366 VDST FMT_NUM_F64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SDST 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_DIV_FMAS_F32 Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if the vector condition code is set. Store the result into a vector register. ENC_VOP3 default 367 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0 367 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_1 367 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 367 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_2 367 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0_has_lit_2 367 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_1_has_lit_2 367 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 367 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_VCC 64 VALU FALSE FALSE FALSE FALSE FALSE V_DIV_FMAS_F64 Multiply two double-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if the vector condition code is set. Store the result into a vector register. ENC_VOP3 default 368 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0 368 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_1 368 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 368 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC2 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_2 368 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0_has_lit_2 368 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_1_has_lit_2 368 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 368 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_VCC 64 VALU FALSE FALSE FALSE FALSE FALSE V_MSAD_U8 Calculate the sum of absolute differences of elements in two packed 4-component unsigned 8-bit integer inputs, except that elements where the second input (known as the reference input) is zero are not included in the sum. Add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3 default 369 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 369 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 369 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 369 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 369 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 369 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 369 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 369 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_QSAD_PK_U16_U8 Perform the V_SAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Truncate each result to 16 bits, pack the values into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 16-bit integers. ENC_VOP3 default 370 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 370 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 370 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 370 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_2 370 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_2 370 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1_has_lit_2 370 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 370 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_MQSAD_PK_U16_U8 Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Truncate each result to 16 bits, pack the values into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 16-bit integers. ENC_VOP3 default 371 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 371 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 371 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 371 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_2 371 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_2 371 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1_has_lit_2 371 VDST FMT_NUM_B64 OPR_VGPR 64 SRC0 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 371 VDST FMT_NUM_B64 OPR_VGPR 64 SIMM32 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_TRIG_PREOP_F64 Look up a 53-bit segment of 2/PI using an integer segment select in the second input. Scale the intermediate result by the exponent from the first double-precision float input and store the double-precision float result into a vector register. ENC_VOP3 default 372 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 372 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 372 VDST FMT_NUM_F64 OPR_VGPR 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 372 VDST FMT_NUM_F64 OPR_VGPR 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MQSAD_U32_U8 Perform the V_MSAD_U8 operation four times using different slices of the first array, all entries of the second array and each entry of the third array. Pack each 32-bit value into a 4-entry array and store the array into a vector register. The first input is an 8-entry array of unsigned 8-bit integers, the second input is a 4-entry array of unsigned 8-bit integers and the third input is a 4-entry array of unsigned 32-bit integers. ENC_VOP3 default 373 VDST FMT_NUM_B128 OPR_VGPR 128 SRC0 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VOP3_INST_LITERAL has_lit_0 373 VDST FMT_NUM_B128 OPR_VGPR 128 SIMM32 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VOP3_INST_LITERAL has_lit_1 373 VDST FMT_NUM_B128 OPR_VGPR 128 SRC0 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VOP3_INST_LITERAL has_lit_0_has_lit_1 373 VDST FMT_NUM_B128 OPR_VGPR 128 SIMM32 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VOP3_INST_LITERAL has_lit_2 373 VDST FMT_NUM_B128 OPR_VGPR 128 SRC0 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VOP3_INST_LITERAL has_lit_0_has_lit_2 373 VDST FMT_NUM_B128 OPR_VGPR 128 SIMM32 FMT_NUM_B64 OPR_SRC 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VOP3_INST_LITERAL has_lit_1_has_lit_2 373 VDST FMT_NUM_B128 OPR_VGPR 128 SRC0 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 373 VDST FMT_NUM_B128 OPR_VGPR 128 SIMM32 FMT_NUM_B64 OPR_SRC 64 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B128 OPR_SRC_VGPR 128 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_U64_U32 Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register. VOP3_SDST_ENC default 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_2 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_2 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1_has_lit_2 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 374 VDST FMT_NUM_U64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_I64_I32 Multiply two signed integer inputs, add a third signed integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register. VOP3_SDST_ENC default 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_2 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_2 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_1_has_lit_2 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 375 VDST FMT_NUM_I64 OPR_VGPR 64 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_XOR3_B32 Calculate the bitwise XOR of three vector inputs and store the result into a vector register. ENC_VOP3 default 376 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 376 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 376 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 376 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 376 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 376 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 376 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 376 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_LSHLREV_B64 Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector register. ENC_VOP3 default 767 VDST FMT_NUM_U64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 767 VDST FMT_NUM_U64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 767 VDST FMT_NUM_U64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 767 VDST FMT_NUM_U64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_LSHRREV_B64 Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector register. ENC_VOP3 default 768 VDST FMT_NUM_U64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 768 VDST FMT_NUM_U64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 768 VDST FMT_NUM_U64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 768 VDST FMT_NUM_U64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_ASHRREV_I64 Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register. ENC_VOP3 default 769 VDST FMT_NUM_I64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 769 VDST FMT_NUM_I64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 769 VDST FMT_NUM_I64 OPR_VGPR 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 769 VDST FMT_NUM_I64 OPR_VGPR 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_NC_U16 Add two unsigned 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3 default 771 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 771 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 771 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 771 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_NC_U16 Subtract the second unsigned input from the first input and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3 default 772 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 772 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 772 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 772 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MUL_LO_U16 Multiply two unsigned 16-bit integer inputs and store the low bits of the result into a vector register. ENC_VOP3 default 773 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 773 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 773 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 773 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_LSHRREV_B16 Given a shift count in the first vector input, calculate the logical shift right of the second vector input and store the result into a vector register. ENC_VOP3 default 775 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 775 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 775 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 775 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_ASHRREV_I16 Given a shift count in the first vector input, calculate the arithmetic shift right (preserving sign bit) of the second vector input and store the result into a vector register. ENC_VOP3 default 776 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 776 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 776 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 776 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MAX_U16 Select the maximum of two unsigned 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 777 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 777 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 777 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 777 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MAX_I16 Select the maximum of two signed 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 778 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 778 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 778 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 778 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MIN_U16 Select the minimum of two unsigned 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 779 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 779 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 779 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 779 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MIN_I16 Select the minimum of two signed 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 780 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 780 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 780 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 780 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_NC_I16 Add two signed 16-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3 default 781 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 781 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 781 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 781 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_NC_I16 Subtract the second signed input from the first input and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3 default 782 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 782 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 782 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 782 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_CO_U32 Add two unsigned inputs, store the result into a vector register and store the carry-out mask into a scalar register. VOP3_SDST_ENC default 783 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0 783 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_1 783 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 783 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_CO_U32 Subtract the second unsigned input from the first input, store the result into a vector register and store the carry-out mask into a scalar register. VOP3_SDST_ENC default 784 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0 784 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_1 784 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 784 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PACK_B32_F16 Pack two half-precision float values into a single 32-bit value and store the result into a vector register. ENC_VOP3 default 785 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 785 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 785 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 785 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PKNORM_I16_F16 Convert from two half-precision float inputs to a packed signed normalized short and store the result into a vector register. ENC_VOP3 default 786 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 786 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 786 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 786 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PKNORM_U16_F16 Convert from two half-precision float inputs to a packed unsigned normalized short and store the result into a vector register. ENC_VOP3 default 787 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 787 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 787 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 787 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_LSHLREV_B16 Given a shift count in the first vector input, calculate the logical shift left of the second vector input and store the result into a vector register. ENC_VOP3 default 788 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 788 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 788 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 788 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_SUBREV_CO_U32 Subtract the first unsigned input from the second input, store the result into a vector register and store the carry-out mask into a scalar register. VOP3_SDST_ENC default 793 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0 793 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_1 793 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_SDST_ENC_INST_LITERAL has_lit_0_has_lit_1 793 VDST FMT_NUM_U32 OPR_VGPR 32 SDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_U16 Multiply two unsigned 16-bit integer inputs, add an unsigned 16-bit integer value from a third input, and store the result into a vector register. ENC_VOP3 default 832 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 832 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 832 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 832 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 832 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 832 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 832 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 832 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_INTERP_P1LL_F16 Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation. ENC_VOP3 default 834 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 VOP3_INST_LITERAL has_lit_0 834 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 VOP3_INST_LITERAL has_lit_1 834 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 834 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 VOP3_INST_LITERAL has_lit_2 834 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 834 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 834 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 834 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 VALU FALSE FALSE FALSE FALSE FALSE V_INTERP_P1LV_F16 Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute specifier, load a half-precision float parameter value from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation. ENC_VOP3 default 835 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F16 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0 835 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F16 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_1 835 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F16 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 835 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F16 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_2 835 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F16 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 835 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F16 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 835 VDST FMT_NUM_F32 OPR_VGPR 32 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F16 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 835 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F16 OPR_SRC_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_PERM_B32 Permute a 64-bit value constructed from two vector inputs (most significant bits come from the first input) using a per-lane selector from the third input. The lane selector allows each byte of the result to choose from any of the 8 input bytes, perform sign extension or pad with 0/1 bits. Store the result into a vector register. ENC_VOP3 default 836 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 836 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 836 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 836 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 836 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 836 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 836 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 836 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_XAD_U32 Calculate bitwise XOR of the first two vector inputs, then add the third vector input to the intermediate result, then store the final result into a vector register. ENC_VOP3 default 837 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 837 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 837 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 837 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 837 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 837 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 837 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 837 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_LSHL_ADD_U32 Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result, then store the final result into a vector register. ENC_VOP3 default 838 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 838 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 838 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 838 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 838 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 838 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 838 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 838 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_LSHL_U32 Add the first two integer inputs, then given a shift count in the third input, calculate the logical shift left of the intermediate result, then store the final result into a vector register. ENC_VOP3 default 839 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 839 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 839 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 839 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 839 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 839 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 839 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 839 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMA_F16 Multiply two half-precision float inputs and add a third input using fused multiply add, and store the result into a vector register. ENC_VOP3 default 843 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 843 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 843 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 843 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 843 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 843 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 843 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 843 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MIN3_F16 Select the minimum of three half-precision float inputs and store the selected value into a vector register. ENC_VOP3 default 849 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 849 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 849 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 849 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 849 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 849 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 849 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 849 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MIN3_I16 Select the minimum of three signed 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 850 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 850 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 850 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 850 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 850 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 850 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 850 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 850 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MIN3_U16 Select the minimum of three unsigned 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 851 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 851 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 851 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 851 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 851 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 851 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 851 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 851 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MAX3_F16 Select the maximum of three half-precision float inputs and store the selected value into a vector register. ENC_VOP3 default 852 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 852 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 852 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 852 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 852 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 852 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 852 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 852 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MAX3_I16 Select the maximum of three signed 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 853 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 853 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 853 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 853 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 853 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 853 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 853 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 853 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MAX3_U16 Select the maximum of three unsigned 16-bit integer inputs and store the selected value into a vector register. ENC_VOP3 default 854 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 854 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 854 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 854 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 854 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 854 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 854 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 854 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MED3_F16 Select the median of three half-precision float values and store the selected value into a vector register. ENC_VOP3 default 855 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 855 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 855 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 855 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 855 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 855 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 855 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 855 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MED3_I16 Select the median of three signed 16-bit integer values and store the selected value into a vector register. ENC_VOP3 default 856 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 856 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 856 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 856 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 856 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 856 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 856 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 856 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_MED3_U16 Select the median of three unsigned 16-bit integer values and store the selected value into a vector register. ENC_VOP3 default 857 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 857 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 857 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 857 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 857 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 857 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 857 VDST FMT_NUM_U16 OPR_VGPR 16 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 857 VDST FMT_NUM_U16 OPR_VGPR 16 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_INTERP_P2_F16 Given a single-precision float J coordinate in a vector register, an attribute specifier and the result of a prior V_INTERP_P1_F32 in another vector register, load a half-precision float parameter value from the local data share, compute the second part of parameter interpolation and store the final result as a half-precision float value into a vector register. ENC_VOP3 default 858 VDST FMT_NUM_F16 OPR_VGPR 16 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F32 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0 858 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F32 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_1 858 VDST FMT_NUM_F16 OPR_VGPR 16 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F32 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 858 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SRC2 FMT_NUM_F32 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_2 858 VDST FMT_NUM_F16 OPR_VGPR 16 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 858 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SRC0 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 858 VDST FMT_NUM_F16 OPR_VGPR 16 SRC1 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 858 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_F16 OPR_ATTR 16 SIMM32 FMT_NUM_F32 OPR_SRC_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_I16 Multiply two signed 16-bit integer inputs, add a signed 16-bit integer value from a third input, and store the result into a vector register. ENC_VOP3 default 862 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 862 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 862 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 862 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 862 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 862 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 862 VDST FMT_NUM_I16 OPR_VGPR 16 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 862 VDST FMT_NUM_I16 OPR_VGPR 16 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_DIV_FIXUP_F16 Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. ENC_VOP3 default 863 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 863 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 863 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 863 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_2 863 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_2 863 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1_has_lit_2 863 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 863 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_F16 OPR_SRC 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_F16 OPR_SRC_NOLDS 16 VALU FALSE FALSE FALSE FALSE FALSE V_READLANE_B32 Read the scalar value in the specified lane of the first input where the lane select is in the second input. Store the result into a scalar register. ENC_VOP3 default 864 VDST FMT_NUM_B32 OPR_SREG 32 SRC0 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 SRC1 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VOP3_INST_LITERAL has_lit_0 864 VDST FMT_NUM_B32 OPR_SREG 32 SIMM32 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 SRC1 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VOP3_INST_LITERAL has_lit_1 864 VDST FMT_NUM_B32 OPR_SREG 32 SRC0 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 864 VDST FMT_NUM_B32 OPR_SREG 32 SIMM32 FMT_NUM_B32 OPR_VGPR_OR_LDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VALU FALSE FALSE FALSE FALSE FALSE V_WRITELANE_B32 Write the scalar value in the first input into the specified lane of a vector register where the lane select is in the second input. ENC_VOP3 default 865 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SSRC 32 SRC1 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VOP3_INST_LITERAL has_lit_0 865 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC 32 SRC1 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VOP3_INST_LITERAL has_lit_1 865 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SSRC 32 SIMM32 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 865 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC 32 SIMM32 FMT_NUM_B32 OPR_SSRC_LANESEL 32 VALU FALSE FALSE FALSE FALSE FALSE V_LDEXP_F32 Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register. ENC_VOP3 default 866 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 866 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 866 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 866 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_BFM_B32 Calculate a bitfield mask given a field offset and size and store the result into a vector register. ENC_VOP3 default 867 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 867 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 867 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 867 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_BCNT_U32_B32 Count the number of "1" bits in the vector input and store the result into a vector register. ENC_VOP3 default 868 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 868 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 868 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 868 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MBCNT_LO_U32_B32 For each lane 0 <= N < 32, examine the N least significant bits of the first input and count how many of those bits are "1". For each lane 32 <= N < 64, all "1" bits in the first input are counted. Add this count to the value in the second input and store the result into a vector register. ENC_VOP3 default 869 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 869 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 869 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 869 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MBCNT_HI_U32_B32 For each lane 32 <= N < 64, examine the N least significant bits of the first input and count how many of those bits are "1". For lane positions 0 <= N < 32 no bits are examined and the count is zero. Add this count to the value in the second input and store the result into a vector register. ENC_VOP3 default 870 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 870 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 870 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 870 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PKNORM_I16_F32 Convert from two single-precision float inputs to a packed signed normalized short and store the result into a vector register. ENC_VOP3 default 872 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 872 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 872 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 872 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PKNORM_U16_F32 Convert from two single-precision float inputs to a packed unsigned normalized short and store the result into a vector register. ENC_VOP3 default 873 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 873 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 873 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 873 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_F32 OPR_SRC 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PK_U16_U32 Convert from two unsigned 32-bit integer inputs to a packed unsigned 16-bit integer value and store the result into a vector register. ENC_VOP3 default 874 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 874 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 874 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 874 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CVT_PK_I16_I32 Convert from two signed 32-bit integer inputs to a packed signed 16-bit integer value and store the result into a vector register. ENC_VOP3 default 875 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 875 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 875 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 875 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ADD3_U32 Add three unsigned inputs and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3 default 877 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 877 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 877 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 877 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 877 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 877 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 877 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 877 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_LSHL_OR_B32 Given a shift count in the second input, calculate the logical shift left of the first input, then calculate the bitwise OR of the intermediate result and the third input, then store the final result into a vector register. ENC_VOP3 default 879 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 879 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 879 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 879 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 879 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 879 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 879 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 879 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_AND_OR_B32 Calculate bitwise AND on the first two vector inputs, then compute the bitwise OR of the intermediate result and the third vector input, then store the final result into a vector register. ENC_VOP3 default 881 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 881 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 881 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 881 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 881 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 881 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 881 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 881 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_OR3_B32 Calculate the bitwise OR of three vector inputs and store the result into a vector register. ENC_VOP3 default 882 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 882 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 882 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 882 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 882 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 882 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 882 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 882 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U32 OPR_SRC 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_U32_U16 Multiply two unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from a third input, and store the result as an unsigned 32-bit integer into a vector register. ENC_VOP3 default 883 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 883 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 883 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 883 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 883 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 883 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 883 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 883 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_U16 OPR_SRC 16 SIMM32 FMT_NUM_U16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_MAD_I32_I16 Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register. ENC_VOP3 default 885 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 885 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 885 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 885 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 885 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 885 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 885 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 885 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I16 OPR_SRC 16 SIMM32 FMT_NUM_I16 OPR_SRC_NOLDS 16 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_SUB_NC_I32 Subtract the second signed input from the first input and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3 default 886 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 886 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 886 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 886 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PERMLANE16_B32 Perform arbitrary gather-style operation within a row (16 contiguous lanes). ENC_VOP3 default 887 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 887 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 887 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 887 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 887 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 887 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 887 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 887 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PERMLANEX16_B32 Perform arbitrary gather-style operation across two rows (each row is 16 contiguous lanes). ENC_VOP3 default 888 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 888 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 888 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 888 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_2 888 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_2 888 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SRC1 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1_has_lit_2 888 VDST FMT_NUM_B32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 888 VDST FMT_NUM_B32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SSRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_ADD_NC_I32 Add two signed 32-bit integer inputs and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3 default 895 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 895 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 895 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 895 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_I32 OPR_SRC 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MAD_I16 Multiply two packed signed 16-bit integer inputs component-wise, add a packed signed 16-bit integer value from a third input component-wise, and store the result into a vector register. ENC_VOP3P default 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 0 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MUL_LO_U16 Multiply two packed unsigned 16-bit integer inputs component-wise and store the low bits of each resulting component into a vector register. ENC_VOP3P default 1 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 1 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 1 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 1 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_ADD_I16 Add two packed signed 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3P default 2 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 2 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 2 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 2 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_SUB_I16 Subtract the second packed signed 16-bit integer input from the first input component-wise and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3P default 3 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 3 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 3 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 3 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_LSHLREV_B16 Given a packed shift count in the first vector input, calculate the component-wise logical shift left of the second packed vector input and store the result into a vector register. ENC_VOP3P default 4 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 4 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 4 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 4 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_LSHRREV_B16 Given a packed shift count in the first vector input, calculate the component-wise logical shift right of the second packed vector input and store the result into a vector register. ENC_VOP3P default 5 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 5 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 5 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 5 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_ASHRREV_I16 Given a packed shift count in the first vector input, calculate the component-wise arithmetic shift right (preserving sign bit) of the second packed vector input and store the result into a vector register. ENC_VOP3P default 6 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 6 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 6 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 6 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MAX_I16 Select the component-wise maximum of two packed signed 16-bit integer inputs and store the selected values into a vector register. ENC_VOP3P default 7 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 7 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 7 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 7 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MIN_I16 Select the component-wise minimum of two packed signed 16-bit integer inputs and store the selected values into a vector register. ENC_VOP3P default 8 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 8 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 8 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 8 VDST FMT_NUM_PK_I16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MAD_U16 Multiply two packed unsigned 16-bit integer inputs component-wise, add a packed unsigned 16-bit integer value from a third input component-wise, and store the result into a vector register. ENC_VOP3P default 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 9 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_ADD_U16 Add two packed unsigned 16-bit integer inputs component-wise and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3P default 10 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 10 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 10 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 10 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_SUB_U16 Subtract the second packed unsigned 16-bit integer input from the first input component-wise and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3P default 11 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 11 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 11 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 11 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MAX_U16 Select the component-wise maximum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register. ENC_VOP3P default 12 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 12 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 12 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 12 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MIN_U16 Select the component-wise minimum of two packed unsigned 16-bit integer inputs and store the selected values into a vector register. ENC_VOP3P default 13 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 13 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 13 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 13 VDST FMT_NUM_PK_U16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_FMA_F16 Multiply two packed half-precision float inputs component-wise and add a third input component-wise using fused multiply add, and store the result into a vector register. ENC_VOP3P default 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 14 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_ADD_F16 Add two packed half-precision float inputs component-wise and store the result into a vector register. No carry-in or carry-out support. ENC_VOP3P default 15 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 15 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 15 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 15 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MUL_F16 Multiply two packed half-precision float inputs component-wise and store the result into a vector register. ENC_VOP3P default 16 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 16 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 16 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 16 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MIN_F16 Select the component-wise minimum of two packed half-precision float inputs and store the result into a vector register. ENC_VOP3P default 17 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 17 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 17 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 17 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_PK_MAX_F16 Select the component-wise maximum of two packed half-precision float inputs and store the result into a vector register. ENC_VOP3P default 18 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 18 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 18 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 18 VDST FMT_NUM_PK_F16 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT2_F32_F16 Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain, add a single-precision float value from the third input and store the result into a vector register. ENC_VOP3P default 19 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 19 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 19 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 19 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 19 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 19 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SRC1 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 19 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 19 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC 32 SIMM32 FMT_NUM_PK_F16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_F32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT2_I32_I16 Compute the dot product of two packed 2-D signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3P default 20 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 20 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 20 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 20 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 20 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 20 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SRC1 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 20 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 20 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC 32 SIMM32 FMT_NUM_PK_I16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT2_U32_U16 Compute the dot product of two packed 2-D unsigned 16-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3P default 21 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 21 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 21 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 21 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 21 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 21 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SRC1 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 21 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 21 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC 32 SIMM32 FMT_NUM_PK_U16 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT4_I32_I8 Compute the dot product of two packed 4-D signed 8-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3P default 22 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I8 OPR_SRC 32 SRC1 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 22 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC 32 SRC1 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 22 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I8 OPR_SRC 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 22 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 22 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I8 OPR_SRC 32 SRC1 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 22 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC 32 SRC1 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 22 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I8 OPR_SRC 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 22 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC 32 SIMM32 FMT_NUM_PK_I8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT4_U32_U8 Compute the dot product of two packed 4-D unsigned 8-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3P default 23 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U8 OPR_SRC 32 SRC1 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 23 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC 32 SRC1 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 23 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U8 OPR_SRC 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 23 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 23 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U8 OPR_SRC 32 SRC1 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 23 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC 32 SRC1 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 23 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U8 OPR_SRC 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 23 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC 32 SIMM32 FMT_NUM_PK_U8 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT8_I32_I4 Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3P default 24 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I4 OPR_SRC 32 SRC1 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 24 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC 32 SRC1 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 24 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I4 OPR_SRC 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 24 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 24 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I4 OPR_SRC 32 SRC1 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 24 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC 32 SRC1 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 24 VDST FMT_NUM_I32 OPR_VGPR 32 SRC0 FMT_NUM_PK_I4 OPR_SRC 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 24 VDST FMT_NUM_I32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC 32 SIMM32 FMT_NUM_PK_I4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_I32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_DOT8_U32_U4 Compute the dot product of two packed 8-D unsigned 4-bit integer inputs in the unsigned 32-bit integer domain, add an unsigned 32-bit integer value from the third input and store the result into a vector register. ENC_VOP3P default 25 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U4 OPR_SRC 32 SRC1 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 25 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC 32 SRC1 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 25 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U4 OPR_SRC 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 25 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 25 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U4 OPR_SRC 32 SRC1 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 25 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC 32 SRC1 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 25 VDST FMT_NUM_U32 OPR_VGPR 32 SRC0 FMT_NUM_PK_U4 OPR_SRC 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 25 VDST FMT_NUM_U32 OPR_VGPR 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC 32 SIMM32 FMT_NUM_PK_U4 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_U32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMA_MIX_F32 Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of 16-bit and 32-bit floating point values. Store the result into a vector register. ENC_VOP3P default 32 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 32 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 32 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 32 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 32 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 32 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 32 VDST FMT_NUM_F32 OPR_VGPR 32 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 32 VDST FMT_NUM_F32 OPR_VGPR 32 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMA_MIXLO_F16 Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of 16-bit and 32-bit floating point values. Convert the result to a half-precision float. Store the result into the low bits of a vector register. ENC_VOP3P default 33 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 33 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 33 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 33 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 33 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 33 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 33 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 33 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_FMA_MIXHI_F16 Multiply two inputs and add a third input using fused multiply add where the inputs are a mix of 16-bit and 32-bit floating point values. Convert the result to a half-precision float. Store the result into the high bits of a vector register. ENC_VOP3P default 34 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0 34 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1 34 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1 34 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SRC2 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_2 34 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_2 34 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_1_has_lit_2 34 VDST FMT_NUM_F16 OPR_VGPR 16 SRC0 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3P_INST_LITERAL has_lit_0_has_lit_1_has_lit_2 34 VDST FMT_NUM_F16 OPR_VGPR 16 SIMM32 FMT_NUM_B32 OPR_SRC 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 SIMM32 FMT_NUM_B32 OPR_SRC_NOLDS 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_F_F32 Set the vector condition code to 0. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 0 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 0 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 0 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 0 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 0 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 0 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 0 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_F32 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 1 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 1 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 1 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 1 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 1 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 1 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 1 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_F32 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 2 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 2 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 2 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 2 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 2 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 2 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 2 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_F32 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 3 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 3 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 3 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 3 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 3 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 3 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 3 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_F32 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 4 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 4 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 4 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 4 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 4 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 4 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 4 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LG_F32 Set the vector condition code to 1 iff the first input is less than or greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 5 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 5 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 5 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 5 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 5 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 5 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 5 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_F32 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 6 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 6 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 6 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 6 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 6 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 6 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 6 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_O_F32 Set the vector condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 7 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 7 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 7 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 7 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 7 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 7 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 7 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_U_F32 Set the vector condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 8 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 8 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 8 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 8 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 8 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 8 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 8 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NGE_F32 Set the vector condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 9 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 9 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 9 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 9 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 9 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 9 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 9 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLG_F32 Set the vector condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 10 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 10 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 10 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 10 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 10 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 10 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 10 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NGT_F32 Set the vector condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 11 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 11 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 11 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 11 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 11 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 11 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 11 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLE_F32 Set the vector condition code to 1 iff the first input is not less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 12 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 12 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 12 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 12 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 12 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 12 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 12 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NEQ_F32 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 13 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 13 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 13 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 13 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 13 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 13 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 13 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLT_F32 Set the vector condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 14 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 14 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 14 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 14 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 14 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 14 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 14 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_TRU_F32 Set the vector condition code to 1. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 15 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 15 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 15 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 15 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 15 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 ENC_VOPC default 15 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 15 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_F_F32 Set the vector condition code to 0. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 16 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 16 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 16 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 16 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 16 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 16 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 16 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_F32 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 17 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 17 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 17 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 17 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 17 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 17 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 17 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_F32 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 18 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 18 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 18 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 18 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 18 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 18 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 18 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_F32 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 19 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 19 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 19 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 19 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 19 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 19 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 19 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_F32 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 20 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 20 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 20 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 20 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 20 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 20 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 20 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LG_F32 Set the vector condition code to 1 iff the first input is less than or greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 21 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 21 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 21 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 21 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 21 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 21 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 21 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_F32 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 22 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 22 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 22 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 22 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 22 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 22 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 22 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_O_F32 Set the vector condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 23 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 23 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 23 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 23 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 23 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 23 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 23 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_U_F32 Set the vector condition code to 1 iff the first input is not orderable to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 24 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 24 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 24 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 24 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 24 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 24 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 24 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NGE_F32 Set the vector condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 25 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 25 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 25 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 25 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 25 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 25 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 25 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLG_F32 Set the vector condition code to 1 iff the first input is not less than or greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 26 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 26 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 26 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 26 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 26 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 26 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 26 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NGT_F32 Set the vector condition code to 1 iff the first input is not greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 27 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 27 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 27 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 27 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 27 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 27 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 27 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLE_F32 Set the vector condition code to 1 iff the first input is not less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 28 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 28 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 28 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 28 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 28 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 28 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 28 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NEQ_F32 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 29 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 29 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 29 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 29 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 29 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 29 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 29 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLT_F32 Set the vector condition code to 1 iff the first input is not less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 30 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 30 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 30 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 30 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 30 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 30 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 30 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_TRU_F32 Set the vector condition code to 1. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 31 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_F32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 31 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 31 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 31 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 31 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_F32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 31 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 31 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_F32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_F_F64 Set the vector condition code to 0. Store the result into VCC or a scalar register. ENC_VOP3 default 32 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 32 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 32 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 32 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 32 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 32 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_F64 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 33 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 33 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 33 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 33 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 33 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 33 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_F64 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 34 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 34 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 34 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 34 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 34 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 34 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_F64 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 35 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 35 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 35 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 35 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 35 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 35 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_F64 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 36 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 36 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 36 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 36 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 36 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 36 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LG_F64 Set the vector condition code to 1 iff the first input is less than or greater than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 37 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 37 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 37 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 37 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 37 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 37 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_F64 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 38 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 38 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 38 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 38 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 38 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 38 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_O_F64 Set the vector condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 39 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 39 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 39 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 39 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 39 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 39 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_U_F64 Set the vector condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 40 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 40 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 40 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 40 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 40 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 40 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NGE_F64 Set the vector condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 41 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 41 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 41 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 41 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 41 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 41 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLG_F64 Set the vector condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 42 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 42 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 42 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 42 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 42 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 42 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NGT_F64 Set the vector condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 43 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 43 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 43 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 43 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 43 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 43 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLE_F64 Set the vector condition code to 1 iff the first input is not less than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 44 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 44 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 44 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 44 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 44 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 44 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NEQ_F64 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 45 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 45 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 45 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 45 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 45 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 45 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLT_F64 Set the vector condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 46 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 46 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 46 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 46 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 46 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 46 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_TRU_F64 Set the vector condition code to 1. Store the result into VCC or a scalar register. ENC_VOP3 default 47 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 47 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 47 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 47 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 ENC_VOPC default 47 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 47 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_F_F64 Set the vector condition code to 0. Store the result into the EXEC mask. ENC_VOP3 default 48 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 48 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 48 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 48 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 48 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 48 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_F64 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. ENC_VOP3 default 49 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 49 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 49 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 49 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 49 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 49 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_F64 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 50 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 50 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 50 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 50 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 50 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 50 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_F64 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 51 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 51 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 51 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 51 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 51 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 51 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_F64 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. ENC_VOP3 default 52 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 52 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 52 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 52 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 52 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 52 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LG_F64 Set the vector condition code to 1 iff the first input is less than or greater than the second input. Store the result into the EXEC mask. ENC_VOP3 default 53 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 53 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 53 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 53 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 53 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 53 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_F64 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 54 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 54 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 54 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 54 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 54 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 54 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_O_F64 Set the vector condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask. ENC_VOP3 default 55 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 55 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 55 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 55 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 55 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 55 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_U_F64 Set the vector condition code to 1 iff the first input is not orderable to the second input. Store the result into the EXEC mask. ENC_VOP3 default 56 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 56 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 56 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 56 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 56 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 56 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NGE_F64 Set the vector condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 57 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 57 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 57 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 57 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 57 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 57 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLG_F64 Set the vector condition code to 1 iff the first input is not less than or greater than the second input. Store the result into the EXEC mask. ENC_VOP3 default 58 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 58 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 58 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 58 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 58 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 58 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NGT_F64 Set the vector condition code to 1 iff the first input is not greater than the second input. Store the result into the EXEC mask. ENC_VOP3 default 59 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 59 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 59 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 59 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 59 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 59 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLE_F64 Set the vector condition code to 1 iff the first input is not less than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 60 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 60 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 60 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 60 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 60 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 60 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NEQ_F64 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 61 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 61 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 61 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 61 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 61 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 61 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLT_F64 Set the vector condition code to 1 iff the first input is not less than the second input. Store the result into the EXEC mask. ENC_VOP3 default 62 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 62 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 62 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 62 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 62 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 62 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_TRU_F64 Set the vector condition code to 1. Store the result into the EXEC mask. ENC_VOP3 default 63 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 63 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 63 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 63 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_F64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 63 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 63 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_F64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_F_I32 Set the vector condition code to 0. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 128 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 128 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 128 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 128 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 128 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 128 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 128 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_I32 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 129 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 129 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 129 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 129 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 129 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 129 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 129 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_I32 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 130 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 130 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 130 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 130 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 130 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 130 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 130 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_I32 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 131 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 131 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 131 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 131 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 131 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 131 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 131 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_I32 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 132 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 132 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 132 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 132 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 132 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 132 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 132 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NE_I32 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 133 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 133 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 133 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 133 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 133 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 133 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 133 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_I32 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 134 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 134 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 134 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 134 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 134 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 134 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 134 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_T_I32 Set the vector condition code to 1. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 135 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 135 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 135 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 135 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 135 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 ENC_VOPC default 135 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 135 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_CLASS_F32 Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the vector condition code to the result. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 136 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_B32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 136 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 136 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 136 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 136 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 ENC_VOPC default 136 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 136 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_I16 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 137 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 137 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 137 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 137 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 137 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 ENC_VOPC default 137 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 137 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_I16 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 138 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 138 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 138 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 138 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 138 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 ENC_VOPC default 138 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 138 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_I16 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 139 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 139 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 139 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 139 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 139 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 ENC_VOPC default 139 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 139 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_I16 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 140 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 140 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 140 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 140 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 140 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 ENC_VOPC default 140 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 140 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NE_I16 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 141 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 141 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 141 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 141 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 141 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 ENC_VOPC default 141 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 141 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_I16 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 142 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 142 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 142 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 142 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 142 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 ENC_VOPC default 142 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 142 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_CLASS_F16 Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the vector condition code to the result. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 143 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 143 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 143 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 143 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 143 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 143 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 143 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_F_I32 Set the vector condition code to 0. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 144 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 144 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 144 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 144 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 144 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 144 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 144 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_I32 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 145 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 145 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 145 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 145 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 145 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 145 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 145 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_I32 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 146 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 146 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 146 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 146 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 146 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 146 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 146 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_I32 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 147 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 147 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 147 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 147 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 147 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 147 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 147 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_I32 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 148 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 148 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 148 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 148 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 148 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 148 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 148 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NE_I32 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 149 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 149 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 149 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 149 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 149 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 149 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 149 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_I32 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 150 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 150 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 150 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 150 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 150 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 150 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 150 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_T_I32 Set the vector condition code to 1. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 151 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_I32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 151 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 151 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 151 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 151 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 SRC1 FMT_NUM_I32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 151 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 151 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I32 OPR_SRC 32 VSRC1 FMT_NUM_I32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_CLASS_F32 Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a single-precision float, and set the vector condition code to the result. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 152 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_B32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 152 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 152 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 152 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 152 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 152 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 152 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F32 OPR_SRC 32 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_I16 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 153 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 153 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 153 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 153 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 153 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 153 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 153 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_I16 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 154 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 154 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 154 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 154 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 154 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 154 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 154 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_I16 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 155 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 155 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 155 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 155 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 155 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 155 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 155 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_I16 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 156 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 156 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 156 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 156 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 156 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 156 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 156 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NE_I16 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 157 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 157 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 157 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 157 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 157 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 157 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 157 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_I16 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 158 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_I16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_I16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 158 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 158 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 158 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 158 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 SRC1 FMT_NUM_I16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 158 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 158 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I16 OPR_SRC 16 VSRC1 FMT_NUM_I16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_CLASS_F16 Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a half-precision float, and set the vector condition code to the result. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 159 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 159 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 159 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 159 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 159 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 159 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 159 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_F_I64 Set the vector condition code to 0. Store the result into VCC or a scalar register. ENC_VOP3 default 160 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 160 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 160 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 160 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 160 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 160 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_I64 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 161 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 161 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 161 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 161 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 161 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 161 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_I64 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 162 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 162 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 162 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 162 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 162 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 162 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_I64 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 163 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 163 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 163 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 163 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 163 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 163 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_I64 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 164 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 164 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 164 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 164 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 164 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 164 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NE_I64 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 165 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 165 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 165 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 165 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 165 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 165 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_I64 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 166 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 166 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 166 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 166 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 166 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 166 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_T_I64 Set the vector condition code to 1. Store the result into VCC or a scalar register. ENC_VOP3 default 167 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 167 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 167 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 167 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 ENC_VOPC default 167 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 167 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_CLASS_F64 Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the vector condition code to the result. Store the result into VCC or a scalar register. ENC_VOP3 default 168 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 168 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 168 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 168 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 ENC_VOPC default 168 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_B32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 168 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_B32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_U16 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 169 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 169 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 169 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 169 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 169 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 ENC_VOPC default 169 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 169 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_U16 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 170 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 170 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 170 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 170 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 170 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 ENC_VOPC default 170 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 170 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_U16 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 171 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 171 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 171 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 171 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 171 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 ENC_VOPC default 171 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 171 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_U16 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 172 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 172 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 172 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 172 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 172 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 ENC_VOPC default 172 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 172 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NE_U16 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 173 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 173 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 173 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 173 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 173 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 ENC_VOPC default 173 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 173 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_U16 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 174 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 174 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 174 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 174 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 174 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 ENC_VOPC default 174 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 174 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_F_I64 Set the vector condition code to 0. Store the result into the EXEC mask. ENC_VOP3 default 176 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 176 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 176 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 176 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 176 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 176 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_I64 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. ENC_VOP3 default 177 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 177 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 177 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 177 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 177 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 177 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_I64 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 178 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 178 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 178 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 178 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 178 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 178 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_I64 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 179 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 179 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 179 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 179 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 179 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 179 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_I64 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. ENC_VOP3 default 180 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 180 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 180 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 180 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 180 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 180 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NE_I64 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 181 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 181 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 181 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 181 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 181 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 181 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_I64 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 182 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 182 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 182 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 182 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 182 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 182 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_T_I64 Set the vector condition code to 1. Store the result into the EXEC mask. ENC_VOP3 default 183 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 183 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 183 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 183 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_I64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 183 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 183 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_I64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_I64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_CLASS_F64 Evaluate the IEEE numeric class function specified as a 10 bit mask in the second input on the first input, a double-precision float, and set the vector condition code to the result. Store the result into the EXEC mask. ENC_VOP3 default 184 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 184 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 184 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 184 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_B32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 184 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 184 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_B32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_U16 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 185 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 185 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 185 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 185 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 185 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 185 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 185 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_U16 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 186 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 186 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 186 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 186 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 186 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 186 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 186 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_U16 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 187 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 187 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 187 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 187 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 187 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 187 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 187 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_U16 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 188 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 188 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 188 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 188 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 188 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 188 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 188 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NE_U16 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 189 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 189 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 189 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 189 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 189 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 189 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 189 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_U16 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 190 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_U16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 190 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 190 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 190 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 190 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 SRC1 FMT_NUM_U16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 190 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 190 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U16 OPR_SRC 16 VSRC1 FMT_NUM_U16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_F_U32 Set the vector condition code to 0. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 192 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 192 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 192 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 192 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 192 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 192 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 192 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_U32 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 193 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 193 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 193 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 193 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 193 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 193 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 193 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_U32 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 194 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 194 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 194 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 194 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 194 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 194 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 194 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_U32 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 195 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 195 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 195 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 195 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 195 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 195 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 195 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_U32 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 196 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 196 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 196 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 196 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 196 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 196 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 196 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NE_U32 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 197 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 197 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 197 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 197 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 197 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 197 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 197 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_U32 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 198 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 198 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 198 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 198 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 198 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 198 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 198 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_T_U32 Set the vector condition code to 1. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 199 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 ENC_VOP3 default 199 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0 199 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_1 199 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 VOP3_INST_LITERAL has_lit_0_has_lit_1 199 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 ENC_VOPC default 199 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VOPC_INST_LITERAL has_lit 199 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_F_F16 Set the vector condition code to 0. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 200 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 200 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 200 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 200 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 200 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 200 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 200 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_F16 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 201 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 201 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 201 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 201 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 201 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 201 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 201 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_F16 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 202 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 202 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 202 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 202 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 202 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 202 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 202 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_F16 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 203 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 203 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 203 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 203 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 203 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 203 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 203 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_F16 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 204 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 204 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 204 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 204 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 204 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 204 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 204 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LG_F16 Set the vector condition code to 1 iff the first input is less than or greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 205 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 205 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 205 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 205 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 205 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 205 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 205 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_F16 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 206 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 206 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 206 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 206 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 206 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 206 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 206 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_O_F16 Set the vector condition code to 1 iff the first input is orderable to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 207 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 207 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 207 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 207 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 207 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 207 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 207 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_F_U32 Set the vector condition code to 0. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 208 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 208 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 208 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 208 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 208 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 208 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 208 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_U32 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 209 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 209 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 209 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 209 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 209 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 209 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 209 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_U32 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 210 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 210 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 210 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 210 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 210 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 210 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 210 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_U32 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 211 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 211 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 211 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 211 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 211 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 211 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 211 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_U32 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 212 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 212 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 212 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 212 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 212 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 212 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 212 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NE_U32 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 213 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 213 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 213 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 213 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 213 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 213 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 213 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_U32 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 214 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 214 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 214 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 214 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 214 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 214 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 214 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_T_U32 Set the vector condition code to 1. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 215 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_U32 OPR_SRC_SIMPLE 32 VSRC1 FMT_NUM_U32 OPR_SRC_SIMPLE 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 215 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 215 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 215 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 215 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 SRC1 FMT_NUM_U32 OPR_SRC_NOLDS 32 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 215 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 215 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U32 OPR_SRC 32 VSRC1 FMT_NUM_U32 OPR_VGPR 32 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_F_F16 Set the vector condition code to 0. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 216 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 216 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 216 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 216 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 216 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 216 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 216 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_F16 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 217 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 217 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 217 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 217 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 217 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 217 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 217 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_F16 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 218 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 218 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 218 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 218 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 218 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 218 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 218 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_F16 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 219 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 219 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 219 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 219 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 219 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 219 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 219 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_F16 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 220 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 220 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 220 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 220 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 220 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 220 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 220 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LG_F16 Set the vector condition code to 1 iff the first input is less than or greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 221 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 221 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 221 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 221 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 221 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 221 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 221 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_F16 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 222 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 222 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 222 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 222 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 222 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 222 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 222 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_O_F16 Set the vector condition code to 1 iff the first input is orderable to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 223 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 223 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 223 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 223 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 223 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 223 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 223 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_F_U64 Set the vector condition code to 0. Store the result into VCC or a scalar register. ENC_VOP3 default 224 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 224 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 224 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 224 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 224 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 224 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LT_U64 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 225 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 225 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 225 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 225 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 225 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 225 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_EQ_U64 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 226 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 226 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 226 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 226 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 226 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 226 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_LE_U64 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 227 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 227 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 227 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 227 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 227 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 227 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GT_U64 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 228 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 228 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 228 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 228 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 228 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 228 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NE_U64 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 229 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 229 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 229 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 229 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 229 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 229 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_GE_U64 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into VCC or a scalar register. ENC_VOP3 default 230 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 230 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 230 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 230 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 230 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 230 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_T_U64 Set the vector condition code to 1. Store the result into VCC or a scalar register. ENC_VOP3 default 231 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0 231 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_1 231 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 231 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 ENC_VOPC default 231 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VOPC_INST_LITERAL has_lit 231 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_U_F16 Set the vector condition code to 1 iff the first input is not orderable to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 232 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 232 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 232 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 232 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 232 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 232 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 232 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NGE_F16 Set the vector condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 233 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 233 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 233 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 233 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 233 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 233 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 233 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLG_F16 Set the vector condition code to 1 iff the first input is not less than or greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 234 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 234 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 234 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 234 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 234 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 234 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 234 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NGT_F16 Set the vector condition code to 1 iff the first input is not greater than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 235 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 235 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 235 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 235 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 235 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 235 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 235 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLE_F16 Set the vector condition code to 1 iff the first input is not less than or equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 236 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 236 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 236 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 236 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 236 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 236 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 236 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NEQ_F16 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 237 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 237 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 237 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 237 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 237 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 237 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 237 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_NLT_F16 Set the vector condition code to 1 iff the first input is not less than the second input. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 238 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 238 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 238 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 238 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 238 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 238 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 238 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMP_TRU_F16 Set the vector condition code to 1. Store the result into VCC or a scalar register. VOPC_VOP_SDWA_SDST_ENC default 239 SDST FMT_NUM_M64 OPR_SREG 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 ENC_VOP3 default 239 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0 239 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_1 239 VDST FMT_NUM_M64 OPR_SREG 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 VOP3_INST_LITERAL has_lit_0_has_lit_1 239 VDST FMT_NUM_M64 OPR_SREG 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 ENC_VOPC default 239 FMT_NUM_M64 OPR_VCC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VOPC_INST_LITERAL has_lit 239 FMT_NUM_M64 OPR_VCC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_F_U64 Set the vector condition code to 0. Store the result into the EXEC mask. ENC_VOP3 default 240 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 240 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 240 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 240 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 240 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 240 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LT_U64 Set the vector condition code to 1 iff the first input is less than the second input. Store the result into the EXEC mask. ENC_VOP3 default 241 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 241 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 241 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 241 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 241 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 241 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_EQ_U64 Set the vector condition code to 1 iff the first input is equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 242 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 242 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 242 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 242 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 242 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 242 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_LE_U64 Set the vector condition code to 1 iff the first input is less than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 243 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 243 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 243 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 243 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 243 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 243 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GT_U64 Set the vector condition code to 1 iff the first input is greater than the second input. Store the result into the EXEC mask. ENC_VOP3 default 244 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 244 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 244 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 244 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 244 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 244 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NE_U64 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 245 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 245 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 245 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 245 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 245 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 245 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_GE_U64 Set the vector condition code to 1 iff the first input is greater than or equal to the second input. Store the result into the EXEC mask. ENC_VOP3 default 246 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 246 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 246 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 246 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 246 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 246 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_T_U64 Set the vector condition code to 1. Store the result into the EXEC mask. ENC_VOP3 default 247 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 247 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 247 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 247 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 SRC1 FMT_NUM_U64 OPR_SRC_NOLDS 64 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 247 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 247 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_U64 OPR_SRC_NOLDS 64 VSRC1 FMT_NUM_U64 OPR_VGPR 64 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_U_F16 Set the vector condition code to 1 iff the first input is not orderable to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 248 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 248 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 248 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 248 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 248 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 248 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 248 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NGE_F16 Set the vector condition code to 1 iff the first input is not greater than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 249 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 249 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 249 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 249 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 249 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 249 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 249 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLG_F16 Set the vector condition code to 1 iff the first input is not less than or greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 250 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 250 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 250 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 250 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 250 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 250 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 250 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NGT_F16 Set the vector condition code to 1 iff the first input is not greater than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 251 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 251 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 251 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 251 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 251 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 251 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 251 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLE_F16 Set the vector condition code to 1 iff the first input is not less than or equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 252 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 252 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 252 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 252 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 252 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 252 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 252 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NEQ_F16 Set the vector condition code to 1 iff the first input is not equal to the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 253 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 253 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 253 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 253 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 253 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 253 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 253 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_NLT_F16 Set the vector condition code to 1 iff the first input is not less than the second input. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 254 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 254 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 254 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 254 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 254 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 254 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 254 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FALSE FALSE FALSE FALSE FALSE V_CMPX_TRU_F16 Set the vector condition code to 1. Store the result into the EXEC mask. VOPC_VOP_SDWA_SDST_ENC default 255 FMT_NUM_M64 OPR_EXEC 64 VSRC0 FMT_NUM_F16 OPR_SRC_SIMPLE 16 VSRC1 FMT_NUM_F16 OPR_SRC_SIMPLE 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOP3 default 255 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0 255 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_1 255 VDST FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOP3_INST_LITERAL has_lit_0_has_lit_1 255 VDST FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 SRC1 FMT_NUM_F16 OPR_SRC_NOLDS 16 FMT_NUM_M64 OPR_SDST_EXEC 64 ENC_VOPC default 255 FMT_NUM_M64 OPR_EXEC 64 SRC0 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VOPC_INST_LITERAL has_lit 255 FMT_NUM_M64 OPR_EXEC 64 SIMM32 FMT_NUM_F16 OPR_SRC 16 VSRC1 FMT_NUM_F16 OPR_VGPR 16 FMT_NUM_M64 OPR_SDST_EXEC 64 VALU FMT_ANY Value can be anything. bits 1 1 Bits 1 0 FMT_BUF 64-bit virtual memory address. descriptor 64 1 Descriptor 64 0 FMT_IMG 256-bit image resource constant. descriptor 256 1 Descriptor 256 0 FMT_IMG_BVH 128-bit BVH resource constant. descriptor 128 1 Descriptor 128 0 FMT_NUM_B1 bits 1 1 Bits 1 0 FMT_NUM_B128 bits 128 1 Bits 128 0 FMT_NUM_B16 bits 16 1 Bits 16 0 FMT_NUM_B256 bits 256 1 Bits 256 0 FMT_NUM_B32 bits 32 1 Bits 32 0 FMT_NUM_B512 bits 512 1 Bits 512 0 FMT_NUM_B64 bits 64 1 Bits 64 0 FMT_NUM_B8 bits 8 1 Bits 8 0 FMT_NUM_B96 bits 96 1 Bits 96 0 FMT_NUM_BF16 float 16 1 Mantissa 7 0 Exponent 8 7 Sign 1 15 FMT_NUM_F16 float 16 1 Mantissa 10 0 Exponent 5 10 Sign 1 15 FMT_NUM_F32 float 32 1 Mantissa 23 0 Exponent 8 23 Sign 1 31 FMT_NUM_F64 float 64 1 Mantissa 52 0 Exponent 11 52 Sign 1 63 FMT_NUM_I16 integer 16 1 Integer 16 0 FMT_NUM_I24 integer 24 1 Integer 24 0 FMT_NUM_I32 integer 32 1 Integer 32 0 FMT_NUM_I4 integer 4 1 Integer 4 0 FMT_NUM_I64 integer 64 1 Integer 64 0 FMT_NUM_I8 integer 8 1 Integer 8 0 FMT_NUM_M64 bits 64 1 Bits 64 0 FMT_NUM_PK2_U8 integer 16 2 Integer 8 0 Integer 8 8 FMT_NUM_PK4_I8 integer 32 4 Integer 8 0 Integer 8 8 Integer 8 16 Integer 8 24 FMT_NUM_PK4_U8 integer 32 4 Integer 8 0 Integer 8 8 Integer 8 16 Integer 8 24 FMT_NUM_PK_F16 float 32 2 Mantissa 10 0 Exponent 5 10 Sign 1 15 Mantissa 10 16 Exponent 5 26 Sign 1 31 FMT_NUM_PK_I16 integer 32 2 Integer 16 0 Integer 16 16 FMT_NUM_PK_I4 integer 32 8 Integer 4 0 Integer 4 4 Integer 4 8 Integer 4 12 Integer 4 16 Integer 4 20 Integer 4 24 Integer 4 28 FMT_NUM_PK_I8 integer 32 4 Integer 8 0 Integer 8 8 Integer 8 16 Integer 8 24 FMT_NUM_PK_U16 integer 32 2 Integer 16 0 Integer 16 16 FMT_NUM_PK_U4 integer 32 8 Integer 4 0 Integer 4 4 Integer 4 8 Integer 4 12 Integer 4 16 Integer 4 20 Integer 4 24 Integer 4 28 FMT_NUM_PK_U8 integer 32 4 Integer 8 0 Integer 8 8 Integer 8 16 Integer 8 24 FMT_NUM_U16 integer 16 1 Integer 16 0 FMT_NUM_U24 integer 24 1 Integer 24 0 FMT_NUM_U32 integer 32 1 Integer 32 0 FMT_NUM_U4 integer 4 1 Integer 4 0 FMT_NUM_U64 integer 64 1 Integer 64 0 FMT_NUM_U8 integer 8 1 Integer 8 0 FMT_RSRC 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_SCALAR 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_SCRATCH 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_SCRATCH_BYTE 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_SCRATCH_STRIDE 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_TYPED 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_TYPED_BYTE 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_TYPED_STRIDE 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_VECTOR 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_VECTOR_BYTE 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_RSRC_VECTOR_STRIDE 128-bit buffer resource constant. descriptor 128 1 Descriptor 128 0 FMT_SAMP 128-bit image sampler constant. descriptor 128 1 Descriptor 128 0 OPR_ATTR attr0 First interpolation attribute. Increment from here for additional attributes. There are SQ_NUM_ATTR attributes in total. 0 attr1 <p>See above.</p> 1 attr2 <p>See above.</p> 2 attr3 <p>See above.</p> 3 attr4 <p>See above.</p> 4 attr5 <p>See above.</p> 5 attr6 <p>See above.</p> 6 attr7 <p>See above.</p> 7 attr8 <p>See above.</p> 8 attr9 <p>See above.</p> 9 attr10 <p>See above.</p> 10 attr11 <p>See above.</p> 11 attr12 <p>See above.</p> 12 attr13 <p>See above.</p> 13 attr14 <p>See above.</p> 14 attr15 <p>See above.</p> 15 attr16 <p>See above.</p> 16 attr17 <p>See above.</p> 17 attr18 <p>See above.</p> 18 attr19 <p>See above.</p> 19 attr20 <p>See above.</p> 20 attr21 <p>See above.</p> 21 attr22 <p>See above.</p> 22 attr23 <p>See above.</p> 23 attr24 <p>See above.</p> 24 attr25 <p>See above.</p> 25 attr26 <p>See above.</p> 26 attr27 <p>See above.</p> 27 attr28 <p>See above.</p> 28 attr29 <p>See above.</p> 29 attr30 <p>See above.</p> 30 attr31 <p>See above.</p> 31 attr32 <p>See above.</p> 32 OPR_DSMEM Describes an operation that reads or writes either GDS or LDS memory. dsmem I/O to DS memory 0 OPR_EXEC exec EXEC[63:0] 126 OPR_FLAT_SCRATCH Flat scratch implied register operand. flat_scratch flat_scratch[63:0] 0 OPR_HWREG Reference to a hardware register that is manipulated by getreg or setreg. This operand encodes the ID of the register to access and allows access to a subset of the full register by specifying an offset and size in bits. ID ID of hardware register to access. 6 0 hw_reg_mode 1 hw_reg_status 2 hw_reg_trapsts 3 hw_reg_hw_id_legacy 4 hw_reg_gpr_alloc 5 hw_reg_lds_alloc 6 hw_reg_ib_sts 7 hw_reg_pc_lo 8 hw_reg_pc_hi 9 hw_reg_inst_dw0 10 hw_reg_inst_dw1 11 hw_reg_ib_dbg0 12 hw_reg_ib_dbg1 13 hw_reg_flush_ib 14 hw_reg_sh_mem_bases 15 hw_reg_shader_tba_lo 16 hw_reg_shader_tba_hi 17 hw_reg_shader_tma_lo 18 hw_reg_shader_tma_hi 19 hw_reg_shader_flat_scratch_lo 20 hw_reg_shader_flat_scratch_hi 21 hw_reg_shader_xnack_mask 22 hw_reg_hw_id1 23 hw_reg_hw_id2 24 hw_reg_pops_packer 25 hw_reg_sched_mode 26 hw_reg_vgpr_offset 27 hw_reg_ib_sts2 28 OFFSET LSB offset of register bits to access. 5 6 SIZE Size of register bits to access, minus 1. Set this field to 31 to read/write all bits of the hardware register. 5 11 OPR_LABEL OPR_PARAM p10 Parameter vector representing the 'i' axis of interpolation: the value (P1 - P0) 0 p20 Parameter vector representing the 'j' axis of interpolation: the value (P2 - P0) 1 p0 Parameter vector representing the '0' of interpolation: the value P0 itself. 2 OPR_PC Program counter implied operand. pc pc[63:0] 0 OPR_SDST s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 exec_lo exec[31:0] 126 exec_hi exec[63:32] 127 OPR_SDST_EXEC exec_lo exec[31:0] 126 exec_hi exec[63:32] 127 OPR_SDST_M0 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 OPR_SENDMSG Send a message back to SPI. GSOP 2 4 gs_op_nop 0 gs_op_cut 1 gs_op_emit 2 gs_op_emit_cut 3 MSG 4 0 msg_interrupt 1 msg_gs 2 msg_gs_done 3 msg_savewave 4 msg_stall_wave_gen 5 msg_halt_waves 6 msg_ordered_ps_done 7 msg_gs_alloc_req 9 msg_get_doorbell 10 msg_get_ddid 11 msg_sysmsg 15 STREAMID 2 8 OPR_SIMM16 16-bit integer constant. VALUE Integer constant value. 16 0 OPR_SIMM32 32-bit integer constant. VALUE Integer constant value. 32 0 OPR_SIMM8 8-bit integer constant. src_simm8 0 VALUE Integer constant value. 8 0 OPR_SMEM_OFFSET s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 src_simm21 0 OPR_SRC All operands. Covers all operands that are allowed as scalar or vector sources. s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 exec_lo exec[31:0] 126 exec_hi exec[63:32] 127 0 128 1 1 (integer) 129 2 2 (integer) 130 3 3 (integer) 131 4 4 (integer) 132 5 5 (integer) 133 6 6 (integer) 134 7 7 (integer) 135 8 8 (integer) 136 9 9 (integer) 137 10 10 (integer) 138 11 11 (integer) 139 12 12 (integer) 140 13 13 (integer) 141 14 14 (integer) 142 15 15 (integer) 143 16 16 (integer) 144 17 17 (integer) 145 18 18 (integer) 146 19 19 (integer) 147 20 20 (integer) 148 21 21 (integer) 149 22 22 (integer) 150 23 23 (integer) 151 24 24 (integer) 152 25 25 (integer) 153 26 26 (integer) 154 27 27 (integer) 155 28 28 (integer) 156 29 29 (integer) 157 30 30 (integer) 158 31 31 (integer) 159 32 32 (integer) 160 33 33 (integer) 161 34 34 (integer) 162 35 35 (integer) 163 36 36 (integer) 164 37 37 (integer) 165 38 38 (integer) 166 39 39 (integer) 167 40 40 (integer) 168 41 41 (integer) 169 42 42 (integer) 170 43 43 (integer) 171 44 44 (integer) 172 45 45 (integer) 173 46 46 (integer) 174 47 47 (integer) 175 48 48 (integer) 176 49 49 (integer) 177 50 50 (integer) 178 51 51 (integer) 179 52 52 (integer) 180 53 53 (integer) 181 54 54 (integer) 182 55 55 (integer) 183 56 56 (integer) 184 57 57 (integer) 185 58 58 (integer) 186 59 59 (integer) 187 60 60 (integer) 188 61 61 (integer) 189 62 62 (integer) 190 63 63 (integer) 191 64 64 (integer) 192 -1 -1 (integer) 193 -2 -2 (integer) 194 -3 -3 (integer) 195 -4 -4 (integer) 196 -5 -5 (integer) 197 -6 -6 (integer) 198 -7 -7 (integer) 199 -8 -8 (integer) 200 -9 -9 (integer) 201 -10 -10 (integer) 202 -11 -11 (integer) 203 -12 -12 (integer) 204 -13 -13 (integer) 205 -14 -14 (integer) 206 -15 -15 (integer) 207 -16 -16 (integer) 208 0.5 0.5 240 -0.5 -0.5 241 1.0 1.0 242 -1.0 -1.0 243 2.0 2.0 244 -2.0 -2.0 245 4.0 4.0 246 -4.0 -4.0 247 0.15915494 1 / (2 * PI). 16-bit: 0x3118, 32-bit: 0x3e22f983, 64-bit: 0x3fc45f30_6dc9c882. 248 src_vccz True if vector condition code is zero. 251 src_execz True if execute mask is zero. 252 src_scc Scalar condition code. 253 src_shared_base 235 src_shared_limit 236 src_private_base 237 src_private_limit 238 src_pops_exiting_wave_id POPS counter (12b). Returns the ID of the most recent wave to complete in-order. 239 v0 Vector GPR 0. Increment from here for additional GPRs. There are NUM_VGPR VGPRs in total. Use the constant SQ_SRC_VGPR_BIT to set or clear the high order bit for vector GPRs in this operand. 256 v1 <p>See above.</p> 257 v2 <p>See above.</p> 258 v3 <p>See above.</p> 259 v4 <p>See above.</p> 260 v5 <p>See above.</p> 261 v6 <p>See above.</p> 262 v7 <p>See above.</p> 263 v8 <p>See above.</p> 264 v9 <p>See above.</p> 265 v10 <p>See above.</p> 266 v11 <p>See above.</p> 267 v12 <p>See above.</p> 268 v13 <p>See above.</p> 269 v14 <p>See above.</p> 270 v15 <p>See above.</p> 271 v16 <p>See above.</p> 272 v17 <p>See above.</p> 273 v18 <p>See above.</p> 274 v19 <p>See above.</p> 275 v20 <p>See above.</p> 276 v21 <p>See above.</p> 277 v22 <p>See above.</p> 278 v23 <p>See above.</p> 279 v24 <p>See above.</p> 280 v25 <p>See above.</p> 281 v26 <p>See above.</p> 282 v27 <p>See above.</p> 283 v28 <p>See above.</p> 284 v29 <p>See above.</p> 285 v30 <p>See above.</p> 286 v31 <p>See above.</p> 287 v32 <p>See above.</p> 288 v33 <p>See above.</p> 289 v34 <p>See above.</p> 290 v35 <p>See above.</p> 291 v36 <p>See above.</p> 292 v37 <p>See above.</p> 293 v38 <p>See above.</p> 294 v39 <p>See above.</p> 295 v40 <p>See above.</p> 296 v41 <p>See above.</p> 297 v42 <p>See above.</p> 298 v43 <p>See above.</p> 299 v44 <p>See above.</p> 300 v45 <p>See above.</p> 301 v46 <p>See above.</p> 302 v47 <p>See above.</p> 303 v48 <p>See above.</p> 304 v49 <p>See above.</p> 305 v50 <p>See above.</p> 306 v51 <p>See above.</p> 307 v52 <p>See above.</p> 308 v53 <p>See above.</p> 309 v54 <p>See above.</p> 310 v55 <p>See above.</p> 311 v56 <p>See above.</p> 312 v57 <p>See above.</p> 313 v58 <p>See above.</p> 314 v59 <p>See above.</p> 315 v60 <p>See above.</p> 316 v61 <p>See above.</p> 317 v62 <p>See above.</p> 318 v63 <p>See above.</p> 319 v64 <p>See above.</p> 320 v65 <p>See above.</p> 321 v66 <p>See above.</p> 322 v67 <p>See above.</p> 323 v68 <p>See above.</p> 324 v69 <p>See above.</p> 325 v70 <p>See above.</p> 326 v71 <p>See above.</p> 327 v72 <p>See above.</p> 328 v73 <p>See above.</p> 329 v74 <p>See above.</p> 330 v75 <p>See above.</p> 331 v76 <p>See above.</p> 332 v77 <p>See above.</p> 333 v78 <p>See above.</p> 334 v79 <p>See above.</p> 335 v80 <p>See above.</p> 336 v81 <p>See above.</p> 337 v82 <p>See above.</p> 338 v83 <p>See above.</p> 339 v84 <p>See above.</p> 340 v85 <p>See above.</p> 341 v86 <p>See above.</p> 342 v87 <p>See above.</p> 343 v88 <p>See above.</p> 344 v89 <p>See above.</p> 345 v90 <p>See above.</p> 346 v91 <p>See above.</p> 347 v92 <p>See above.</p> 348 v93 <p>See above.</p> 349 v94 <p>See above.</p> 350 v95 <p>See above.</p> 351 v96 <p>See above.</p> 352 v97 <p>See above.</p> 353 v98 <p>See above.</p> 354 v99 <p>See above.</p> 355 v100 <p>See above.</p> 356 v101 <p>See above.</p> 357 v102 <p>See above.</p> 358 v103 <p>See above.</p> 359 v104 <p>See above.</p> 360 v105 <p>See above.</p> 361 v106 <p>See above.</p> 362 v107 <p>See above.</p> 363 v108 <p>See above.</p> 364 v109 <p>See above.</p> 365 v110 <p>See above.</p> 366 v111 <p>See above.</p> 367 v112 <p>See above.</p> 368 v113 <p>See above.</p> 369 v114 <p>See above.</p> 370 v115 <p>See above.</p> 371 v116 <p>See above.</p> 372 v117 <p>See above.</p> 373 v118 <p>See above.</p> 374 v119 <p>See above.</p> 375 v120 <p>See above.</p> 376 v121 <p>See above.</p> 377 v122 <p>See above.</p> 378 v123 <p>See above.</p> 379 v124 <p>See above.</p> 380 v125 <p>See above.</p> 381 v126 <p>See above.</p> 382 v127 <p>See above.</p> 383 v128 <p>See above.</p> 384 v129 <p>See above.</p> 385 v130 <p>See above.</p> 386 v131 <p>See above.</p> 387 v132 <p>See above.</p> 388 v133 <p>See above.</p> 389 v134 <p>See above.</p> 390 v135 <p>See above.</p> 391 v136 <p>See above.</p> 392 v137 <p>See above.</p> 393 v138 <p>See above.</p> 394 v139 <p>See above.</p> 395 v140 <p>See above.</p> 396 v141 <p>See above.</p> 397 v142 <p>See above.</p> 398 v143 <p>See above.</p> 399 v144 <p>See above.</p> 400 v145 <p>See above.</p> 401 v146 <p>See above.</p> 402 v147 <p>See above.</p> 403 v148 <p>See above.</p> 404 v149 <p>See above.</p> 405 v150 <p>See above.</p> 406 v151 <p>See above.</p> 407 v152 <p>See above.</p> 408 v153 <p>See above.</p> 409 v154 <p>See above.</p> 410 v155 <p>See above.</p> 411 v156 <p>See above.</p> 412 v157 <p>See above.</p> 413 v158 <p>See above.</p> 414 v159 <p>See above.</p> 415 v160 <p>See above.</p> 416 v161 <p>See above.</p> 417 v162 <p>See above.</p> 418 v163 <p>See above.</p> 419 v164 <p>See above.</p> 420 v165 <p>See above.</p> 421 v166 <p>See above.</p> 422 v167 <p>See above.</p> 423 v168 <p>See above.</p> 424 v169 <p>See above.</p> 425 v170 <p>See above.</p> 426 v171 <p>See above.</p> 427 v172 <p>See above.</p> 428 v173 <p>See above.</p> 429 v174 <p>See above.</p> 430 v175 <p>See above.</p> 431 v176 <p>See above.</p> 432 v177 <p>See above.</p> 433 v178 <p>See above.</p> 434 v179 <p>See above.</p> 435 v180 <p>See above.</p> 436 v181 <p>See above.</p> 437 v182 <p>See above.</p> 438 v183 <p>See above.</p> 439 v184 <p>See above.</p> 440 v185 <p>See above.</p> 441 v186 <p>See above.</p> 442 v187 <p>See above.</p> 443 v188 <p>See above.</p> 444 v189 <p>See above.</p> 445 v190 <p>See above.</p> 446 v191 <p>See above.</p> 447 v192 <p>See above.</p> 448 v193 <p>See above.</p> 449 v194 <p>See above.</p> 450 v195 <p>See above.</p> 451 v196 <p>See above.</p> 452 v197 <p>See above.</p> 453 v198 <p>See above.</p> 454 v199 <p>See above.</p> 455 v200 <p>See above.</p> 456 v201 <p>See above.</p> 457 v202 <p>See above.</p> 458 v203 <p>See above.</p> 459 v204 <p>See above.</p> 460 v205 <p>See above.</p> 461 v206 <p>See above.</p> 462 v207 <p>See above.</p> 463 v208 <p>See above.</p> 464 v209 <p>See above.</p> 465 v210 <p>See above.</p> 466 v211 <p>See above.</p> 467 v212 <p>See above.</p> 468 v213 <p>See above.</p> 469 v214 <p>See above.</p> 470 v215 <p>See above.</p> 471 v216 <p>See above.</p> 472 v217 <p>See above.</p> 473 v218 <p>See above.</p> 474 v219 <p>See above.</p> 475 v220 <p>See above.</p> 476 v221 <p>See above.</p> 477 v222 <p>See above.</p> 478 v223 <p>See above.</p> 479 v224 <p>See above.</p> 480 v225 <p>See above.</p> 481 v226 <p>See above.</p> 482 v227 <p>See above.</p> 483 v228 <p>See above.</p> 484 v229 <p>See above.</p> 485 v230 <p>See above.</p> 486 v231 <p>See above.</p> 487 v232 <p>See above.</p> 488 v233 <p>See above.</p> 489 v234 <p>See above.</p> 490 v235 <p>See above.</p> 491 v236 <p>See above.</p> 492 v237 <p>See above.</p> 493 v238 <p>See above.</p> 494 v239 <p>See above.</p> 495 v240 <p>See above.</p> 496 v241 <p>See above.</p> 497 v242 <p>See above.</p> 498 v243 <p>See above.</p> 499 v244 <p>See above.</p> 500 v245 <p>See above.</p> 501 v246 <p>See above.</p> 502 v247 <p>See above.</p> 503 v248 <p>See above.</p> 504 v249 <p>See above.</p> 505 v250 <p>See above.</p> 506 v251 <p>See above.</p> 507 v252 <p>See above.</p> 508 v253 <p>See above.</p> 509 v254 <p>See above.</p> 510 v255 <p>See above.</p> 511 src_lds_direct Use LDS direct to supply a single 32-bit value to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT. See M0_FMT_LDS_DIRECT structure. Implies OPF_RDM0 when this operand is used. 254 src_literal 32-bit literal constant follows this instruction. 16-bit operands use only the 16 LSBs of this constant. 64-bit unsigned integer operands (U64, B64) zero-extend the constant. 64-bit signed integer operands (I64) sign-extend the constant. 64-bit floating-point operands use the constant as the high 32 MSBs of a double-precision floating point value (1 sign bit, 11 exponent bits and 20 mantissa bits). 255 OPR_SRC_NOLDS Simple operands, plus SRC_LITERAL. Covers all operands that are allowed as scalar or vector sources except for SRC_LDS_DIRECT. s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 exec_lo exec[31:0] 126 exec_hi exec[63:32] 127 0 128 1 1 (integer) 129 2 2 (integer) 130 3 3 (integer) 131 4 4 (integer) 132 5 5 (integer) 133 6 6 (integer) 134 7 7 (integer) 135 8 8 (integer) 136 9 9 (integer) 137 10 10 (integer) 138 11 11 (integer) 139 12 12 (integer) 140 13 13 (integer) 141 14 14 (integer) 142 15 15 (integer) 143 16 16 (integer) 144 17 17 (integer) 145 18 18 (integer) 146 19 19 (integer) 147 20 20 (integer) 148 21 21 (integer) 149 22 22 (integer) 150 23 23 (integer) 151 24 24 (integer) 152 25 25 (integer) 153 26 26 (integer) 154 27 27 (integer) 155 28 28 (integer) 156 29 29 (integer) 157 30 30 (integer) 158 31 31 (integer) 159 32 32 (integer) 160 33 33 (integer) 161 34 34 (integer) 162 35 35 (integer) 163 36 36 (integer) 164 37 37 (integer) 165 38 38 (integer) 166 39 39 (integer) 167 40 40 (integer) 168 41 41 (integer) 169 42 42 (integer) 170 43 43 (integer) 171 44 44 (integer) 172 45 45 (integer) 173 46 46 (integer) 174 47 47 (integer) 175 48 48 (integer) 176 49 49 (integer) 177 50 50 (integer) 178 51 51 (integer) 179 52 52 (integer) 180 53 53 (integer) 181 54 54 (integer) 182 55 55 (integer) 183 56 56 (integer) 184 57 57 (integer) 185 58 58 (integer) 186 59 59 (integer) 187 60 60 (integer) 188 61 61 (integer) 189 62 62 (integer) 190 63 63 (integer) 191 64 64 (integer) 192 -1 -1 (integer) 193 -2 -2 (integer) 194 -3 -3 (integer) 195 -4 -4 (integer) 196 -5 -5 (integer) 197 -6 -6 (integer) 198 -7 -7 (integer) 199 -8 -8 (integer) 200 -9 -9 (integer) 201 -10 -10 (integer) 202 -11 -11 (integer) 203 -12 -12 (integer) 204 -13 -13 (integer) 205 -14 -14 (integer) 206 -15 -15 (integer) 207 -16 -16 (integer) 208 0.5 0.5 240 -0.5 -0.5 241 1.0 1.0 242 -1.0 -1.0 243 2.0 2.0 244 -2.0 -2.0 245 4.0 4.0 246 -4.0 -4.0 247 0.15915494 1 / (2 * PI). 16-bit: 0x3118, 32-bit: 0x3e22f983, 64-bit: 0x3fc45f30_6dc9c882. 248 src_vccz True if vector condition code is zero. 251 src_execz True if execute mask is zero. 252 src_scc Scalar condition code. 253 src_shared_base 235 src_shared_limit 236 src_private_base 237 src_private_limit 238 src_pops_exiting_wave_id POPS counter (12b). Returns the ID of the most recent wave to complete in-order. 239 v0 Vector GPR 0. Increment from here for additional GPRs. There are NUM_VGPR VGPRs in total. Use the constant SQ_SRC_VGPR_BIT to set or clear the high order bit for vector GPRs in this operand. 256 v1 <p>See above.</p> 257 v2 <p>See above.</p> 258 v3 <p>See above.</p> 259 v4 <p>See above.</p> 260 v5 <p>See above.</p> 261 v6 <p>See above.</p> 262 v7 <p>See above.</p> 263 v8 <p>See above.</p> 264 v9 <p>See above.</p> 265 v10 <p>See above.</p> 266 v11 <p>See above.</p> 267 v12 <p>See above.</p> 268 v13 <p>See above.</p> 269 v14 <p>See above.</p> 270 v15 <p>See above.</p> 271 v16 <p>See above.</p> 272 v17 <p>See above.</p> 273 v18 <p>See above.</p> 274 v19 <p>See above.</p> 275 v20 <p>See above.</p> 276 v21 <p>See above.</p> 277 v22 <p>See above.</p> 278 v23 <p>See above.</p> 279 v24 <p>See above.</p> 280 v25 <p>See above.</p> 281 v26 <p>See above.</p> 282 v27 <p>See above.</p> 283 v28 <p>See above.</p> 284 v29 <p>See above.</p> 285 v30 <p>See above.</p> 286 v31 <p>See above.</p> 287 v32 <p>See above.</p> 288 v33 <p>See above.</p> 289 v34 <p>See above.</p> 290 v35 <p>See above.</p> 291 v36 <p>See above.</p> 292 v37 <p>See above.</p> 293 v38 <p>See above.</p> 294 v39 <p>See above.</p> 295 v40 <p>See above.</p> 296 v41 <p>See above.</p> 297 v42 <p>See above.</p> 298 v43 <p>See above.</p> 299 v44 <p>See above.</p> 300 v45 <p>See above.</p> 301 v46 <p>See above.</p> 302 v47 <p>See above.</p> 303 v48 <p>See above.</p> 304 v49 <p>See above.</p> 305 v50 <p>See above.</p> 306 v51 <p>See above.</p> 307 v52 <p>See above.</p> 308 v53 <p>See above.</p> 309 v54 <p>See above.</p> 310 v55 <p>See above.</p> 311 v56 <p>See above.</p> 312 v57 <p>See above.</p> 313 v58 <p>See above.</p> 314 v59 <p>See above.</p> 315 v60 <p>See above.</p> 316 v61 <p>See above.</p> 317 v62 <p>See above.</p> 318 v63 <p>See above.</p> 319 v64 <p>See above.</p> 320 v65 <p>See above.</p> 321 v66 <p>See above.</p> 322 v67 <p>See above.</p> 323 v68 <p>See above.</p> 324 v69 <p>See above.</p> 325 v70 <p>See above.</p> 326 v71 <p>See above.</p> 327 v72 <p>See above.</p> 328 v73 <p>See above.</p> 329 v74 <p>See above.</p> 330 v75 <p>See above.</p> 331 v76 <p>See above.</p> 332 v77 <p>See above.</p> 333 v78 <p>See above.</p> 334 v79 <p>See above.</p> 335 v80 <p>See above.</p> 336 v81 <p>See above.</p> 337 v82 <p>See above.</p> 338 v83 <p>See above.</p> 339 v84 <p>See above.</p> 340 v85 <p>See above.</p> 341 v86 <p>See above.</p> 342 v87 <p>See above.</p> 343 v88 <p>See above.</p> 344 v89 <p>See above.</p> 345 v90 <p>See above.</p> 346 v91 <p>See above.</p> 347 v92 <p>See above.</p> 348 v93 <p>See above.</p> 349 v94 <p>See above.</p> 350 v95 <p>See above.</p> 351 v96 <p>See above.</p> 352 v97 <p>See above.</p> 353 v98 <p>See above.</p> 354 v99 <p>See above.</p> 355 v100 <p>See above.</p> 356 v101 <p>See above.</p> 357 v102 <p>See above.</p> 358 v103 <p>See above.</p> 359 v104 <p>See above.</p> 360 v105 <p>See above.</p> 361 v106 <p>See above.</p> 362 v107 <p>See above.</p> 363 v108 <p>See above.</p> 364 v109 <p>See above.</p> 365 v110 <p>See above.</p> 366 v111 <p>See above.</p> 367 v112 <p>See above.</p> 368 v113 <p>See above.</p> 369 v114 <p>See above.</p> 370 v115 <p>See above.</p> 371 v116 <p>See above.</p> 372 v117 <p>See above.</p> 373 v118 <p>See above.</p> 374 v119 <p>See above.</p> 375 v120 <p>See above.</p> 376 v121 <p>See above.</p> 377 v122 <p>See above.</p> 378 v123 <p>See above.</p> 379 v124 <p>See above.</p> 380 v125 <p>See above.</p> 381 v126 <p>See above.</p> 382 v127 <p>See above.</p> 383 v128 <p>See above.</p> 384 v129 <p>See above.</p> 385 v130 <p>See above.</p> 386 v131 <p>See above.</p> 387 v132 <p>See above.</p> 388 v133 <p>See above.</p> 389 v134 <p>See above.</p> 390 v135 <p>See above.</p> 391 v136 <p>See above.</p> 392 v137 <p>See above.</p> 393 v138 <p>See above.</p> 394 v139 <p>See above.</p> 395 v140 <p>See above.</p> 396 v141 <p>See above.</p> 397 v142 <p>See above.</p> 398 v143 <p>See above.</p> 399 v144 <p>See above.</p> 400 v145 <p>See above.</p> 401 v146 <p>See above.</p> 402 v147 <p>See above.</p> 403 v148 <p>See above.</p> 404 v149 <p>See above.</p> 405 v150 <p>See above.</p> 406 v151 <p>See above.</p> 407 v152 <p>See above.</p> 408 v153 <p>See above.</p> 409 v154 <p>See above.</p> 410 v155 <p>See above.</p> 411 v156 <p>See above.</p> 412 v157 <p>See above.</p> 413 v158 <p>See above.</p> 414 v159 <p>See above.</p> 415 v160 <p>See above.</p> 416 v161 <p>See above.</p> 417 v162 <p>See above.</p> 418 v163 <p>See above.</p> 419 v164 <p>See above.</p> 420 v165 <p>See above.</p> 421 v166 <p>See above.</p> 422 v167 <p>See above.</p> 423 v168 <p>See above.</p> 424 v169 <p>See above.</p> 425 v170 <p>See above.</p> 426 v171 <p>See above.</p> 427 v172 <p>See above.</p> 428 v173 <p>See above.</p> 429 v174 <p>See above.</p> 430 v175 <p>See above.</p> 431 v176 <p>See above.</p> 432 v177 <p>See above.</p> 433 v178 <p>See above.</p> 434 v179 <p>See above.</p> 435 v180 <p>See above.</p> 436 v181 <p>See above.</p> 437 v182 <p>See above.</p> 438 v183 <p>See above.</p> 439 v184 <p>See above.</p> 440 v185 <p>See above.</p> 441 v186 <p>See above.</p> 442 v187 <p>See above.</p> 443 v188 <p>See above.</p> 444 v189 <p>See above.</p> 445 v190 <p>See above.</p> 446 v191 <p>See above.</p> 447 v192 <p>See above.</p> 448 v193 <p>See above.</p> 449 v194 <p>See above.</p> 450 v195 <p>See above.</p> 451 v196 <p>See above.</p> 452 v197 <p>See above.</p> 453 v198 <p>See above.</p> 454 v199 <p>See above.</p> 455 v200 <p>See above.</p> 456 v201 <p>See above.</p> 457 v202 <p>See above.</p> 458 v203 <p>See above.</p> 459 v204 <p>See above.</p> 460 v205 <p>See above.</p> 461 v206 <p>See above.</p> 462 v207 <p>See above.</p> 463 v208 <p>See above.</p> 464 v209 <p>See above.</p> 465 v210 <p>See above.</p> 466 v211 <p>See above.</p> 467 v212 <p>See above.</p> 468 v213 <p>See above.</p> 469 v214 <p>See above.</p> 470 v215 <p>See above.</p> 471 v216 <p>See above.</p> 472 v217 <p>See above.</p> 473 v218 <p>See above.</p> 474 v219 <p>See above.</p> 475 v220 <p>See above.</p> 476 v221 <p>See above.</p> 477 v222 <p>See above.</p> 478 v223 <p>See above.</p> 479 v224 <p>See above.</p> 480 v225 <p>See above.</p> 481 v226 <p>See above.</p> 482 v227 <p>See above.</p> 483 v228 <p>See above.</p> 484 v229 <p>See above.</p> 485 v230 <p>See above.</p> 486 v231 <p>See above.</p> 487 v232 <p>See above.</p> 488 v233 <p>See above.</p> 489 v234 <p>See above.</p> 490 v235 <p>See above.</p> 491 v236 <p>See above.</p> 492 v237 <p>See above.</p> 493 v238 <p>See above.</p> 494 v239 <p>See above.</p> 495 v240 <p>See above.</p> 496 v241 <p>See above.</p> 497 v242 <p>See above.</p> 498 v243 <p>See above.</p> 499 v244 <p>See above.</p> 500 v245 <p>See above.</p> 501 v246 <p>See above.</p> 502 v247 <p>See above.</p> 503 v248 <p>See above.</p> 504 v249 <p>See above.</p> 505 v250 <p>See above.</p> 506 v251 <p>See above.</p> 507 v252 <p>See above.</p> 508 v253 <p>See above.</p> 509 v254 <p>See above.</p> 510 v255 <p>See above.</p> 511 src_literal 32-bit literal constant follows this instruction. 16-bit operands use only the 16 LSBs of this constant. 64-bit unsigned integer operands (U64, B64) zero-extend the constant. 64-bit signed integer operands (I64) sign-extend the constant. 64-bit floating-point operands use the constant as the high 32 MSBs of a double-precision floating point value (1 sign bit, 11 exponent bits and 20 mantissa bits). 255 OPR_SRC_SIMPLE Simple operands. Covers all operands that are allowed as scalar or vector sources except for SRC_LDS_DIRECT and SRC_LITERAL. s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 exec_lo exec[31:0] 126 exec_hi exec[63:32] 127 0 128 1 1 (integer) 129 2 2 (integer) 130 3 3 (integer) 131 4 4 (integer) 132 5 5 (integer) 133 6 6 (integer) 134 7 7 (integer) 135 8 8 (integer) 136 9 9 (integer) 137 10 10 (integer) 138 11 11 (integer) 139 12 12 (integer) 140 13 13 (integer) 141 14 14 (integer) 142 15 15 (integer) 143 16 16 (integer) 144 17 17 (integer) 145 18 18 (integer) 146 19 19 (integer) 147 20 20 (integer) 148 21 21 (integer) 149 22 22 (integer) 150 23 23 (integer) 151 24 24 (integer) 152 25 25 (integer) 153 26 26 (integer) 154 27 27 (integer) 155 28 28 (integer) 156 29 29 (integer) 157 30 30 (integer) 158 31 31 (integer) 159 32 32 (integer) 160 33 33 (integer) 161 34 34 (integer) 162 35 35 (integer) 163 36 36 (integer) 164 37 37 (integer) 165 38 38 (integer) 166 39 39 (integer) 167 40 40 (integer) 168 41 41 (integer) 169 42 42 (integer) 170 43 43 (integer) 171 44 44 (integer) 172 45 45 (integer) 173 46 46 (integer) 174 47 47 (integer) 175 48 48 (integer) 176 49 49 (integer) 177 50 50 (integer) 178 51 51 (integer) 179 52 52 (integer) 180 53 53 (integer) 181 54 54 (integer) 182 55 55 (integer) 183 56 56 (integer) 184 57 57 (integer) 185 58 58 (integer) 186 59 59 (integer) 187 60 60 (integer) 188 61 61 (integer) 189 62 62 (integer) 190 63 63 (integer) 191 64 64 (integer) 192 -1 -1 (integer) 193 -2 -2 (integer) 194 -3 -3 (integer) 195 -4 -4 (integer) 196 -5 -5 (integer) 197 -6 -6 (integer) 198 -7 -7 (integer) 199 -8 -8 (integer) 200 -9 -9 (integer) 201 -10 -10 (integer) 202 -11 -11 (integer) 203 -12 -12 (integer) 204 -13 -13 (integer) 205 -14 -14 (integer) 206 -15 -15 (integer) 207 -16 -16 (integer) 208 0.5 0.5 240 -0.5 -0.5 241 1.0 1.0 242 -1.0 -1.0 243 2.0 2.0 244 -2.0 -2.0 245 4.0 4.0 246 -4.0 -4.0 247 0.15915494 1 / (2 * PI). 16-bit: 0x3118, 32-bit: 0x3e22f983, 64-bit: 0x3fc45f30_6dc9c882. 248 src_vccz True if vector condition code is zero. 251 src_execz True if execute mask is zero. 252 src_scc Scalar condition code. 253 src_shared_base 235 src_shared_limit 236 src_private_base 237 src_private_limit 238 src_pops_exiting_wave_id POPS counter (12b). Returns the ID of the most recent wave to complete in-order. 239 v0 Vector GPR 0. Increment from here for additional GPRs. There are NUM_VGPR VGPRs in total. Use the constant SQ_SRC_VGPR_BIT to set or clear the high order bit for vector GPRs in this operand. 256 v1 <p>See above.</p> 257 v2 <p>See above.</p> 258 v3 <p>See above.</p> 259 v4 <p>See above.</p> 260 v5 <p>See above.</p> 261 v6 <p>See above.</p> 262 v7 <p>See above.</p> 263 v8 <p>See above.</p> 264 v9 <p>See above.</p> 265 v10 <p>See above.</p> 266 v11 <p>See above.</p> 267 v12 <p>See above.</p> 268 v13 <p>See above.</p> 269 v14 <p>See above.</p> 270 v15 <p>See above.</p> 271 v16 <p>See above.</p> 272 v17 <p>See above.</p> 273 v18 <p>See above.</p> 274 v19 <p>See above.</p> 275 v20 <p>See above.</p> 276 v21 <p>See above.</p> 277 v22 <p>See above.</p> 278 v23 <p>See above.</p> 279 v24 <p>See above.</p> 280 v25 <p>See above.</p> 281 v26 <p>See above.</p> 282 v27 <p>See above.</p> 283 v28 <p>See above.</p> 284 v29 <p>See above.</p> 285 v30 <p>See above.</p> 286 v31 <p>See above.</p> 287 v32 <p>See above.</p> 288 v33 <p>See above.</p> 289 v34 <p>See above.</p> 290 v35 <p>See above.</p> 291 v36 <p>See above.</p> 292 v37 <p>See above.</p> 293 v38 <p>See above.</p> 294 v39 <p>See above.</p> 295 v40 <p>See above.</p> 296 v41 <p>See above.</p> 297 v42 <p>See above.</p> 298 v43 <p>See above.</p> 299 v44 <p>See above.</p> 300 v45 <p>See above.</p> 301 v46 <p>See above.</p> 302 v47 <p>See above.</p> 303 v48 <p>See above.</p> 304 v49 <p>See above.</p> 305 v50 <p>See above.</p> 306 v51 <p>See above.</p> 307 v52 <p>See above.</p> 308 v53 <p>See above.</p> 309 v54 <p>See above.</p> 310 v55 <p>See above.</p> 311 v56 <p>See above.</p> 312 v57 <p>See above.</p> 313 v58 <p>See above.</p> 314 v59 <p>See above.</p> 315 v60 <p>See above.</p> 316 v61 <p>See above.</p> 317 v62 <p>See above.</p> 318 v63 <p>See above.</p> 319 v64 <p>See above.</p> 320 v65 <p>See above.</p> 321 v66 <p>See above.</p> 322 v67 <p>See above.</p> 323 v68 <p>See above.</p> 324 v69 <p>See above.</p> 325 v70 <p>See above.</p> 326 v71 <p>See above.</p> 327 v72 <p>See above.</p> 328 v73 <p>See above.</p> 329 v74 <p>See above.</p> 330 v75 <p>See above.</p> 331 v76 <p>See above.</p> 332 v77 <p>See above.</p> 333 v78 <p>See above.</p> 334 v79 <p>See above.</p> 335 v80 <p>See above.</p> 336 v81 <p>See above.</p> 337 v82 <p>See above.</p> 338 v83 <p>See above.</p> 339 v84 <p>See above.</p> 340 v85 <p>See above.</p> 341 v86 <p>See above.</p> 342 v87 <p>See above.</p> 343 v88 <p>See above.</p> 344 v89 <p>See above.</p> 345 v90 <p>See above.</p> 346 v91 <p>See above.</p> 347 v92 <p>See above.</p> 348 v93 <p>See above.</p> 349 v94 <p>See above.</p> 350 v95 <p>See above.</p> 351 v96 <p>See above.</p> 352 v97 <p>See above.</p> 353 v98 <p>See above.</p> 354 v99 <p>See above.</p> 355 v100 <p>See above.</p> 356 v101 <p>See above.</p> 357 v102 <p>See above.</p> 358 v103 <p>See above.</p> 359 v104 <p>See above.</p> 360 v105 <p>See above.</p> 361 v106 <p>See above.</p> 362 v107 <p>See above.</p> 363 v108 <p>See above.</p> 364 v109 <p>See above.</p> 365 v110 <p>See above.</p> 366 v111 <p>See above.</p> 367 v112 <p>See above.</p> 368 v113 <p>See above.</p> 369 v114 <p>See above.</p> 370 v115 <p>See above.</p> 371 v116 <p>See above.</p> 372 v117 <p>See above.</p> 373 v118 <p>See above.</p> 374 v119 <p>See above.</p> 375 v120 <p>See above.</p> 376 v121 <p>See above.</p> 377 v122 <p>See above.</p> 378 v123 <p>See above.</p> 379 v124 <p>See above.</p> 380 v125 <p>See above.</p> 381 v126 <p>See above.</p> 382 v127 <p>See above.</p> 383 v128 <p>See above.</p> 384 v129 <p>See above.</p> 385 v130 <p>See above.</p> 386 v131 <p>See above.</p> 387 v132 <p>See above.</p> 388 v133 <p>See above.</p> 389 v134 <p>See above.</p> 390 v135 <p>See above.</p> 391 v136 <p>See above.</p> 392 v137 <p>See above.</p> 393 v138 <p>See above.</p> 394 v139 <p>See above.</p> 395 v140 <p>See above.</p> 396 v141 <p>See above.</p> 397 v142 <p>See above.</p> 398 v143 <p>See above.</p> 399 v144 <p>See above.</p> 400 v145 <p>See above.</p> 401 v146 <p>See above.</p> 402 v147 <p>See above.</p> 403 v148 <p>See above.</p> 404 v149 <p>See above.</p> 405 v150 <p>See above.</p> 406 v151 <p>See above.</p> 407 v152 <p>See above.</p> 408 v153 <p>See above.</p> 409 v154 <p>See above.</p> 410 v155 <p>See above.</p> 411 v156 <p>See above.</p> 412 v157 <p>See above.</p> 413 v158 <p>See above.</p> 414 v159 <p>See above.</p> 415 v160 <p>See above.</p> 416 v161 <p>See above.</p> 417 v162 <p>See above.</p> 418 v163 <p>See above.</p> 419 v164 <p>See above.</p> 420 v165 <p>See above.</p> 421 v166 <p>See above.</p> 422 v167 <p>See above.</p> 423 v168 <p>See above.</p> 424 v169 <p>See above.</p> 425 v170 <p>See above.</p> 426 v171 <p>See above.</p> 427 v172 <p>See above.</p> 428 v173 <p>See above.</p> 429 v174 <p>See above.</p> 430 v175 <p>See above.</p> 431 v176 <p>See above.</p> 432 v177 <p>See above.</p> 433 v178 <p>See above.</p> 434 v179 <p>See above.</p> 435 v180 <p>See above.</p> 436 v181 <p>See above.</p> 437 v182 <p>See above.</p> 438 v183 <p>See above.</p> 439 v184 <p>See above.</p> 440 v185 <p>See above.</p> 441 v186 <p>See above.</p> 442 v187 <p>See above.</p> 443 v188 <p>See above.</p> 444 v189 <p>See above.</p> 445 v190 <p>See above.</p> 446 v191 <p>See above.</p> 447 v192 <p>See above.</p> 448 v193 <p>See above.</p> 449 v194 <p>See above.</p> 450 v195 <p>See above.</p> 451 v196 <p>See above.</p> 452 v197 <p>See above.</p> 453 v198 <p>See above.</p> 454 v199 <p>See above.</p> 455 v200 <p>See above.</p> 456 v201 <p>See above.</p> 457 v202 <p>See above.</p> 458 v203 <p>See above.</p> 459 v204 <p>See above.</p> 460 v205 <p>See above.</p> 461 v206 <p>See above.</p> 462 v207 <p>See above.</p> 463 v208 <p>See above.</p> 464 v209 <p>See above.</p> 465 v210 <p>See above.</p> 466 v211 <p>See above.</p> 467 v212 <p>See above.</p> 468 v213 <p>See above.</p> 469 v214 <p>See above.</p> 470 v215 <p>See above.</p> 471 v216 <p>See above.</p> 472 v217 <p>See above.</p> 473 v218 <p>See above.</p> 474 v219 <p>See above.</p> 475 v220 <p>See above.</p> 476 v221 <p>See above.</p> 477 v222 <p>See above.</p> 478 v223 <p>See above.</p> 479 v224 <p>See above.</p> 480 v225 <p>See above.</p> 481 v226 <p>See above.</p> 482 v227 <p>See above.</p> 483 v228 <p>See above.</p> 484 v229 <p>See above.</p> 485 v230 <p>See above.</p> 486 v231 <p>See above.</p> 487 v232 <p>See above.</p> 488 v233 <p>See above.</p> 489 v234 <p>See above.</p> 490 v235 <p>See above.</p> 491 v236 <p>See above.</p> 492 v237 <p>See above.</p> 493 v238 <p>See above.</p> 494 v239 <p>See above.</p> 495 v240 <p>See above.</p> 496 v241 <p>See above.</p> 497 v242 <p>See above.</p> 498 v243 <p>See above.</p> 499 v244 <p>See above.</p> 500 v245 <p>See above.</p> 501 v246 <p>See above.</p> 502 v247 <p>See above.</p> 503 v248 <p>See above.</p> 504 v249 <p>See above.</p> 505 v250 <p>See above.</p> 506 v251 <p>See above.</p> 507 v252 <p>See above.</p> 508 v253 <p>See above.</p> 509 v254 <p>See above.</p> 510 v255 <p>See above.</p> 511 OPR_SRC_VGPR Operand must be a vector GPR. Uses a 9-bit operand field. v0 Vector GPR 0. Increment from here for additional GPRs. There are NUM_VGPR VGPRs in total. Use the constant SQ_SRC_VGPR_BIT to set or clear the high order bit for vector GPRs in this operand. 256 v1 <p>See above.</p> 257 v2 <p>See above.</p> 258 v3 <p>See above.</p> 259 v4 <p>See above.</p> 260 v5 <p>See above.</p> 261 v6 <p>See above.</p> 262 v7 <p>See above.</p> 263 v8 <p>See above.</p> 264 v9 <p>See above.</p> 265 v10 <p>See above.</p> 266 v11 <p>See above.</p> 267 v12 <p>See above.</p> 268 v13 <p>See above.</p> 269 v14 <p>See above.</p> 270 v15 <p>See above.</p> 271 v16 <p>See above.</p> 272 v17 <p>See above.</p> 273 v18 <p>See above.</p> 274 v19 <p>See above.</p> 275 v20 <p>See above.</p> 276 v21 <p>See above.</p> 277 v22 <p>See above.</p> 278 v23 <p>See above.</p> 279 v24 <p>See above.</p> 280 v25 <p>See above.</p> 281 v26 <p>See above.</p> 282 v27 <p>See above.</p> 283 v28 <p>See above.</p> 284 v29 <p>See above.</p> 285 v30 <p>See above.</p> 286 v31 <p>See above.</p> 287 v32 <p>See above.</p> 288 v33 <p>See above.</p> 289 v34 <p>See above.</p> 290 v35 <p>See above.</p> 291 v36 <p>See above.</p> 292 v37 <p>See above.</p> 293 v38 <p>See above.</p> 294 v39 <p>See above.</p> 295 v40 <p>See above.</p> 296 v41 <p>See above.</p> 297 v42 <p>See above.</p> 298 v43 <p>See above.</p> 299 v44 <p>See above.</p> 300 v45 <p>See above.</p> 301 v46 <p>See above.</p> 302 v47 <p>See above.</p> 303 v48 <p>See above.</p> 304 v49 <p>See above.</p> 305 v50 <p>See above.</p> 306 v51 <p>See above.</p> 307 v52 <p>See above.</p> 308 v53 <p>See above.</p> 309 v54 <p>See above.</p> 310 v55 <p>See above.</p> 311 v56 <p>See above.</p> 312 v57 <p>See above.</p> 313 v58 <p>See above.</p> 314 v59 <p>See above.</p> 315 v60 <p>See above.</p> 316 v61 <p>See above.</p> 317 v62 <p>See above.</p> 318 v63 <p>See above.</p> 319 v64 <p>See above.</p> 320 v65 <p>See above.</p> 321 v66 <p>See above.</p> 322 v67 <p>See above.</p> 323 v68 <p>See above.</p> 324 v69 <p>See above.</p> 325 v70 <p>See above.</p> 326 v71 <p>See above.</p> 327 v72 <p>See above.</p> 328 v73 <p>See above.</p> 329 v74 <p>See above.</p> 330 v75 <p>See above.</p> 331 v76 <p>See above.</p> 332 v77 <p>See above.</p> 333 v78 <p>See above.</p> 334 v79 <p>See above.</p> 335 v80 <p>See above.</p> 336 v81 <p>See above.</p> 337 v82 <p>See above.</p> 338 v83 <p>See above.</p> 339 v84 <p>See above.</p> 340 v85 <p>See above.</p> 341 v86 <p>See above.</p> 342 v87 <p>See above.</p> 343 v88 <p>See above.</p> 344 v89 <p>See above.</p> 345 v90 <p>See above.</p> 346 v91 <p>See above.</p> 347 v92 <p>See above.</p> 348 v93 <p>See above.</p> 349 v94 <p>See above.</p> 350 v95 <p>See above.</p> 351 v96 <p>See above.</p> 352 v97 <p>See above.</p> 353 v98 <p>See above.</p> 354 v99 <p>See above.</p> 355 v100 <p>See above.</p> 356 v101 <p>See above.</p> 357 v102 <p>See above.</p> 358 v103 <p>See above.</p> 359 v104 <p>See above.</p> 360 v105 <p>See above.</p> 361 v106 <p>See above.</p> 362 v107 <p>See above.</p> 363 v108 <p>See above.</p> 364 v109 <p>See above.</p> 365 v110 <p>See above.</p> 366 v111 <p>See above.</p> 367 v112 <p>See above.</p> 368 v113 <p>See above.</p> 369 v114 <p>See above.</p> 370 v115 <p>See above.</p> 371 v116 <p>See above.</p> 372 v117 <p>See above.</p> 373 v118 <p>See above.</p> 374 v119 <p>See above.</p> 375 v120 <p>See above.</p> 376 v121 <p>See above.</p> 377 v122 <p>See above.</p> 378 v123 <p>See above.</p> 379 v124 <p>See above.</p> 380 v125 <p>See above.</p> 381 v126 <p>See above.</p> 382 v127 <p>See above.</p> 383 v128 <p>See above.</p> 384 v129 <p>See above.</p> 385 v130 <p>See above.</p> 386 v131 <p>See above.</p> 387 v132 <p>See above.</p> 388 v133 <p>See above.</p> 389 v134 <p>See above.</p> 390 v135 <p>See above.</p> 391 v136 <p>See above.</p> 392 v137 <p>See above.</p> 393 v138 <p>See above.</p> 394 v139 <p>See above.</p> 395 v140 <p>See above.</p> 396 v141 <p>See above.</p> 397 v142 <p>See above.</p> 398 v143 <p>See above.</p> 399 v144 <p>See above.</p> 400 v145 <p>See above.</p> 401 v146 <p>See above.</p> 402 v147 <p>See above.</p> 403 v148 <p>See above.</p> 404 v149 <p>See above.</p> 405 v150 <p>See above.</p> 406 v151 <p>See above.</p> 407 v152 <p>See above.</p> 408 v153 <p>See above.</p> 409 v154 <p>See above.</p> 410 v155 <p>See above.</p> 411 v156 <p>See above.</p> 412 v157 <p>See above.</p> 413 v158 <p>See above.</p> 414 v159 <p>See above.</p> 415 v160 <p>See above.</p> 416 v161 <p>See above.</p> 417 v162 <p>See above.</p> 418 v163 <p>See above.</p> 419 v164 <p>See above.</p> 420 v165 <p>See above.</p> 421 v166 <p>See above.</p> 422 v167 <p>See above.</p> 423 v168 <p>See above.</p> 424 v169 <p>See above.</p> 425 v170 <p>See above.</p> 426 v171 <p>See above.</p> 427 v172 <p>See above.</p> 428 v173 <p>See above.</p> 429 v174 <p>See above.</p> 430 v175 <p>See above.</p> 431 v176 <p>See above.</p> 432 v177 <p>See above.</p> 433 v178 <p>See above.</p> 434 v179 <p>See above.</p> 435 v180 <p>See above.</p> 436 v181 <p>See above.</p> 437 v182 <p>See above.</p> 438 v183 <p>See above.</p> 439 v184 <p>See above.</p> 440 v185 <p>See above.</p> 441 v186 <p>See above.</p> 442 v187 <p>See above.</p> 443 v188 <p>See above.</p> 444 v189 <p>See above.</p> 445 v190 <p>See above.</p> 446 v191 <p>See above.</p> 447 v192 <p>See above.</p> 448 v193 <p>See above.</p> 449 v194 <p>See above.</p> 450 v195 <p>See above.</p> 451 v196 <p>See above.</p> 452 v197 <p>See above.</p> 453 v198 <p>See above.</p> 454 v199 <p>See above.</p> 455 v200 <p>See above.</p> 456 v201 <p>See above.</p> 457 v202 <p>See above.</p> 458 v203 <p>See above.</p> 459 v204 <p>See above.</p> 460 v205 <p>See above.</p> 461 v206 <p>See above.</p> 462 v207 <p>See above.</p> 463 v208 <p>See above.</p> 464 v209 <p>See above.</p> 465 v210 <p>See above.</p> 466 v211 <p>See above.</p> 467 v212 <p>See above.</p> 468 v213 <p>See above.</p> 469 v214 <p>See above.</p> 470 v215 <p>See above.</p> 471 v216 <p>See above.</p> 472 v217 <p>See above.</p> 473 v218 <p>See above.</p> 474 v219 <p>See above.</p> 475 v220 <p>See above.</p> 476 v221 <p>See above.</p> 477 v222 <p>See above.</p> 478 v223 <p>See above.</p> 479 v224 <p>See above.</p> 480 v225 <p>See above.</p> 481 v226 <p>See above.</p> 482 v227 <p>See above.</p> 483 v228 <p>See above.</p> 484 v229 <p>See above.</p> 485 v230 <p>See above.</p> 486 v231 <p>See above.</p> 487 v232 <p>See above.</p> 488 v233 <p>See above.</p> 489 v234 <p>See above.</p> 490 v235 <p>See above.</p> 491 v236 <p>See above.</p> 492 v237 <p>See above.</p> 493 v238 <p>See above.</p> 494 v239 <p>See above.</p> 495 v240 <p>See above.</p> 496 v241 <p>See above.</p> 497 v242 <p>See above.</p> 498 v243 <p>See above.</p> 499 v244 <p>See above.</p> 500 v245 <p>See above.</p> 501 v246 <p>See above.</p> 502 v247 <p>See above.</p> 503 v248 <p>See above.</p> 504 v249 <p>See above.</p> 505 v250 <p>See above.</p> 506 v251 <p>See above.</p> 507 v252 <p>See above.</p> 508 v253 <p>See above.</p> 509 v254 <p>See above.</p> 510 v255 <p>See above.</p> 511 OPR_SREG s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 OPR_SREG_M0_INL s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 0 128 1 1 (integer) 129 2 2 (integer) 130 3 3 (integer) 131 4 4 (integer) 132 5 5 (integer) 133 6 6 (integer) 134 7 7 (integer) 135 8 8 (integer) 136 9 9 (integer) 137 10 10 (integer) 138 11 11 (integer) 139 12 12 (integer) 140 13 13 (integer) 141 14 14 (integer) 142 15 15 (integer) 143 16 16 (integer) 144 17 17 (integer) 145 18 18 (integer) 146 19 19 (integer) 147 20 20 (integer) 148 21 21 (integer) 149 22 22 (integer) 150 23 23 (integer) 151 24 24 (integer) 152 25 25 (integer) 153 26 26 (integer) 154 27 27 (integer) 155 28 28 (integer) 156 29 29 (integer) 157 30 30 (integer) 158 31 31 (integer) 159 32 32 (integer) 160 33 33 (integer) 161 34 34 (integer) 162 35 35 (integer) 163 36 36 (integer) 164 37 37 (integer) 165 38 38 (integer) 166 39 39 (integer) 167 40 40 (integer) 168 41 41 (integer) 169 42 42 (integer) 170 43 43 (integer) 171 44 44 (integer) 172 45 45 (integer) 173 46 46 (integer) 174 47 47 (integer) 175 48 48 (integer) 176 49 49 (integer) 177 50 50 (integer) 178 51 51 (integer) 179 52 52 (integer) 180 53 53 (integer) 181 54 54 (integer) 182 55 55 (integer) 183 56 56 (integer) 184 57 57 (integer) 185 58 58 (integer) 186 59 59 (integer) 187 60 60 (integer) 188 61 61 (integer) 189 62 62 (integer) 190 63 63 (integer) 191 64 64 (integer) 192 -1 -1 (integer) 193 -2 -2 (integer) 194 -3 -3 (integer) 195 -4 -4 (integer) 196 -5 -5 (integer) 197 -6 -6 (integer) 198 -7 -7 (integer) 199 -8 -8 (integer) 200 -9 -9 (integer) 201 -10 -10 (integer) 202 -11 -11 (integer) 203 -12 -12 (integer) 204 -13 -13 (integer) 205 -14 -14 (integer) 206 -15 -15 (integer) 207 -16 -16 (integer) 208 0.5 0.5 240 -0.5 -0.5 241 1.0 1.0 242 -1.0 -1.0 243 2.0 2.0 244 -2.0 -2.0 245 4.0 4.0 246 -4.0 -4.0 247 0.15915494 1 / (2 * PI). 16-bit: 0x3118, 32-bit: 0x3e22f983, 64-bit: 0x3fc45f30_6dc9c882. 248 src_vccz True if vector condition code is zero. 251 src_execz True if execute mask is zero. 252 src_scc Scalar condition code. 253 src_shared_base 235 src_shared_limit 236 src_private_base 237 src_private_limit 238 src_pops_exiting_wave_id POPS counter (12b). Returns the ID of the most recent wave to complete in-order. 239 OPR_SREG_NONULL s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 OPR_SSRC All scalar operands. Covers all operands that are allowed as scalar sources. s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 exec_lo exec[31:0] 126 exec_hi exec[63:32] 127 0 128 1 1 (integer) 129 2 2 (integer) 130 3 3 (integer) 131 4 4 (integer) 132 5 5 (integer) 133 6 6 (integer) 134 7 7 (integer) 135 8 8 (integer) 136 9 9 (integer) 137 10 10 (integer) 138 11 11 (integer) 139 12 12 (integer) 140 13 13 (integer) 141 14 14 (integer) 142 15 15 (integer) 143 16 16 (integer) 144 17 17 (integer) 145 18 18 (integer) 146 19 19 (integer) 147 20 20 (integer) 148 21 21 (integer) 149 22 22 (integer) 150 23 23 (integer) 151 24 24 (integer) 152 25 25 (integer) 153 26 26 (integer) 154 27 27 (integer) 155 28 28 (integer) 156 29 29 (integer) 157 30 30 (integer) 158 31 31 (integer) 159 32 32 (integer) 160 33 33 (integer) 161 34 34 (integer) 162 35 35 (integer) 163 36 36 (integer) 164 37 37 (integer) 165 38 38 (integer) 166 39 39 (integer) 167 40 40 (integer) 168 41 41 (integer) 169 42 42 (integer) 170 43 43 (integer) 171 44 44 (integer) 172 45 45 (integer) 173 46 46 (integer) 174 47 47 (integer) 175 48 48 (integer) 176 49 49 (integer) 177 50 50 (integer) 178 51 51 (integer) 179 52 52 (integer) 180 53 53 (integer) 181 54 54 (integer) 182 55 55 (integer) 183 56 56 (integer) 184 57 57 (integer) 185 58 58 (integer) 186 59 59 (integer) 187 60 60 (integer) 188 61 61 (integer) 189 62 62 (integer) 190 63 63 (integer) 191 64 64 (integer) 192 -1 -1 (integer) 193 -2 -2 (integer) 194 -3 -3 (integer) 195 -4 -4 (integer) 196 -5 -5 (integer) 197 -6 -6 (integer) 198 -7 -7 (integer) 199 -8 -8 (integer) 200 -9 -9 (integer) 201 -10 -10 (integer) 202 -11 -11 (integer) 203 -12 -12 (integer) 204 -13 -13 (integer) 205 -14 -14 (integer) 206 -15 -15 (integer) 207 -16 -16 (integer) 208 0.5 0.5 240 -0.5 -0.5 241 1.0 1.0 242 -1.0 -1.0 243 2.0 2.0 244 -2.0 -2.0 245 4.0 4.0 246 -4.0 -4.0 247 0.15915494 1 / (2 * PI). 16-bit: 0x3118, 32-bit: 0x3e22f983, 64-bit: 0x3fc45f30_6dc9c882. 248 src_vccz True if vector condition code is zero. 251 src_execz True if execute mask is zero. 252 src_scc Scalar condition code. 253 src_shared_base 235 src_shared_limit 236 src_private_base 237 src_private_limit 238 src_pops_exiting_wave_id POPS counter (12b). Returns the ID of the most recent wave to complete in-order. 239 src_lds_direct Use LDS direct to supply a single 32-bit value to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT. See M0_FMT_LDS_DIRECT structure. Implies OPF_RDM0 when this operand is used. 254 src_literal 32-bit literal constant follows this instruction. 16-bit operands use only the 16 LSBs of this constant. 64-bit unsigned integer operands (U64, B64) zero-extend the constant. 64-bit signed integer operands (I64) sign-extend the constant. 64-bit floating-point operands use the constant as the high 32 MSBs of a double-precision floating point value (1 sign bit, 11 exponent bits and 20 mantissa bits). 255 OPR_SSRC_LANESEL Operand is legal for a lane-select operand, generally scalar integer values in the range 0..63. s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 0 128 1 1 (integer) 129 2 2 (integer) 130 3 3 (integer) 131 4 4 (integer) 132 5 5 (integer) 133 6 6 (integer) 134 7 7 (integer) 135 8 8 (integer) 136 9 9 (integer) 137 10 10 (integer) 138 11 11 (integer) 139 12 12 (integer) 140 13 13 (integer) 141 14 14 (integer) 142 15 15 (integer) 143 16 16 (integer) 144 17 17 (integer) 145 18 18 (integer) 146 19 19 (integer) 147 20 20 (integer) 148 21 21 (integer) 149 22 22 (integer) 150 23 23 (integer) 151 24 24 (integer) 152 25 25 (integer) 153 26 26 (integer) 154 27 27 (integer) 155 28 28 (integer) 156 29 29 (integer) 157 30 30 (integer) 158 31 31 (integer) 159 32 32 (integer) 160 33 33 (integer) 161 34 34 (integer) 162 35 35 (integer) 163 36 36 (integer) 164 37 37 (integer) 165 38 38 (integer) 166 39 39 (integer) 167 40 40 (integer) 168 41 41 (integer) 169 42 42 (integer) 170 43 43 (integer) 171 44 44 (integer) 172 45 45 (integer) 173 46 46 (integer) 174 47 47 (integer) 175 48 48 (integer) 176 49 49 (integer) 177 50 50 (integer) 178 51 51 (integer) 179 52 52 (integer) 180 53 53 (integer) 181 54 54 (integer) 182 55 55 (integer) 183 56 56 (integer) 184 57 57 (integer) 185 58 58 (integer) 186 59 59 (integer) 187 60 60 (integer) 188 61 61 (integer) 189 62 62 (integer) 190 63 63 (integer) 191 OPR_SSRC_NOLDS Simple scalar operands, plus SRC_LITERAL. Covers all operands that are allowed as scalar sources except for SRC_LDS_DIRECT. s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_GFX7_5_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s0 Scalar GPR 0. Increment from here for additional GPRs. There are NUM_SGPR SGPRs in total. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 0 s1 <p>See above.</p> 1 s2 <p>See above.</p> 2 s3 <p>See above.</p> 3 s4 <p>See above.</p> 4 s5 <p>See above.</p> 5 s6 <p>See above.</p> 6 s7 <p>See above.</p> 7 s8 <p>See above.</p> 8 s9 <p>See above.</p> 9 s10 <p>See above.</p> 10 s11 <p>See above.</p> 11 s12 <p>See above.</p> 12 s13 <p>See above.</p> 13 s14 <p>See above.</p> 14 s15 <p>See above.</p> 15 s16 <p>See above.</p> 16 s17 <p>See above.</p> 17 s18 <p>See above.</p> 18 s19 <p>See above.</p> 19 s20 <p>See above.</p> 20 s21 <p>See above.</p> 21 s22 <p>See above.</p> 22 s23 <p>See above.</p> 23 s24 <p>See above.</p> 24 s25 <p>See above.</p> 25 s26 <p>See above.</p> 26 s27 <p>See above.</p> 27 s28 <p>See above.</p> 28 s29 <p>See above.</p> 29 s30 <p>See above.</p> 30 s31 <p>See above.</p> 31 s32 <p>See above.</p> 32 s33 <p>See above.</p> 33 s34 <p>See above.</p> 34 s35 <p>See above.</p> 35 s36 <p>See above.</p> 36 s37 <p>See above.</p> 37 s38 <p>See above.</p> 38 s39 <p>See above.</p> 39 s40 <p>See above.</p> 40 s41 <p>See above.</p> 41 s42 <p>See above.</p> 42 s43 <p>See above.</p> 43 s44 <p>See above.</p> 44 s45 <p>See above.</p> 45 s46 <p>See above.</p> 46 s47 <p>See above.</p> 47 s48 <p>See above.</p> 48 s49 <p>See above.</p> 49 s50 <p>See above.</p> 50 s51 <p>See above.</p> 51 s52 <p>See above.</p> 52 s53 <p>See above.</p> 53 s54 <p>See above.</p> 54 s55 <p>See above.</p> 55 s56 <p>See above.</p> 56 s57 <p>See above.</p> 57 s58 <p>See above.</p> 58 s59 <p>See above.</p> 59 s60 <p>See above.</p> 60 s61 <p>See above.</p> 61 s62 <p>See above.</p> 62 s63 <p>See above.</p> 63 s64 <p>See above.</p> 64 s65 <p>See above.</p> 65 s66 <p>See above.</p> 66 s67 <p>See above.</p> 67 s68 <p>See above.</p> 68 s69 <p>See above.</p> 69 s70 <p>See above.</p> 70 s71 <p>See above.</p> 71 s72 <p>See above.</p> 72 s73 <p>See above.</p> 73 s74 <p>See above.</p> 74 s75 <p>See above.</p> 75 s76 <p>See above.</p> 76 s77 <p>See above.</p> 77 s78 <p>See above.</p> 78 s79 <p>See above.</p> 79 s80 <p>See above.</p> 80 s81 <p>See above.</p> 81 s82 <p>See above.</p> 82 s83 <p>See above.</p> 83 s84 <p>See above.</p> 84 s85 <p>See above.</p> 85 s86 <p>See above.</p> 86 s87 <p>See above.</p> 87 s88 <p>See above.</p> 88 s89 <p>See above.</p> 89 s90 <p>See above.</p> 90 s91 <p>See above.</p> 91 s92 <p>See above.</p> 92 s93 <p>See above.</p> 93 s94 <p>See above.</p> 94 s95 <p>See above.</p> 95 s96 <p>See above.</p> 96 s97 <p>See above.</p> 97 s98 <p>See above.</p> 98 s99 <p>See above.</p> 99 s100 <p>See above.</p> 100 s101 <p>See above.</p> 101 s102 <p>See above.</p> 102 s103 <p>See above.</p> 103 s104 <p>See above.</p> 104 s105 <p>See above.</p> 105 tba_lo Trap handler base address, low 32 bits. 108 tba_hi Trap handler base address, high 32 bits. 109 tma_lo Trap handler memory address, low 32 bits. 110 tma_hi Trap handler memory address, high 32 bits. 111 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 112 ttmp1 Trap handler temps (privileged). 113 ttmp2 Trap handler temps (privileged). 114 ttmp3 Trap handler temps (privileged). 115 ttmp4 Trap handler temps (privileged). 116 ttmp5 Trap handler temps (privileged). 117 ttmp6 Trap handler temps (privileged). 118 ttmp7 Trap handler temps (privileged). 119 ttmp8 Trap handler temps (privileged). 120 ttmp9 Trap handler temps (privileged). 121 ttmp10 Trap handler temps (privileged). 122 ttmp11 Trap handler temps (privileged). 123 ttmp0 Trap handler temps (privileged). Increment from here for additional TTMPs. There are NUM_TTMP TTMPs in total. {TTMP1,TTMP0} = PC_save{hi,lo}. Alignment restriction: unless otherwise noted, 64-bit SGPR values must be even-aligned (first SGPR address is even); 128-bit and wider SGPR values must be aligned to a multiple of 4. 108 ttmp1 Trap handler temps (privileged). 109 ttmp2 Trap handler temps (privileged). 110 ttmp3 Trap handler temps (privileged). 111 ttmp4 Trap handler temps (privileged). 112 ttmp5 Trap handler temps (privileged). 113 ttmp6 Trap handler temps (privileged). 114 ttmp7 Trap handler temps (privileged). 115 ttmp8 Trap handler temps (privileged). 116 ttmp9 Trap handler temps (privileged). 117 ttmp10 Trap handler temps (privileged). 118 ttmp11 Trap handler temps (privileged). 119 ttmp12 Trap handler temps (privileged). 120 ttmp13 Trap handler temps (privileged). 121 ttmp14 Trap handler temps (privileged). 122 ttmp15 Trap handler temps (privileged). 123 flat_scratch_lo flat_scratch[31:0] 104 flat_scratch_hi flat_scratch[63:32] 105 vcc_lo VCC[31:0] 106 vcc_hi VCC[63:32] 107 null Do not write destination. For scalar memory, do not use SOFFSET in address calculation. For scratch addressing, do not use an SGPR in the addressing calculation. Otherwise read back zero. 125 m0 Special register used to hold LDS/GDS addresses, relative indices, and send-message values. 124 exec_lo exec[31:0] 126 exec_hi exec[63:32] 127 0 128 1 1 (integer) 129 2 2 (integer) 130 3 3 (integer) 131 4 4 (integer) 132 5 5 (integer) 133 6 6 (integer) 134 7 7 (integer) 135 8 8 (integer) 136 9 9 (integer) 137 10 10 (integer) 138 11 11 (integer) 139 12 12 (integer) 140 13 13 (integer) 141 14 14 (integer) 142 15 15 (integer) 143 16 16 (integer) 144 17 17 (integer) 145 18 18 (integer) 146 19 19 (integer) 147 20 20 (integer) 148 21 21 (integer) 149 22 22 (integer) 150 23 23 (integer) 151 24 24 (integer) 152 25 25 (integer) 153 26 26 (integer) 154 27 27 (integer) 155 28 28 (integer) 156 29 29 (integer) 157 30 30 (integer) 158 31 31 (integer) 159 32 32 (integer) 160 33 33 (integer) 161 34 34 (integer) 162 35 35 (integer) 163 36 36 (integer) 164 37 37 (integer) 165 38 38 (integer) 166 39 39 (integer) 167 40 40 (integer) 168 41 41 (integer) 169 42 42 (integer) 170 43 43 (integer) 171 44 44 (integer) 172 45 45 (integer) 173 46 46 (integer) 174 47 47 (integer) 175 48 48 (integer) 176 49 49 (integer) 177 50 50 (integer) 178 51 51 (integer) 179 52 52 (integer) 180 53 53 (integer) 181 54 54 (integer) 182 55 55 (integer) 183 56 56 (integer) 184 57 57 (integer) 185 58 58 (integer) 186 59 59 (integer) 187 60 60 (integer) 188 61 61 (integer) 189 62 62 (integer) 190 63 63 (integer) 191 64 64 (integer) 192 -1 -1 (integer) 193 -2 -2 (integer) 194 -3 -3 (integer) 195 -4 -4 (integer) 196 -5 -5 (integer) 197 -6 -6 (integer) 198 -7 -7 (integer) 199 -8 -8 (integer) 200 -9 -9 (integer) 201 -10 -10 (integer) 202 -11 -11 (integer) 203 -12 -12 (integer) 204 -13 -13 (integer) 205 -14 -14 (integer) 206 -15 -15 (integer) 207 -16 -16 (integer) 208 0.5 0.5 240 -0.5 -0.5 241 1.0 1.0 242 -1.0 -1.0 243 2.0 2.0 244 -2.0 -2.0 245 4.0 4.0 246 -4.0 -4.0 247 0.15915494 1 / (2 * PI). 16-bit: 0x3118, 32-bit: 0x3e22f983, 64-bit: 0x3fc45f30_6dc9c882. 248 src_vccz True if vector condition code is zero. 251 src_execz True if execute mask is zero. 252 src_scc Scalar condition code. 253 src_shared_base 235 src_shared_limit 236 src_private_base 237 src_private_limit 238 src_pops_exiting_wave_id POPS counter (12b). Returns the ID of the most recent wave to complete in-order. 239 src_literal 32-bit literal constant follows this instruction. 16-bit operands use only the 16 LSBs of this constant. 64-bit unsigned integer operands (U64, B64) zero-extend the constant. 64-bit signed integer operands (I64) sign-extend the constant. 64-bit floating-point operands use the constant as the high 32 MSBs of a double-precision floating point value (1 sign bit, 11 exponent bits and 20 mantissa bits). 255 OPR_SSRC_SPECIAL_SCC src_scc Scalar condition code. 253 OPR_TGT mrt0 Output to colour MRT 0. Increment from here for additional MRTs. There are EXP_NUM_MRT MRTs in total. 0 mrt1 <p>See above.</p> 1 mrt2 <p>See above.</p> 2 mrt3 <p>See above.</p> 3 mrt4 <p>See above.</p> 4 mrt5 <p>See above.</p> 5 mrt6 <p>See above.</p> 6 mrt7 <p>See above.</p> 7 mrtz Output to Z. 8 null Output to NULL. 9 pos0 Output to position 0. Increment from here for additional positions. There are EXP_NUM_POS positions in total. POS4 (the last one) is for stereo rendering. 12 pos1 <p>See above.</p> 13 pos2 <p>See above.</p> 14 pos3 <p>See above.</p> 15 pos4 <p>See above.</p> 16 prim Output NGG primitive (connectivity) data. 20 param0 Output to parameter 0. Increment from here for additional parameters. There are EXP_NUM_PARAM parameters in total. 32 param1 <p>See above.</p> 33 param2 <p>See above.</p> 34 param3 <p>See above.</p> 35 param4 <p>See above.</p> 36 param5 <p>See above.</p> 37 param6 <p>See above.</p> 38 param7 <p>See above.</p> 39 param8 <p>See above.</p> 40 param9 <p>See above.</p> 41 param10 <p>See above.</p> 42 param11 <p>See above.</p> 43 param12 <p>See above.</p> 44 param13 <p>See above.</p> 45 param14 <p>See above.</p> 46 param15 <p>See above.</p> 47 param16 <p>See above.</p> 48 param17 <p>See above.</p> 49 param18 <p>See above.</p> 50 param19 <p>See above.</p> 51 param20 <p>See above.</p> 52 param21 <p>See above.</p> 53 param22 <p>See above.</p> 54 param23 <p>See above.</p> 55 param24 <p>See above.</p> 56 param25 <p>See above.</p> 57 param26 <p>See above.</p> 58 param27 <p>See above.</p> 59 param28 <p>See above.</p> 60 param29 <p>See above.</p> 61 param30 <p>See above.</p> 62 param31 <p>See above.</p> 63 OPR_VCC vcc VCC[63:0] 106 OPR_VERSION Microcode version header. MDP 1 15 VERSION Version number. 8 0 uc_version_gfx7 0 uc_version_gfx7_5 2 uc_version_gfx10 Baseline microcode for GFX10.0. 4 W32 1 14 W64 1 13 OPR_VGPR Operand must be a vector GPR. Uses an 8-bit operand field. v0 Vector GPR 0. Increment from here for additional GPRs. There are NUM_VGPR VGPRs in total. 0 v1 <p>See above.</p> 1 v2 <p>See above.</p> 2 v3 <p>See above.</p> 3 v4 <p>See above.</p> 4 v5 <p>See above.</p> 5 v6 <p>See above.</p> 6 v7 <p>See above.</p> 7 v8 <p>See above.</p> 8 v9 <p>See above.</p> 9 v10 <p>See above.</p> 10 v11 <p>See above.</p> 11 v12 <p>See above.</p> 12 v13 <p>See above.</p> 13 v14 <p>See above.</p> 14 v15 <p>See above.</p> 15 v16 <p>See above.</p> 16 v17 <p>See above.</p> 17 v18 <p>See above.</p> 18 v19 <p>See above.</p> 19 v20 <p>See above.</p> 20 v21 <p>See above.</p> 21 v22 <p>See above.</p> 22 v23 <p>See above.</p> 23 v24 <p>See above.</p> 24 v25 <p>See above.</p> 25 v26 <p>See above.</p> 26 v27 <p>See above.</p> 27 v28 <p>See above.</p> 28 v29 <p>See above.</p> 29 v30 <p>See above.</p> 30 v31 <p>See above.</p> 31 v32 <p>See above.</p> 32 v33 <p>See above.</p> 33 v34 <p>See above.</p> 34 v35 <p>See above.</p> 35 v36 <p>See above.</p> 36 v37 <p>See above.</p> 37 v38 <p>See above.</p> 38 v39 <p>See above.</p> 39 v40 <p>See above.</p> 40 v41 <p>See above.</p> 41 v42 <p>See above.</p> 42 v43 <p>See above.</p> 43 v44 <p>See above.</p> 44 v45 <p>See above.</p> 45 v46 <p>See above.</p> 46 v47 <p>See above.</p> 47 v48 <p>See above.</p> 48 v49 <p>See above.</p> 49 v50 <p>See above.</p> 50 v51 <p>See above.</p> 51 v52 <p>See above.</p> 52 v53 <p>See above.</p> 53 v54 <p>See above.</p> 54 v55 <p>See above.</p> 55 v56 <p>See above.</p> 56 v57 <p>See above.</p> 57 v58 <p>See above.</p> 58 v59 <p>See above.</p> 59 v60 <p>See above.</p> 60 v61 <p>See above.</p> 61 v62 <p>See above.</p> 62 v63 <p>See above.</p> 63 v64 <p>See above.</p> 64 v65 <p>See above.</p> 65 v66 <p>See above.</p> 66 v67 <p>See above.</p> 67 v68 <p>See above.</p> 68 v69 <p>See above.</p> 69 v70 <p>See above.</p> 70 v71 <p>See above.</p> 71 v72 <p>See above.</p> 72 v73 <p>See above.</p> 73 v74 <p>See above.</p> 74 v75 <p>See above.</p> 75 v76 <p>See above.</p> 76 v77 <p>See above.</p> 77 v78 <p>See above.</p> 78 v79 <p>See above.</p> 79 v80 <p>See above.</p> 80 v81 <p>See above.</p> 81 v82 <p>See above.</p> 82 v83 <p>See above.</p> 83 v84 <p>See above.</p> 84 v85 <p>See above.</p> 85 v86 <p>See above.</p> 86 v87 <p>See above.</p> 87 v88 <p>See above.</p> 88 v89 <p>See above.</p> 89 v90 <p>See above.</p> 90 v91 <p>See above.</p> 91 v92 <p>See above.</p> 92 v93 <p>See above.</p> 93 v94 <p>See above.</p> 94 v95 <p>See above.</p> 95 v96 <p>See above.</p> 96 v97 <p>See above.</p> 97 v98 <p>See above.</p> 98 v99 <p>See above.</p> 99 v100 <p>See above.</p> 100 v101 <p>See above.</p> 101 v102 <p>See above.</p> 102 v103 <p>See above.</p> 103 v104 <p>See above.</p> 104 v105 <p>See above.</p> 105 v106 <p>See above.</p> 106 v107 <p>See above.</p> 107 v108 <p>See above.</p> 108 v109 <p>See above.</p> 109 v110 <p>See above.</p> 110 v111 <p>See above.</p> 111 v112 <p>See above.</p> 112 v113 <p>See above.</p> 113 v114 <p>See above.</p> 114 v115 <p>See above.</p> 115 v116 <p>See above.</p> 116 v117 <p>See above.</p> 117 v118 <p>See above.</p> 118 v119 <p>See above.</p> 119 v120 <p>See above.</p> 120 v121 <p>See above.</p> 121 v122 <p>See above.</p> 122 v123 <p>See above.</p> 123 v124 <p>See above.</p> 124 v125 <p>See above.</p> 125 v126 <p>See above.</p> 126 v127 <p>See above.</p> 127 v128 <p>See above.</p> 128 v129 <p>See above.</p> 129 v130 <p>See above.</p> 130 v131 <p>See above.</p> 131 v132 <p>See above.</p> 132 v133 <p>See above.</p> 133 v134 <p>See above.</p> 134 v135 <p>See above.</p> 135 v136 <p>See above.</p> 136 v137 <p>See above.</p> 137 v138 <p>See above.</p> 138 v139 <p>See above.</p> 139 v140 <p>See above.</p> 140 v141 <p>See above.</p> 141 v142 <p>See above.</p> 142 v143 <p>See above.</p> 143 v144 <p>See above.</p> 144 v145 <p>See above.</p> 145 v146 <p>See above.</p> 146 v147 <p>See above.</p> 147 v148 <p>See above.</p> 148 v149 <p>See above.</p> 149 v150 <p>See above.</p> 150 v151 <p>See above.</p> 151 v152 <p>See above.</p> 152 v153 <p>See above.</p> 153 v154 <p>See above.</p> 154 v155 <p>See above.</p> 155 v156 <p>See above.</p> 156 v157 <p>See above.</p> 157 v158 <p>See above.</p> 158 v159 <p>See above.</p> 159 v160 <p>See above.</p> 160 v161 <p>See above.</p> 161 v162 <p>See above.</p> 162 v163 <p>See above.</p> 163 v164 <p>See above.</p> 164 v165 <p>See above.</p> 165 v166 <p>See above.</p> 166 v167 <p>See above.</p> 167 v168 <p>See above.</p> 168 v169 <p>See above.</p> 169 v170 <p>See above.</p> 170 v171 <p>See above.</p> 171 v172 <p>See above.</p> 172 v173 <p>See above.</p> 173 v174 <p>See above.</p> 174 v175 <p>See above.</p> 175 v176 <p>See above.</p> 176 v177 <p>See above.</p> 177 v178 <p>See above.</p> 178 v179 <p>See above.</p> 179 v180 <p>See above.</p> 180 v181 <p>See above.</p> 181 v182 <p>See above.</p> 182 v183 <p>See above.</p> 183 v184 <p>See above.</p> 184 v185 <p>See above.</p> 185 v186 <p>See above.</p> 186 v187 <p>See above.</p> 187 v188 <p>See above.</p> 188 v189 <p>See above.</p> 189 v190 <p>See above.</p> 190 v191 <p>See above.</p> 191 v192 <p>See above.</p> 192 v193 <p>See above.</p> 193 v194 <p>See above.</p> 194 v195 <p>See above.</p> 195 v196 <p>See above.</p> 196 v197 <p>See above.</p> 197 v198 <p>See above.</p> 198 v199 <p>See above.</p> 199 v200 <p>See above.</p> 200 v201 <p>See above.</p> 201 v202 <p>See above.</p> 202 v203 <p>See above.</p> 203 v204 <p>See above.</p> 204 v205 <p>See above.</p> 205 v206 <p>See above.</p> 206 v207 <p>See above.</p> 207 v208 <p>See above.</p> 208 v209 <p>See above.</p> 209 v210 <p>See above.</p> 210 v211 <p>See above.</p> 211 v212 <p>See above.</p> 212 v213 <p>See above.</p> 213 v214 <p>See above.</p> 214 v215 <p>See above.</p> 215 v216 <p>See above.</p> 216 v217 <p>See above.</p> 217 v218 <p>See above.</p> 218 v219 <p>See above.</p> 219 v220 <p>See above.</p> 220 v221 <p>See above.</p> 221 v222 <p>See above.</p> 222 v223 <p>See above.</p> 223 v224 <p>See above.</p> 224 v225 <p>See above.</p> 225 v226 <p>See above.</p> 226 v227 <p>See above.</p> 227 v228 <p>See above.</p> 228 v229 <p>See above.</p> 229 v230 <p>See above.</p> 230 v231 <p>See above.</p> 231 v232 <p>See above.</p> 232 v233 <p>See above.</p> 233 v234 <p>See above.</p> 234 v235 <p>See above.</p> 235 v236 <p>See above.</p> 236 v237 <p>See above.</p> 237 v238 <p>See above.</p> 238 v239 <p>See above.</p> 239 v240 <p>See above.</p> 240 v241 <p>See above.</p> 241 v242 <p>See above.</p> 242 v243 <p>See above.</p> 243 v244 <p>See above.</p> 244 v245 <p>See above.</p> 245 v246 <p>See above.</p> 246 v247 <p>See above.</p> 247 v248 <p>See above.</p> 248 v249 <p>See above.</p> 249 v250 <p>See above.</p> 250 v251 <p>See above.</p> 251 v252 <p>See above.</p> 252 v253 <p>See above.</p> 253 v254 <p>See above.</p> 254 v255 <p>See above.</p> 255 OPR_VGPR_OR_LDS Operand must be a vector GPR or SRC_SPECIAL_LDS. Uses a 9-bit operand field. src_lds_direct Use LDS direct to supply a single 32-bit value to all lanes. A single DWORD is read from LDS memory at ADDR[M0[15:0]], where M0[15:0] is a byte address and is dword-aligned. M0[18:16] specify the data type for the read and may be 0=UBYTE, 1=USHORT, 2=DWORD, 4=SBYTE, 5=SSHORT. See M0_FMT_LDS_DIRECT structure. Implies OPF_RDM0 when this operand is used. 254 v0 Vector GPR 0. Increment from here for additional GPRs. There are NUM_VGPR VGPRs in total. Use the constant SQ_SRC_VGPR_BIT to set or clear the high order bit for vector GPRs in this operand. 256 v1 <p>See above.</p> 257 v2 <p>See above.</p> 258 v3 <p>See above.</p> 259 v4 <p>See above.</p> 260 v5 <p>See above.</p> 261 v6 <p>See above.</p> 262 v7 <p>See above.</p> 263 v8 <p>See above.</p> 264 v9 <p>See above.</p> 265 v10 <p>See above.</p> 266 v11 <p>See above.</p> 267 v12 <p>See above.</p> 268 v13 <p>See above.</p> 269 v14 <p>See above.</p> 270 v15 <p>See above.</p> 271 v16 <p>See above.</p> 272 v17 <p>See above.</p> 273 v18 <p>See above.</p> 274 v19 <p>See above.</p> 275 v20 <p>See above.</p> 276 v21 <p>See above.</p> 277 v22 <p>See above.</p> 278 v23 <p>See above.</p> 279 v24 <p>See above.</p> 280 v25 <p>See above.</p> 281 v26 <p>See above.</p> 282 v27 <p>See above.</p> 283 v28 <p>See above.</p> 284 v29 <p>See above.</p> 285 v30 <p>See above.</p> 286 v31 <p>See above.</p> 287 v32 <p>See above.</p> 288 v33 <p>See above.</p> 289 v34 <p>See above.</p> 290 v35 <p>See above.</p> 291 v36 <p>See above.</p> 292 v37 <p>See above.</p> 293 v38 <p>See above.</p> 294 v39 <p>See above.</p> 295 v40 <p>See above.</p> 296 v41 <p>See above.</p> 297 v42 <p>See above.</p> 298 v43 <p>See above.</p> 299 v44 <p>See above.</p> 300 v45 <p>See above.</p> 301 v46 <p>See above.</p> 302 v47 <p>See above.</p> 303 v48 <p>See above.</p> 304 v49 <p>See above.</p> 305 v50 <p>See above.</p> 306 v51 <p>See above.</p> 307 v52 <p>See above.</p> 308 v53 <p>See above.</p> 309 v54 <p>See above.</p> 310 v55 <p>See above.</p> 311 v56 <p>See above.</p> 312 v57 <p>See above.</p> 313 v58 <p>See above.</p> 314 v59 <p>See above.</p> 315 v60 <p>See above.</p> 316 v61 <p>See above.</p> 317 v62 <p>See above.</p> 318 v63 <p>See above.</p> 319 v64 <p>See above.</p> 320 v65 <p>See above.</p> 321 v66 <p>See above.</p> 322 v67 <p>See above.</p> 323 v68 <p>See above.</p> 324 v69 <p>See above.</p> 325 v70 <p>See above.</p> 326 v71 <p>See above.</p> 327 v72 <p>See above.</p> 328 v73 <p>See above.</p> 329 v74 <p>See above.</p> 330 v75 <p>See above.</p> 331 v76 <p>See above.</p> 332 v77 <p>See above.</p> 333 v78 <p>See above.</p> 334 v79 <p>See above.</p> 335 v80 <p>See above.</p> 336 v81 <p>See above.</p> 337 v82 <p>See above.</p> 338 v83 <p>See above.</p> 339 v84 <p>See above.</p> 340 v85 <p>See above.</p> 341 v86 <p>See above.</p> 342 v87 <p>See above.</p> 343 v88 <p>See above.</p> 344 v89 <p>See above.</p> 345 v90 <p>See above.</p> 346 v91 <p>See above.</p> 347 v92 <p>See above.</p> 348 v93 <p>See above.</p> 349 v94 <p>See above.</p> 350 v95 <p>See above.</p> 351 v96 <p>See above.</p> 352 v97 <p>See above.</p> 353 v98 <p>See above.</p> 354 v99 <p>See above.</p> 355 v100 <p>See above.</p> 356 v101 <p>See above.</p> 357 v102 <p>See above.</p> 358 v103 <p>See above.</p> 359 v104 <p>See above.</p> 360 v105 <p>See above.</p> 361 v106 <p>See above.</p> 362 v107 <p>See above.</p> 363 v108 <p>See above.</p> 364 v109 <p>See above.</p> 365 v110 <p>See above.</p> 366 v111 <p>See above.</p> 367 v112 <p>See above.</p> 368 v113 <p>See above.</p> 369 v114 <p>See above.</p> 370 v115 <p>See above.</p> 371 v116 <p>See above.</p> 372 v117 <p>See above.</p> 373 v118 <p>See above.</p> 374 v119 <p>See above.</p> 375 v120 <p>See above.</p> 376 v121 <p>See above.</p> 377 v122 <p>See above.</p> 378 v123 <p>See above.</p> 379 v124 <p>See above.</p> 380 v125 <p>See above.</p> 381 v126 <p>See above.</p> 382 v127 <p>See above.</p> 383 v128 <p>See above.</p> 384 v129 <p>See above.</p> 385 v130 <p>See above.</p> 386 v131 <p>See above.</p> 387 v132 <p>See above.</p> 388 v133 <p>See above.</p> 389 v134 <p>See above.</p> 390 v135 <p>See above.</p> 391 v136 <p>See above.</p> 392 v137 <p>See above.</p> 393 v138 <p>See above.</p> 394 v139 <p>See above.</p> 395 v140 <p>See above.</p> 396 v141 <p>See above.</p> 397 v142 <p>See above.</p> 398 v143 <p>See above.</p> 399 v144 <p>See above.</p> 400 v145 <p>See above.</p> 401 v146 <p>See above.</p> 402 v147 <p>See above.</p> 403 v148 <p>See above.</p> 404 v149 <p>See above.</p> 405 v150 <p>See above.</p> 406 v151 <p>See above.</p> 407 v152 <p>See above.</p> 408 v153 <p>See above.</p> 409 v154 <p>See above.</p> 410 v155 <p>See above.</p> 411 v156 <p>See above.</p> 412 v157 <p>See above.</p> 413 v158 <p>See above.</p> 414 v159 <p>See above.</p> 415 v160 <p>See above.</p> 416 v161 <p>See above.</p> 417 v162 <p>See above.</p> 418 v163 <p>See above.</p> 419 v164 <p>See above.</p> 420 v165 <p>See above.</p> 421 v166 <p>See above.</p> 422 v167 <p>See above.</p> 423 v168 <p>See above.</p> 424 v169 <p>See above.</p> 425 v170 <p>See above.</p> 426 v171 <p>See above.</p> 427 v172 <p>See above.</p> 428 v173 <p>See above.</p> 429 v174 <p>See above.</p> 430 v175 <p>See above.</p> 431 v176 <p>See above.</p> 432 v177 <p>See above.</p> 433 v178 <p>See above.</p> 434 v179 <p>See above.</p> 435 v180 <p>See above.</p> 436 v181 <p>See above.</p> 437 v182 <p>See above.</p> 438 v183 <p>See above.</p> 439 v184 <p>See above.</p> 440 v185 <p>See above.</p> 441 v186 <p>See above.</p> 442 v187 <p>See above.</p> 443 v188 <p>See above.</p> 444 v189 <p>See above.</p> 445 v190 <p>See above.</p> 446 v191 <p>See above.</p> 447 v192 <p>See above.</p> 448 v193 <p>See above.</p> 449 v194 <p>See above.</p> 450 v195 <p>See above.</p> 451 v196 <p>See above.</p> 452 v197 <p>See above.</p> 453 v198 <p>See above.</p> 454 v199 <p>See above.</p> 455 v200 <p>See above.</p> 456 v201 <p>See above.</p> 457 v202 <p>See above.</p> 458 v203 <p>See above.</p> 459 v204 <p>See above.</p> 460 v205 <p>See above.</p> 461 v206 <p>See above.</p> 462 v207 <p>See above.</p> 463 v208 <p>See above.</p> 464 v209 <p>See above.</p> 465 v210 <p>See above.</p> 466 v211 <p>See above.</p> 467 v212 <p>See above.</p> 468 v213 <p>See above.</p> 469 v214 <p>See above.</p> 470 v215 <p>See above.</p> 471 v216 <p>See above.</p> 472 v217 <p>See above.</p> 473 v218 <p>See above.</p> 474 v219 <p>See above.</p> 475 v220 <p>See above.</p> 476 v221 <p>See above.</p> 477 v222 <p>See above.</p> 478 v223 <p>See above.</p> 479 v224 <p>See above.</p> 480 v225 <p>See above.</p> 481 v226 <p>See above.</p> 482 v227 <p>See above.</p> 483 v228 <p>See above.</p> 484 v229 <p>See above.</p> 485 v230 <p>See above.</p> 486 v231 <p>See above.</p> 487 v232 <p>See above.</p> 488 v233 <p>See above.</p> 489 v234 <p>See above.</p> 490 v235 <p>See above.</p> 491 v236 <p>See above.</p> 492 v237 <p>See above.</p> 493 v238 <p>See above.</p> 494 v239 <p>See above.</p> 495 v240 <p>See above.</p> 496 v241 <p>See above.</p> 497 v242 <p>See above.</p> 498 v243 <p>See above.</p> 499 v244 <p>See above.</p> 500 v245 <p>See above.</p> 501 v246 <p>See above.</p> 502 v247 <p>See above.</p> 503 v248 <p>See above.</p> 504 v249 <p>See above.</p> 505 v250 <p>See above.</p> 506 v251 <p>See above.</p> 507 v252 <p>See above.</p> 508 v253 <p>See above.</p> 509 v254 <p>See above.</p> 510 v255 <p>See above.</p> 511 OPR_WAITCNT A waitcnt operand specifying expcnt, lgkmcnt and vmcnt. EXP 3 4 LGKM 6 8 VM 4 0 VM_HI 2 14 OPR_WAITCNT_DEPCTR A waitcnt operand for ALU and miscellaneous dependency counters. SA_SDST Wait for SA_SDST <= N (N = 1 disables check). 1 0 VA_SDST Wait for VA_SDST <= N (N = 7 disables check). 3 9 VA_SSRC Wait for VA_SSRC <= N (N = 1 disables check). 1 8 VA_VCC Wait for VA_VCC <= N (N = 1 disables check). 1 1 VA_VDST Wait for VA_VDST <= N (N = 15 disables check). 4 12 VM_VSRC Wait for VM_VSRC <= N (N = 7 disables check). 3 2 SALU Scalar ALU (SALU) instructions operate on values that are common to all work-items in the wave. These operations consist of 32-bit integer or floating-point arithmetic, and 32 or 64-bit bitwise operations, and they store results in scalar registers. SMEM Scalar Memory (SMEM) instructions allow a shader program to load data from memory into scalar registers, making the data accessible to all work-items in the wave. VALU Vector ALU (VALU) instructions perform arithmetic or logical operations on data for each of the wave's work-item and write results back to vector registers, scalar registers or the EXEC mask. VMEM Vector-memory (VMEM) instructions transfer data to and from vector registers, making the data uniquely available for each work-item in the wave. EXPORT Export instructions copy data from a VGPR to one of the export buffers (position, color, or Z). BRANCH Branch instructions allow programs to jump - direct or indirect - to an instruction to be executed next, conditionally or unconditionally. MESSAGE Message instructions send a message to fixed function hardware or the host and can be used to request that a value be returned to the wave. WAVE_CONTROL Wave control instructions control a wave's execution these include dependency, delay, scheduling, and wave termination operations. TRAP Trap instructions transition into and out of the wave's trap handler FLOATING_POINT BUFFER TEXTURE LOAD STORE SAMPLE BVH ATOMIC FLAT DATA_SHARE STATIC