# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -instruction-tables=full -iterations=1 < %s | FileCheck %s # The legal (SEW, LMUL) pairs are: # (e8, mf8) (e8, mf4) (e8, mf2) (e8, m1) (e8, m2) (e8, m4) (e8, m8) # (e16, mf4) (e16, mf2) (e16, m1) (e16, m2) (e16, m4) (e16, m8) # (e32, mf2) (e32, m1) (e32, m2) (e32, m4) (e32, m8) # (e64, m1) (e64, m2) (e64, m4) (e64, m8) vsetvli zero, zero, e8, mf8, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e8, mf4, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e8, mf2, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e8, m1, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e8, m2, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e8, m4, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e8, m8, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e16, mf4, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e16, mf2, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e16, m1, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e16, m2, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e16, m4, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e16, m8, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e32, mf2, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e32, m1, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e32, m2, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e32, m4, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e32, m8, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e64, m1, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e64, m2, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e64, m4, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 vsetvli zero, zero, e64, m8, tu, mu vrgather.vv v8, v16, v24 vrgatherei16.vv v8, v16, v24 vcompress.vm v8, v16, v24 # CHECK: Resources: # CHECK-NEXT: [0] - VLEN512SiFive7FDiv:1 # CHECK-NEXT: [1] - VLEN512SiFive7IDiv:1 # CHECK-NEXT: [2] - VLEN512SiFive7PipeA:1 # CHECK-NEXT: [3] - VLEN512SiFive7PipeAB:2 VLEN512SiFive7PipeA, VLEN512SiFive7PipeB # CHECK-NEXT: [4] - VLEN512SiFive7PipeB:1 # CHECK-NEXT: [5] - VLEN512SiFive7VA1:1 # CHECK-NEXT: [6] - VLEN512SiFive7VCQ:1 # CHECK-NEXT: [7] - VLEN512SiFive7VL:1 # CHECK-NEXT: [8] - VLEN512SiFive7VS:1 # CHECK: Instruction Info: # CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [2]: Latency # CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [7]: Bypass Latency # CHECK-NEXT: [8]: Resources ( | [] | [,